From: Ludwig Maier Date: Thu, 21 Aug 2014 13:06:32 +0000 (+0200) Subject: Revert "tmp" X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5dd0b84ff93866e424ff0da4e915a926f57d1113;p=trb3.git Revert "tmp" This reverts commit 672296921838807221744f6883117ff0a4bc022a. --- diff --git a/nxyter/nodelist.txt b/nxyter/nodelist.txt index 756c1ad..74db793 100755 --- a/nxyter/nodelist.txt +++ b/nxyter/nodelist.txt @@ -1,3 +1,18 @@ +[c2] +system = linux +corenum = 4 +env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[c3] +system = linux +corenum = 4 +env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ +[c4] +system = linux +corenum = 4 +env = /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env +workdir = /home/rich/TRB/nXyter/trb3/nxyter/workdir/ [c5] system = linux corenum = 4 diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 268b591..fa2638b 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -47,6 +47,10 @@ entity adc_ad9228 is ADC0_LOCKED_OUT : out std_logic; ADC1_LOCKED_OUT : out std_logic; + ERROR_ADC0_OUT : out std_logic; + ERROR_ADC1_OUT : out std_logic; + ERROR_UNDEF_ADC0_OUT : out std_logic; + ERROR_UNDEF_ADC1_OUT : out std_logic; DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -77,10 +81,7 @@ architecture Behavioral of adc_ad9228 is signal adc0_data_m : adc_data_t; signal adc0_data_clk_m : std_logic; - - signal adc0_data_m_f : adc_data_t; - signal adc0_data_clk_m_f : std_logic; - + signal adc0_byte_status : BYTE_STATUS; signal adc0_byte_status_last : BYTE_STATUS; @@ -115,7 +116,7 @@ architecture Behavioral of adc_ad9228 is signal adc0_locked_ff : std_logic; signal adc0_locked_f : std_logic; signal adc0_locked_o : std_logic; - + signal adc1_fifo_empty : std_logic; signal adc1_fifo_full : std_logic; signal adc1_write_enable : std_logic; @@ -127,17 +128,9 @@ architecture Behavioral of adc_ad9228 is signal adc1_locked_o : std_logic; -- Error - signal error_adc0_ff : std_logic; - signal error_adc0_f : std_logic; signal error_adc0_o : std_logic; - signal error_adc1_ff : std_logic; - signal error_adc1_f : std_logic; signal error_adc1_o : std_logic; - signal error_undef_adc0_ff : std_logic; - signal error_undef_adc0_f : std_logic; signal error_undef_adc0_o : std_logic; - signal error_undef_adc1_ff : std_logic; - signal error_undef_adc1_f : std_logic; signal error_undef_adc1_o : std_logic; -- Output @@ -172,59 +165,32 @@ architecture Behavioral of adc_ad9228 is -- attribute syn_keep : boolean; + attribute syn_keep of q_0_ff : signal is true; + attribute syn_keep of q_0_f : signal is true; + attribute syn_keep of q_1_ff : signal is true; + attribute syn_keep of q_1_f : signal is true; - attribute syn_keep of q_0_ff : signal is true; - attribute syn_keep of q_0_f : signal is true; - attribute syn_keep of q_1_ff : signal is true; - attribute syn_keep of q_1_f : signal is true; + attribute syn_keep of adc0_locked_ff : signal is true; + attribute syn_keep of adc0_locked_f : signal is true; + attribute syn_keep of adc1_locked_ff : signal is true; + attribute syn_keep of adc1_locked_f : signal is true; - attribute syn_keep of adc0_locked_ff : signal is true; - attribute syn_keep of adc0_locked_f : signal is true; - attribute syn_keep of adc1_locked_ff : signal is true; - attribute syn_keep of adc1_locked_f : signal is true; - - attribute syn_keep of adc0_data_m_f : signal is true; - attribute syn_keep of adc0_data_clk_m_f : signal is true; - --- attribute syn_keep of error_adc0_ff : signal is true; --- attribute syn_keep of error_adc0_f : signal is true; --- attribute syn_keep of error_adc1_ff : signal is true; --- attribute syn_keep of error_adc1_f : signal is true; --- --- attribute syn_keep of error_undef_adc0_ff : signal is true; --- attribute syn_keep of error_undef_adc0_f : signal is true; --- attribute syn_keep of error_undef_adc1_ff : signal is true; --- attribute syn_keep of error_undef_adc1_f : signal is true; - - attribute syn_keep of RESET_ADC0_CLKD_F : signal is true; - attribute syn_keep of RESET_ADC0_CLKD : signal is true; - attribute syn_keep of RESET_ADC1_CLKD_F : signal is true; - attribute syn_keep of RESET_ADC1_CLKD : signal is true; + attribute syn_keep of RESET_ADC0_CLKD_F : signal is true; + attribute syn_keep of RESET_ADC0_CLKD : signal is true; + attribute syn_keep of RESET_ADC1_CLKD_F : signal is true; + attribute syn_keep of RESET_ADC1_CLKD : signal is true; attribute syn_preserve : boolean; - attribute syn_preserve of q_0_ff : signal is true; - attribute syn_preserve of q_0_f : signal is true; - attribute syn_preserve of q_1_ff : signal is true; - attribute syn_preserve of q_1_f : signal is true; - - attribute syn_preserve of adc0_locked_ff : signal is true; - attribute syn_preserve of adc0_locked_f : signal is true; - attribute syn_preserve of adc1_locked_ff : signal is true; - attribute syn_preserve of adc1_locked_f : signal is true; - - attribute syn_preserve of adc0_data_m_f : signal is true; - attribute syn_preserve of adc0_data_clk_m_f : signal is true; - --- attribute syn_preserve of error_adc0_ff : signal is true; --- attribute syn_preserve of error_adc0_f : signal is true; --- attribute syn_preserve of error_adc1_ff : signal is true; --- attribute syn_preserve of error_adc1_f : signal is true; --- --- attribute syn_preserve of error_undef_adc0_ff : signal is true; --- attribute syn_preserve of error_undef_adc0_f : signal is true; --- attribute syn_preserve of error_undef_adc1_ff : signal is true; --- attribute syn_preserve of error_undef_adc1_f : signal is true; + attribute syn_preserve of q_0_ff : signal is true; + attribute syn_preserve of q_0_f : signal is true; + attribute syn_preserve of q_1_ff : signal is true; + attribute syn_preserve of q_1_f : signal is true; + attribute syn_preserve of adc0_locked_ff : signal is true; + attribute syn_preserve of adc0_locked_f : signal is true; + attribute syn_preserve of adc1_locked_ff : signal is true; + attribute syn_preserve of adc1_locked_f : signal is true; + attribute syn_preserve of RESET_ADC0_CLKD_F : signal is true; attribute syn_preserve of RESET_ADC0_CLKD : signal is true; attribute syn_preserve of RESET_ADC1_CLKD_F : signal is true; @@ -651,21 +617,18 @@ begin ----------------------------------------------------------------------------- -- Tansfer to CLK_IN ----------------------------------------------------------------------------- - - adc0_data_m_f <= adc0_data_m when rising_edge(DDR_DATA_CLK); - adc0_data_clk_m_f <= adc0_data_clk_m when rising_edge(DDR_DATA_CLK); - + fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc port map ( - Data(11 downto 0) => adc0_data_m_f(0), - Data(23 downto 12) => adc0_data_m_f(1), - Data(35 downto 24) => adc0_data_m_f(2), - Data(47 downto 36) => adc0_data_m_f(3), + Data(11 downto 0) => adc0_data_m(0), + Data(23 downto 12) => adc0_data_m(1), + Data(35 downto 24) => adc0_data_m(2), + Data(47 downto 36) => adc0_data_m(3), WrClock => DDR_DATA_CLK, RdClock => CLK_IN, WrEn => adc0_write_enable, RdEn => adc0_read_enable, - Reset => RESET_ADC0, + Reset => RESET_ADC0_CLKD, RPReset => RESET_ADC0, Q(11 downto 0) => adc0_data_f(0), Q(23 downto 12) => adc0_data_f(1), @@ -676,14 +639,14 @@ begin ); -- Readout Handler - adc0_write_enable <= adc0_data_clk_m_f and not adc0_fifo_full; + adc0_write_enable <= adc0_data_clk_m and not adc0_fifo_full; adc0_read_enable <= not adc0_fifo_empty; PROC_ADC0_FIFO_READ: process(CLK_IN) begin if (rising_edge(CLK_IN)) then adc0_read_enable_t <= adc0_read_enable; - if (RESET_IN = '1') then + if (RESET_ADC0_CLKD = '1') then adc0_read_enable_tt <= '0'; for I in 0 to 3 loop adc0_data_o(I) <= (others => '0'); @@ -717,7 +680,7 @@ begin RdClock => CLK_IN, WrEn => adc1_write_enable, RdEn => adc1_read_enable, - Reset => RESET_ADC1, + Reset => RESET_ADC1_CLKD, RPReset => RESET_ADC1, Q(11 downto 0) => adc1_data_f(0), Q(23 downto 12) => adc1_data_f(1), @@ -734,7 +697,7 @@ begin PROC_ADC1_FIFO_READ: process(CLK_IN) begin if (rising_edge(CLK_IN)) then - if (RESET_IN = '1') then + if (RESET_ADC1_CLKD = '1') then adc1_read_enable_t <= '0'; adc1_read_enable_tt <= '0'; for I in 0 to 3 loop @@ -767,22 +730,58 @@ begin adc1_locked_f <= adc1_locked_ff when rising_edge(CLK_IN); adc1_locked_o <= adc1_locked_f when rising_edge(CLK_IN); - --error_adc0_ff <= adc0_error when rising_edge(CLK_IN); - --error_adc0_f <= error_adc0_ff when rising_edge(CLK_IN); - --error_adc0_o <= error_adc0_f when rising_edge(CLK_IN); - -- - --error_adc1_ff <= adc1_error when rising_edge(CLK_IN); - --error_adc1_f <= error_adc1_ff when rising_edge(CLK_IN); - --error_adc1_o <= error_adc1_f when rising_edge(CLK_IN); - -- - --error_undef_adc0_ff <= adc0_error_undef when rising_edge(CLK_IN); - --error_undef_adc0_f <= error_undef_adc0_ff when rising_edge(CLK_IN); - --error_undef_adc0_o <= error_undef_adc0_f when rising_edge(CLK_IN); - -- - --error_undef_adc1_ff <= adc1_error_undef when rising_edge(CLK_IN); - --error_undef_adc1_f <= error_undef_adc1_ff when rising_edge(CLK_IN); - --error_undef_adc1_o <= error_undef_adc1_f when rising_edge(CLK_IN); + pulse_dtrans_ADC0_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => '0', + PULSE_A_IN => adc0_error, + CLK_B_IN => CLK_IN, + RESET_B_IN => '0', + PULSE_B_OUT => error_adc0_o + ); + + pulse_dtrans_ADC1_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => '0', + PULSE_A_IN => adc1_error, + CLK_B_IN => CLK_IN, + RESET_B_IN => '0', + PULSE_B_OUT => error_adc1_o + ); + + pulse_dtrans_ADC0_ERROR_UNDEF: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => '0', + PULSE_A_IN => adc0_error_undef, + CLK_B_IN => CLK_IN, + RESET_B_IN => '0', + PULSE_B_OUT => error_undef_adc0_o + ); + pulse_dtrans_ADC1_ERROR_UNDEF: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => '0', + PULSE_A_IN => adc1_error_undef, + CLK_B_IN => CLK_IN, + RESET_B_IN => '0', + PULSE_B_OUT => error_undef_adc1_o + ); + -- Output ADC0_SCLK_OUT <= ADC0_SCLK_IN; ADC1_SCLK_OUT <= ADC1_SCLK_IN; @@ -802,4 +801,10 @@ begin ADC0_LOCKED_OUT <= adc0_locked_o; ADC1_LOCKED_OUT <= adc1_locked_o; + ERROR_ADC0_OUT <= error_adc0_o; + ERROR_ADC1_OUT <= error_adc1_o; + + ERROR_UNDEF_ADC0_OUT <= error_undef_adc0_o; + ERROR_UNDEF_ADC1_OUT <= error_undef_adc1_o; + end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 9458c50..115c0cd 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -153,9 +153,7 @@ architecture Behavioral of nx_data_receiver is -- Merge Data Streams signal merge_handler_reset_i : std_logic; signal merge_handler_reset : std_logic; - signal data_frame_f : std_logic_vector(43 downto 0); signal data_frame : std_logic_vector(43 downto 0); - signal data_frame_clk_f : std_logic; signal data_frame_clk : std_logic; signal merge_timeout_ctr : unsigned(3 downto 0); signal merge_timeout_error : std_logic; @@ -187,9 +185,13 @@ architecture Behavioral of nx_data_receiver is signal rate_timer_ctr : unsigned(27 downto 0); -- Error + signal adc_error_i : std_logic; + signal adc_error_undef_i : std_logic; signal error_o : std_logic; signal error_status_bits : std_logic_vector(15 downto 0); signal adc_notlock_counter : unsigned(27 downto 0); + signal adc_error_counter : unsigned(27 downto 0); + signal adc_error_undef_counter : unsigned(27 downto 0); -- Rate Errors signal nx_frame_rate_offline_last : std_logic; @@ -273,6 +275,8 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- signal nx_online_ii : std_logic; signal nx_online_i : std_logic; + signal adc_error : std_logic; + signal adc_error_undef : std_logic; signal startup_reset : std_logic; signal rs_wait_timer_start : std_logic; signal rs_wait_timer_done : std_logic; @@ -321,7 +325,7 @@ architecture Behavioral of nx_data_receiver is signal nx_clk_active : std_logic; -- Parity Error Counter Process - signal parity_error_b : std_logic; + signal parity_error : std_logic; signal parity_error_c100 : std_logic; signal parity_error_counter : unsigned(11 downto 0); @@ -336,9 +340,6 @@ architecture Behavioral of nx_data_receiver is -- Keep FlipFlops, do not change to shift registers ----------- attribute syn_keep : boolean; - - attribute syn_keep of data_frame_f : signal is true; - attribute syn_keep of data_frame_clk_f : signal is true; attribute syn_keep of reset_nx_timestamp_clk_in_ff : signal is true; attribute syn_keep of reset_nx_timestamp_clk_in_f : signal is true; @@ -367,10 +368,6 @@ architecture Behavioral of nx_data_receiver is --attribute syn_keep of nx_frame_word_delay_r : signal is true; attribute syn_preserve : boolean; - - attribute syn_preserve of data_frame_f : signal is true; - attribute syn_preserve of data_frame_clk_f : signal is true; - attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true; attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true; @@ -453,7 +450,7 @@ begin DEBUG_OUT(5) <= nx_frame_rate_offline; DEBUG_OUT(6) <= nx_frame_rate_error; DEBUG_OUT(7) <= pll_adc_not_lock; - DEBUG_OUT(8) <= '0'; + DEBUG_OUT(8) <= adc_error; DEBUG_OUT(9) <= adc_frame_rate_error; DEBUG_OUT(10) <= fifo_reset_handler; DEBUG_OUT(11) <= pll_adc_sampling_clk_reset; @@ -514,17 +511,6 @@ begin DEBUG_OUT(14) <= '0'; DEBUG_OUT(15) <= ADC_SAMPLE_CLK_OUT; - when "111" => - DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; - DEBUG_OUT(1) <= NX_DATA_CLK_IN; - DEBUG_OUT(2) <= data_frame_clk; - DEBUG_OUT(3) <= fifo_fw_reset_i; - DEBUG_OUT(4) <= fifo_fw_full; - DEBUG_OUT(5) <= fifo_fw_write_enable; - DEBUG_OUT(6) <= fifo_fw_empty; - DEBUG_OUT(7) <= fifo_fw_read_enable; - DEBUG_OUT(15 downto 8) <= nx_frame_word_f; - when others => -- Default DEBUG_OUT(0) <= CLK_IN; @@ -650,7 +636,7 @@ begin port map ( CLK_A_IN => NX_DATA_CLK_IN, RESET_A_IN => RESET_NX_DATA_CLK_IN, - PULSE_A_IN => parity_error_b, + PULSE_A_IN => parity_error, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, PULSE_B_OUT => parity_error_c100 @@ -786,9 +772,9 @@ begin Empty => fifo_fw_empty, Full => fifo_fw_full ); - fifo_fw_reset_i <= RESET_NX_DATA_CLK_IN; - fifo_fw_write_enable <= '1'; --not fifo_fw_full; - fifo_fw_read_enable <= '1'; --not fifo_fw_empty; + fifo_fw_reset_i <= '0'; --RESET_IN or RESET_NX_DATA_CLK_IN; + fifo_fw_write_enable <= not fifo_fw_full; + fifo_fw_read_enable <= not fifo_fw_empty; -- Third: delay NX_TIMESTAMP_IN relatively to ADC Clock dynamic_shift_register8x64_1: entity work.dynamic_shift_register8x64 @@ -925,7 +911,7 @@ begin begin if (rising_edge(NX_DATA_CLK_IN)) then if (RESET_NX_DATA_CLK_IN = '1') then - parity_error_b <= '0'; + parity_error <= '0'; else if (nx_frame_clk = '1') then -- Timestamp Bit #6 is excluded (funny nxyter-bug) @@ -937,12 +923,12 @@ begin parity := xor_all(parity_bits); if (parity /= nx_frame_word(0)) then - parity_error_b <= '1'; + parity_error <= '1'; else - parity_error_b <= '0'; + parity_error <= '0'; end if; else - parity_error_b <= '0'; + parity_error <= '0'; end if; end if; end if; @@ -1083,6 +1069,12 @@ begin ADC0_LOCKED_OUT => adc_locked, ADC1_LOCKED_OUT => open, + ERROR_ADC0_OUT => adc_error_i, + ERROR_ADC1_OUT => open, + + ERROR_UNDEF_ADC0_OUT => adc_error_undef_i, + ERROR_UNDEF_ADC1_OUT => open, + DEBUG_IN => adc_debug_type, DEBUG_OUT => ADC_DEBUG ); @@ -1158,26 +1150,22 @@ begin ----------------------------------------------------------------------------- -- Clock Domain Transfer Data Stream ----------------------------------------------------------------------------- - - -- Relax Timing by FF - data_frame_f <= data_frame when rising_edge(NX_DATA_CLK_IN); - data_frame_clk_f <= data_frame_clk when rising_edge(NX_DATA_CLK_IN); - + fifo_data_stream_44to44_dc_1: fifo_data_stream_44to44_dc port map ( - Data => data_frame_f, + Data => data_frame, WrClock => NX_DATA_CLK_IN, RdClock => CLK_IN, WrEn => fifo_write_enable, RdEn => fifo_read_enable, - Reset => RESET_NX_DATA_CLK_IN, --fifo_reset_i, + Reset => fifo_reset_i, RPReset => fifo_reset_i, Q => fifo_data, Empty => fifo_empty, Full => fifo_full ); fifo_reset_i <= RESET_IN or fifo_reset_handler; - fifo_write_enable <= not fifo_full and data_frame_clk_f; + fifo_write_enable <= not fifo_full and data_frame_clk; fifo_read_enable <= not fifo_empty; PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) @@ -1529,6 +1517,7 @@ begin (pll_adc_not_lock = '1' or adc_reset_sync = '1' or adc_frame_rate_error = '1' or + adc_error = '1' or pll_adc_not_lock = '1' or adc_dt_error = '1' or adc_sclk_ok_c100 = '0' or @@ -1541,7 +1530,7 @@ begin parity_rate_error = '1' or nx_frame_rate_error = '1' ) then - R_STATE <= R_IDLE; --R_RESET_TIMESTAMP; + R_STATE <= R_RESET_TIMESTAMP; else reset_timeout_flag <= '0'; rs_timeout_timer_reset <= '1'; @@ -1712,6 +1701,33 @@ begin PULSE_OUT => adc_notlocked_p ); + pulse_dtrans_ADC_ERROR: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => adc_error_i, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_error + ); + + pulse_dtrans_ADC_ERROR_UNDEF: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => adc_error_undef_i, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_error_undef + ); + + PROC_ERROR_STATUS: process(CLK_IN) variable error_mask : std_logic_vector(15 downto 0); begin @@ -1722,6 +1738,8 @@ begin error_status_bits <= (others => '0'); error_o <= '0'; adc_notlock_counter <= (others => '0'); + adc_error_counter <= (others => '0'); + adc_error_undef_counter <= (others => '0'); else adc_sclk_ok_c100 <= adc_sclk_ok_f; @@ -1731,7 +1749,7 @@ begin error_status_bits(3) <= adc_frame_rate_error; error_status_bits(4) <= parity_rate_error; error_status_bits(5) <= not nx_frame_synced_r; - error_status_bits(6) <= '0'; + error_status_bits(6) <= adc_error; error_status_bits(7) <= pll_adc_not_lock; error_status_bits(8) <= not adc_sclk_ok_c100; error_status_bits(9) <= not adc_locked_c100; @@ -1756,6 +1774,14 @@ begin adc_notlock_counter <= adc_notlock_counter + 1; end if; + if (adc_error = '1') then + adc_error_counter <= adc_error_counter + 1; + end if; + + if (adc_error_undef = '1') then + adc_error_undef_counter <= adc_error_undef_counter + 1; + end if; + end if; end if; end process PROC_ERROR_STATUS; @@ -1806,7 +1832,7 @@ begin new_timestamp_dt_error_ctr_r <= (others => '0'); adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); --- nx_frame_word_delay_r <= (others => '0'); + nx_frame_word_delay_r <= (others => '0'); else fifo_full_r <= fifo_full_rr; fifo_empty_r <= fifo_empty_rr; @@ -1991,6 +2017,18 @@ begin slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; + when x"0017" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(adc_error_counter); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0018" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(adc_error_undef_counter); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + when x"001e" => slv_data_out_o(2 downto 0) <= debug_mode; slv_data_out_o(31 downto 3) <= (others => '0'); diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 045d20b..68baed4 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -248,6 +248,10 @@ component adc_ad9228 ADC1_DATA_CLK_OUT : out std_logic; ADC0_LOCKED_OUT : out std_logic; ADC1_LOCKED_OUT : out std_logic; + ERROR_ADC0_OUT : out std_logic; + ERROR_ADC1_OUT : out std_logic; + ERROR_UNDEF_ADC0_OUT : out std_logic; + ERROR_UNDEF_ADC1_OUT : out std_logic; DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 601932b..151219a 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -87,9 +87,9 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_nx_timestamp_c MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/merge_handler_reset_i*" 30 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cnx_ff*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_reset_handler*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_rr*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; @@ -107,11 +107,8 @@ MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/parity_error_b*" 100ns; - MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_CLKDIV*" 30 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_ADC0_CLKD_F*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_frame_locked*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_locked_o*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; @@ -124,7 +121,6 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_of MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_event_buffer_*/fifo_almost_full_thr_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/debug_multiplexer_*/port_select_*" 100 ns; -MULTICYCLE TO CELL "*/NX1_DEBUG_LINE_*" 100 ns; #SPI Interface REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE; @@ -144,7 +140,7 @@ PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c"; PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c"; DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 1.0 ns HOLD 1.0 ns CLKPORT="NX1_DATA_CLK_IN"; +INPUT_SETUP GROUP "NX1_IN" 1.3 ns HOLD 1.3 ns CLKPORT="NX1_DATA_CLK_IN"; UGROUP NXYTER1 BBOX 100 70 BLKNAME nXyter_FEE_board_0; diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index 9f1cba2..660071e 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -2,7 +2,7 @@ -i 2 -l 5 -n 2 --t 10 +-t 5 -s 1 -c 1 -e 2