From: Adrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Date: Tue, 19 Jan 2021 15:21:05 +0000 (+0100)
Subject: exchange MBS logic to new DLm to CTS logic. No inbetween mbs communication is needed.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5e5094ec3a82ae5152e6e250d3c3deb79967bdb1;p=dirich.git

exchange MBS logic to new DLm to CTS logic. No inbetween mbs communication is needed.
---

diff --git a/combiner_cts/code_EBR/Cal_Limits_v2.vhd b/combiner_cts/code_EBR/Cal_Limits_v2.vhd
index 89f44d1..a3d3f0d 100644
--- a/combiner_cts/code_EBR/Cal_Limits_v2.vhd
+++ b/combiner_cts/code_EBR/Cal_Limits_v2.vhd
@@ -70,10 +70,11 @@ architecture Behavioral of Cal_Limits_v2 is
   signal cnt_i       : unsigned(19 downto 0):="00000000000000000000";
   signal cal_Limit   : unsigned(19 downto 0):="00011000011010100000";--"00011000011010100000";
 
-  type array2D is array (0 to 15, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
-  signal def_value   : array2D := (others => (others => "10000000000000010011"));
+  --type array2D is array (0 to 15, 0 to 64) of std_logic_vector(19 downto 0); --(FPGA)(channel)
+  --signal def_value   : array2D := (others => (others => "10000000000000010011")); --max: 512  ;  min: 19
+  signal def_value   : std_logic_vector(19 downto 0) := "10000000000000010011";   --max: 512  ;  min: 19
   
-  type bit_2D is array (16 downto 0, 63 downto 0) of std_logic; --(channel)
+  type bit_2D is array (15 downto 0, 63 downto 0) of std_logic; --(channel)
   signal dflt_i      : bit_2D := (others => (others => '1'));
  
   type tLocalBuffer is array ( (locBufDepth-1) downto 0) of std_logic_vector(31 downto 0); --(Flag [31])(reserved [30] )(FPGA [29:26])(channel [25:20])(Max [19:10])(Min [9:0])
@@ -265,12 +266,19 @@ begin
       --FLASH
         if Do_Cal_in_r = '1' then
           write_curr <= '1';
-          min_out    <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto  0);
-          max_out    <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10);
-          min_curr   <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto  0);
-          max_curr   <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10);
-          Delta_i    <= std_logic_vector(unsigned(def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(9 downto 0)));
-          EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto 0);
+--           min_out    <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto  0);
+--           max_out    <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10);
+--           min_curr   <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto  0);
+--           max_curr   <= def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10);
+--           Delta_i    <= std_logic_vector(unsigned(def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10)) - unsigned(def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(9 downto 0)));
+--           EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))(19 downto 10) & def_value(to_integer(unsigned(FPGA_r)),to_integer(unsigned(chnl_r)))( 9 downto 0);
+
+          min_out    <= def_value( 9 downto  0);
+          max_out    <= def_value(19 downto 10);
+          min_curr   <= def_value( 9 downto  0);
+          max_curr   <= def_value(19 downto 10);
+          Delta_i    <= std_logic_vector(unsigned(def_value(19 downto 10)) - unsigned(def_value(9 downto 0)));
+          EBRbufCurr(locBufDepth-1) <= "10" & FPGA_r & chnl_r(5 downto 0) & def_value(19 downto 10) & def_value( 9 downto 0);
         else
           write_curr <= '0';
           --min_out    <= b"0000000000";
@@ -401,4 +409,4 @@ begin
   chnl_out_write_cnt <= chnl_r;
   FPGA_out_write_cnt <= fpga_r;
   Delta              <= Delta_i;
-end Behavioral;
\ No newline at end of file
+end Behavioral;