From: hadaq Date: Wed, 27 Mar 2013 08:02:06 +0000 (+0000) Subject: reset signal is removed - cu X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5e7d2b363fb04bfd736d8873ca340ce43c3f715a;p=trb3.git reset signal is removed - cu --- diff --git a/tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd b/tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd index 497d384..14cf48d 100644 --- a/tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd +++ b/tdc_releases/tdc_v1.1.1/ShiftRegisterSISO.vhd @@ -5,7 +5,7 @@ -- File : Register.vhd -- Author : c.ugur@gsi.de -- Created : 2012-10-02 --- Last update: 2012-10-04 +-- Last update: 2013-03-27 ------------------------------------------------------------------------------- -- Description: Used to register signals n levels. ------------------------------------------------------------------------------- @@ -18,12 +18,11 @@ use ieee.numeric_std.all; entity ShiftRegisterSISO is generic ( - DEPTH : integer range 1 to 32 := 1; -- defines the number register level - WIDTH : integer range 1 to 32 := 1); -- defines the register size + DEPTH : integer range 1 to 32 := 1; -- defines the number register level + WIDTH : integer range 1 to 32 := 1); -- defines the register size port ( CLK : in std_logic; -- register clock - RESET : in std_logic; -- register reset D_IN : in std_logic_vector(WIDTH-1 downto 0); -- register input D_OUT : out std_logic_vector(WIDTH-1 downto 0)); -- register out @@ -42,14 +41,10 @@ begin -- RTL reg(0) <= D_IN; GEN_Registers : for i in 1 to DEPTH generate - Registers : process (CLK, RESET) + Registers : process (CLK) begin if rising_edge(CLK) then - if RESET = '1' then - reg(i) <= (others => '0'); - else - reg(i) <= reg(i-1); - end if; + reg(i) <= reg(i-1); end if; end process Registers; end generate GEN_Registers;