From: Tobias Weber <toweber86@gmail.com>
Date: Thu, 30 Aug 2018 07:40:52 +0000 (+0200)
Subject: change size of memory for circullar buffer.
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5ebfe933f3a2ebdcb840255462c50d39490d507a;p=trb3.git

change size of memory for circullar buffer.
---

diff --git a/mupix/Mupix8/sources/Datapath/CircularMemory.vhd b/mupix/Mupix8/sources/Datapath/CircularMemory.vhd
index ea0d02d..143b2c6 100644
--- a/mupix/Mupix8/sources/Datapath/CircularMemory.vhd
+++ b/mupix/Mupix8/sources/Datapath/CircularMemory.vhd
@@ -37,7 +37,7 @@ end entity CircularMemory;
 
 architecture RTL of CircularMemory is
 
-  component RAM_DP_4096_32 is
+  component RAM_DP_8192_32 is
     port (
       WrAddress : in  std_logic_vector(11 downto 0);
       RdAddress : in  std_logic_vector(11 downto 0);
@@ -49,7 +49,7 @@ architecture RTL of CircularMemory is
       WrClock   : in  std_logic;
       WrClockEn : in  std_logic;
       Q         : out std_logic_vector(31 downto 0));
-  end component RAM_DP_4096_32;
+  end component RAM_DP_8192_32;
 
   --counters for write/read frequency
   signal ticks_counter                   : unsigned(f_log2(g_clockspeed) - 1 downto 0) := (others => '0');
@@ -78,7 +78,7 @@ architecture RTL of CircularMemory is
 
 begin
 
-  RAM_DP_4096_32_1: entity work.RAM_DP_4096_32
+  RAM_DP_4096_32_1: entity work.RAM_DP_8192_32
     port map (
       WrAddress => WrAddr_mem,
       RdAddress => ReAddr_mem,
diff --git a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
index d0bf9be..79940c6 100644
--- a/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
+++ b/mupix/Mupix8/sources/Datapath/MupixTRBReadout.vhd
@@ -138,6 +138,8 @@ architecture rtl of MupixTRBReadout is
       data_out          : out std_logic_vector(g_datawidth - 1 downto 0)
       );
   end component ReadoutController;
+  
+  signal reset_reg : std_logic := '0';
 
   signal readout_mode_i          : std_logic_vector(1 downto 0)                           := "00";
   signal readout_writes_aft_trig : std_logic_vector(g_cyc_mem_address_width - 1 downto 0) := (others => '0');
@@ -187,6 +189,13 @@ architecture rtl of MupixTRBReadout is
 
 begin
 
+  reset_proc : process(clk)
+  begin
+    if rising_edge(clk) then
+        reset_reg <= rst;
+    end if;
+  end process reset_proc;
+
   start_readout <= start_readout_slow_to_buffer or trb_trigger;
 
   FiFoDataMux_1 : entity work.FiFoDataMux
@@ -196,7 +205,7 @@ begin
       g_clockspeed => 1e8)
     port map (
       clk         => clk,
-      rst         => rst,
+      rst         => reset_reg,
       fifo_empty  => fifo_empty,
       fifo_full   => fifo_full,
       fifo_datain => fifo_datain,
@@ -213,7 +222,7 @@ begin
       Clock => clk,
       WrEn  => fifo_data_width_wr_i,
       RdEn  => fifo_data_width_rd_i,
-      Reset => rst,
+      Reset => reset_reg,
       WCNT  => fifo_data_width_cnt_i,
       Q     => fifo_data_width_dataout_i,
       Empty => fifo_data_width_empty_i,
@@ -225,7 +234,7 @@ begin
       g_datawidthtrb  => g_datawidthtrb)
     port map (
       clk         => clk,
-      reset       => rst,
+      reset       => reset_reg,
       fifo_empty  => fifo_data_width_empty_i,
       fifo_wrcnt  => fifo_data_width_cnt_i,
       fifo_datain => fifo_data_width_dataout_i,
@@ -242,7 +251,7 @@ begin
       )
     port map(
       clk          => clk,
-      rst          => rst,
+      rst          => reset_reg,
       wr_en        => fifo_mux_wren,
       data_in      => fifo_mux_data_out,
       rd_en        => readout_controller_rd_en,
@@ -265,7 +274,7 @@ begin
       )
     port map(
       clk               => clk,
-      rst               => rst,
+      rst               => reset_reg,
       start             => start_readout,
       mode              => readout_mode_i,
       writes_after_trig => readout_writes_aft_trig,
@@ -284,7 +293,7 @@ begin
   data_read_slow : process (clk) is
   begin
     if rising_edge(clk) then
-      if rst = '1' then
+      if reset_reg = '1' then
         slow_readout_fsm             <= idle;
         slow_read_done               <= '0';
         slow_read_busy               <= '0';
@@ -334,7 +343,7 @@ begin
   slv_bus_handler : process(clk) is
   begin
     if rising_edge(clk) then
-      if rst = '1' then
+      if reset_reg = '1' then
         SLV_DATA_OUT         <= (others => '0');
         SLV_ACK_OUT          <= '0';
         SLV_NO_MORE_DATA_OUT <= '0';
diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd
index f2fbe5a..2234a22 100644
--- a/mupix/Mupix8/sources/MupixBoard.vhd
+++ b/mupix/Mupix8/sources/MupixBoard.vhd
@@ -538,7 +538,7 @@ begin  -- Behavioral
   mupixreadout1 : entity work.MupixTRBReadout
     generic map(
       g_mupix_links           => c_links,
-      g_cyc_mem_address_width => 12,
+      g_cyc_mem_address_width => 13,
       g_datawidthfifo         => c_mupixhitsize,
       g_datawidthtrb          => 32
       )