From: hadeshyp <hadeshyp>
Date: Mon, 14 Jan 2008 17:14:25 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~643
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5f220a0b628e934ae3e2e8bc33b36a1aee13bd53;p=trbnet.git

*** empty log message ***
---

diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd
index 5577789..8d89593 100644
--- a/testbench/trb_net16_dummy_apl.vhd
+++ b/testbench/trb_net16_dummy_apl.vhd
@@ -62,9 +62,12 @@ architecture trb_net16_dummy_apl_arch of trb_net16_dummy_apl is
   signal address, reghigh, reglow : std_logic_vector(15 downto 0);
 begin
 
-  address <= x"0008";
-  reghigh <= x"DEAD";
-  reglow  <= x"AFFE";
+--   address <= x"0008";
+--   reghigh <= x"DEAD";
+--   reglow  <= x"AFFE";
+  address <= x"0003";
+  reghigh <= x"000B";
+  reglow  <= x"000D";
 
 
 
@@ -97,9 +100,10 @@ begin
 -- IDLE
 -------------------------------------------------------------------------
       if current_state = IDLE then
-        if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then
-          next_state <=  RUNNING;
-          next_APL_SEND_OUT <= '0';
+        if reg_counter = TRANSFER_LENGTH then
+          next_state <= WAITING;
+        elsif APL_FIFO_FULL_IN = '1' then
+          next_state <=  IDLE;
         else
           next_APL_SEND_OUT <= buf_APL_SEND_OUT;
           next_state <=  WRITING;
@@ -142,6 +146,7 @@ begin
 -- WAITING
 -----------------------------------------------------------------------
       elsif current_state = WAITING then
+        next_APL_SEND_OUT <= '0';
         if APL_RUN_IN = '1' or buf_APL_SEND_OUT = '1' then
           next_state <=  WAITING;
         else
diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd
index 7ff21c6..a138165 100644
--- a/trb_net16_med_tlk.vhd
+++ b/trb_net16_med_tlk.vhd
@@ -88,6 +88,8 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is
   signal reg_TXD   : std_logic_vector(15 downto 0);
   signal reg_TX_EN : std_logic;
 
+  signal TLK_CLK_neg : std_logic;
+signal CLK_Out, CLK_FB_Out, FB_CLK : std_logic;
 begin
 
 --   STAT(3 downto 0)   <= fifo_status_a;
@@ -143,6 +145,8 @@ begin
   STAT(5) <= fifo_empty_a;
   STAT(6) <= fifo_rd_en_m;
   STAT(7) <= fifo_empty_m;
+  STAT(8) <= fifo_full_a;
+  STAT(31 downto 16) <= reg_RXD;
   
   process(TLK_RX_CLK)
     begin
@@ -186,9 +190,34 @@ begin
 --Sender
 -------------
 
+U_DCM_Transmitter: DCM
+  generic map( 
+      CLKIN_PERIOD => 10.00, -- 30.30ns
+      STARTUP_WAIT => FALSE,
+      PHASE_SHIFT => 0,
+      DESKEW_ADJUST => "SOURCE_SYNCHRONOUS",
+      CLKOUT_PHASE_SHIFT => "FIXED"
+      )  
+  port map (
+      CLKIN =>    TLK_CLK,
+      CLKFB =>    FB_CLK,
+      DSSEN =>    '0',
+      PSINCDEC => '0',
+      PSEN =>     '0',
+      PSCLK =>    '0',
+      RST =>      RESET,
+      CLK0 =>     CLK_FB_Out, -- for feedback
+      CLK90=>    CLK_Out,
+      LOCKED =>   open
+     ); 
+--      
+U0_BUFG: BUFG  port map (I => CLK_FB_Out,    O => TLK_CLK_neg);
+U1_BUFG: BUFG  port map (I => CLK_FB_Out, O => FB_CLK);
+
+
   FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport
     port map(
-      read_clock_in   => TLK_CLK,
+      read_clock_in   => TLK_CLK_neg,
       write_clock_in  => CLK,
       read_enable_in  => fifo_rd_en_m,
       write_enable_in => fifo_wr_en_m,
@@ -206,9 +235,9 @@ begin
   TLK_TXD <= reg_TXD;
   TLK_TX_EN <= reg_TX_EN;
 
-  process(TLK_CLK)
+  process(TLK_CLK_neg)
     begin
-      if rising_edge(TLK_CLK) then
+      if rising_edge(TLK_CLK_neg) then
         if internal_reset = '1' then
           reg_TXD   <= (others => '0');
           reg_TX_EN <= '0';
@@ -219,9 +248,9 @@ begin
       end if;
     end process;
 
-  process(TLK_CLK)
+  process(TLK_CLK_neg)
     begin
-      if rising_edge(TLK_CLK) then
+      if rising_edge(TLK_CLK_neg) then
         if internal_reset = '1' then
           last_fifo_rd_en_m <= '0';
         else