From: Jan Michel Date: Fri, 5 Jun 2015 14:58:03 +0000 (+0200) Subject: update with nice wrapper for all basic tools such as uart, spi, flash, adc... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5f35de2a1062b487d8bf956583a0ff15be988114;p=trb3sc.git update with nice wrapper for all basic tools such as uart, spi, flash, adc... --- diff --git a/README.txt b/README.txt new file mode 100644 index 0000000..e788f5c --- /dev/null +++ b/README.txt @@ -0,0 +1,25 @@ + +## Directories ## + + +code + VHDL sources specific for TRB3sc + +cores + Ipexpress cores specific to TRB3sc + +pinout + Pinout for all design as well as basic constraints present in all designs + +scripts + E.g. the compile script to be used for all TRB3sc projects and configuratioon files for these scripts + +template + A basic design with all global features, should be used as template for own designs, but can be used as-is for tests + + + +## Preparation ## + - a config_compile_NAME.pl file is needed for each project and environment in the project directory + - for multipar, add a nodelist to the scripts directory + - link both the nodelist and the compile script to your project directory \ No newline at end of file diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd new file mode 100644 index 0000000..67dd1af --- /dev/null +++ b/code/trb3sc_tools.vhd @@ -0,0 +1,183 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_components.all; + use work.trb_net_std.all; + use work.trb3_components.all; + use work.config.all; + +entity trb3sc_tools is + port( + CLK : in std_logic; + RESET : in std_logic; + + --Flash & Reload + FLASH_CS : out std_logic; + FLASH_CLK : out std_logic; + FLASH_IN : in std_logic; + FLASH_OUT : out std_logic; + PROGRAMN : out std_logic; + REBOOT_IN : in std_logic; + + --SPI + SPI_CS_OUT : out std_logic_vector(15 downto 0); + SPI_MOSI_OUT: out std_logic_vector(15 downto 0); + SPI_MISO_IN : in std_logic_vector(15 downto 0) := (others => '0'); + SPI_CLK_OUT : out std_logic_vector(15 downto 0); + + --UART + UART_TX : out std_logic; + UART_RX : in std_logic := '0'; + + --ADC + ADC_CS : out std_logic := '0'; + ADC_MOSI : out std_logic := '0'; + ADC_MISO : in std_logic := '0'; + ADC_CLK : out std_logic := '0'; + + --SED + SED_ERROR_OUT : out std_logic; + + --Slowcontrol + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + + DEBUG_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture trb3sc_tools_arch of trb3sc_tools is + +signal busflash_rx, busspi_rx, busadc_rx, bussed_rx, busuart_rx : CTRLBUS_RX; +signal busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx : CTRLBUS_TX; + +signal spi_sdi, spi_sdo, spi_sck : std_logic; +signal spi_cs : std_logic_vector(15 downto 0); + +begin + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => CLK, + RESET => RESET, + + REGIO_RX => BUS_RX, + REGIO_TX => BUS_TX, + + BUS_RX(0) => busflash_rx, + BUS_RX(1) => busspi_rx, + BUS_RX(2) => busadc_rx, + BUS_RX(3) => bussed_rx, + BUS_RX(4) => busuart_rx, + BUS_TX(0) => busflash_tx, + BUS_TX(1) => busspi_tx, + BUS_TX(2) => busadc_tx, + BUS_TX(3) => bussed_tx, + BUS_TX(4) => busuart_tx, + + STAT_DEBUG => open + ); + + + +--------------------------------------------------------------------------- +-- Flash & Reboot +--------------------------------------------------------------------------- + THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload_record + port map( + CLK_IN => CLK, + RESET_IN => RESET, + + BUS_RX => busflash_rx, + BUS_TX => busflash_tx, + + DO_REBOOT_IN => REBOOT_IN, + PROGRAMN => PROGRAMN, + + SPI_CS_OUT => FLASH_CS, + SPI_SCK_OUT => FLASH_CLK, + SPI_SDO_OUT => FLASH_OUT, + SPI_SDI_IN => FLASH_IN + ); + +--------------------------------------------------------------------------- +-- SED Detection +--------------------------------------------------------------------------- + THE_SED : entity work.sedcheck + port map( + CLK => CLK, + ERROR_OUT => SED_ERROR_OUT, + BUS_RX => bussed_rx, + BUS_TX => bussed_tx, + DEBUG => open + ); + + +--------------------------------------------------------------------------- +-- ADC +--------------------------------------------------------------------------- + + +--------------------------------------------------------------------------- +-- SPI +--------------------------------------------------------------------------- + gen_SPI : if INCLUDE_SPI = 1 generate + THE_SPI : spi_ltc2600 + port map( + CLK_IN => CLK, + RESET_IN => RESET, + -- Slave bus + BUS_ADDR_IN => busspi_rx.addr(4 downto 0), + BUS_READ_IN => busspi_rx.read, + BUS_WRITE_IN => busspi_rx.write, + BUS_ACK_OUT => busspi_tx.ack, + BUS_BUSY_OUT => busspi_tx.nack, + BUS_DATA_IN => busspi_rx.data, + BUS_DATA_OUT => busspi_tx.data, + -- SPI connections + SPI_CS_OUT(15 downto 0) => spi_cs, + SPI_SDI_IN => spi_sdi, + SPI_SDO_OUT => spi_sdo, + SPI_SCK_OUT => spi_sck + ); + SPI_CS_OUT <= spi_cs; + SPI_CLK_OUT <= (others => spi_sck); + SPI_MOSI_OUT <= (others => spi_sdo); + spi_sdi <= or_all(SPI_MISO_IN and not spi_cs); + end generate; + +--------------------------------------------------------------------------- +-- UART +--------------------------------------------------------------------------- + gen_uart : if INCLUDE_UART = 1 generate + THE_UART : entity work.uart + generic map( + OUTPUTS => 1 + ) + port map( + CLK => CLK, + RESET => RESET, + UART_RX(0) => UART_RX, + UART_TX(0) => UART_TX, + BUS_RX => busuart_rx, + BUS_TX => busuart_tx + ); + end generate; + + + + +end architecture; \ No newline at end of file diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf new file mode 100644 index 0000000..671f71a --- /dev/null +++ b/pinout/basic_constraints.lpf @@ -0,0 +1,44 @@ +COMMERCIAL ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + +SYSCONFIG MCCLK_FREQ = 20; + +FREQUENCY PORT CLK_CORE_PCLK 240 MHz; +FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz; +FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz; + +FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz; +FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz; +FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125 MHz; + +FREQUENCY PORT CLK_EXT_PCLK 200 MHz; +FREQUENCY PORT CLK_EXT_PLL_LEFT 200 MHz; +FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz; + + +#If these signals do not exist, somebody messed around with the design... +MULTICYCLE TO CELL "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns; +MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; +MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; +GSR_NET NET "GSR_N"; + + +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; +MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/SCI_DATA_OUT*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i"; + +LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ; +REGION "MEDIA_UPLINK" "R102C95D" 13 25; +LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ; + diff --git a/pinout/trb3sc_basic.lpf b/pinout/trb3sc_basic.lpf index a077403..970f47f 100644 --- a/pinout/trb3sc_basic.lpf +++ b/pinout/trb3sc_basic.lpf @@ -1,49 +1,3 @@ -COMMERCIAL ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; - -################################################################# -# Basic Settings -################################################################# - -SYSCONFIG MCCLK_FREQ = 20; - -FREQUENCY PORT CLK_CORE_PCLK 240 MHz; -FREQUENCY PORT CLK_CORE_PLL_LEFT 240 MHz; -FREQUENCY PORT CLK_CORE_PLL_RIGHT 240 MHz; - -FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz; -FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz; -FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125 MHz; - -FREQUENCY PORT CLK_EXT_PCLK 200 MHz; -FREQUENCY PORT CLK_EXT_PLL_LEFT 200 MHz; -FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz; - - -#If these signals do not exist, somebody messed around with the design... -MULTICYCLE TO CELL "THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio*" 20 ns; -MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 20 ns; -MULTICYCLE FROM CELL "THE_CLOCK_RESET/gen_norecov_clock.clear_n_i" 20 ns; -MULTICYCLE TO CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/trb_reset_pulse*" 20 ns; -MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; -GSR_NET NET "GSR_N"; - - -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; -MULTICYCLE FROM CELL "THE_MEDIA_INTERFACE/sci*" 20 ns; -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/SCI_DATA_OUT*" 20 ns; -MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.wa*" 20 ns; -BLOCK PATH TO CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i"; -BLOCK PATH FROM CLKNET "THE_MEDIA_INTERFACE/PROC_SCI_CTRL.sci_write_i"; - -LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ; -REGION "MEDIA_UPLINK" "R102C95D" 13 25; -LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ; - - - ################################################################# # Clock I/O ################################################################# diff --git a/scripts/compile.pl b/scripts/compile.pl index afed5ed..8f74a9f 100755 --- a/scripts/compile.pl +++ b/scripts/compile.pl @@ -19,7 +19,8 @@ my $synplify_command = $config{synplify_command}; my $synplify_locale_workaround = "en_US\@UTF-8"; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed - +my $include_TDC = $config{include_TDC} || 0; +my $include_GBE = $config{include_GBE} || 0; my $twr_number_of_errors = $config{twr_number_of_errors} || 10; @@ -111,12 +112,21 @@ system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); #create full lpf file print GREEN, "Generating constraints file...\n\n", RESET; system("cp ../pinout/$TOPNAME.lpf $WORKDIR/$TOPNAME.lpf"); -system("cat ../tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); -system("cat ../tdc_release/tdc_constraints_script.lpf >> $WORKDIR/$TOPNAME.lpf"); -system("cat ../tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); +system("cat ../pinout/basic_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + +if($include_TDC) { + system("cat ../tdc_release/trbnet_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat ../tdc_release/tdc_constraints_script.lpf >> $WORKDIR/$TOPNAME.lpf"); + system("cat ../tdc_release/unimportant_lines_constraints.lpf >> $WORKDIR/$TOPNAME.lpf"); + } +if($include_GBE) { + + } #copy delay line to project folder -system("ln -s ../tdc_release/Adder_304.ngo $WORKDIR/"); +if($include_TDC) { + system("ln -fs ../tdc_release/Adder_304.ngo $WORKDIR/"); + } #generate timestamp my $t=time; diff --git a/template/config_compile_frankfurt.pl b/template/config_compile_frankfurt.pl index 2306fd6..28137a7 100644 --- a/template/config_compile_frankfurt.pl +++ b/template/config_compile_frankfurt.pl @@ -7,6 +7,12 @@ synplify_command => "/d/jspc29/lattice/diamond/3.4_x64/bin/lin64/syn #synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +#Include only necessary lpf files +include_TDC => 0, +include_GBE => 0, + +#Report settings firefox_open => 0, twr_number_of_errors => 20, + diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index 9d84d59..a868bfc 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -91,6 +91,7 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" @@ -98,12 +99,17 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dual add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" -#Flash & Reload +#Flash & Reload, Tools add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" @@ -122,7 +128,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.v add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" - +#TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index f41ac6b..34952ae 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -165,8 +165,8 @@ architecture trb3sc_arch of trb3sc_basic is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_rx, bussci_rx, busflash_rx, bussed_rx, bustc_rx : CTRLBUS_RX; - signal ctrlbus_tx, bussci_tx, busflash_tx, bussed_tx, bustc_tx : CTRLBUS_TX; + signal ctrlbus_rx, bussci_rx, bustools_rx, bustc_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci_tx, bustools_tx, bustc_tx : CTRLBUS_TX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -181,10 +181,8 @@ architecture trb3sc_arch of trb3sc_basic is attribute syn_preserve of GSR_N : signal is true; attribute syn_keep of bussci_rx : signal is true; attribute syn_preserve of bussci_rx : signal is true; - attribute syn_keep of busflash_rx : signal is true; - attribute syn_preserve of busflash_rx : signal is true; - attribute syn_keep of bussed_rx : signal is true; - attribute syn_preserve of bussed_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; attribute syn_keep of bustc_rx : signal is true; attribute syn_preserve of bustc_rx : signal is true; @@ -340,9 +338,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d500", 2 => x"b000", 3 => x"d300", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 2, 2 => 9, 3 => 1, others => 0), + PORT_NUMBER => 3, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -352,53 +350,53 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record REGIO_RX => ctrlbus_rx, REGIO_TX => ctrlbus_tx, - BUS_RX(0) => busflash_rx, --Flash - BUS_RX(1) => bussed_rx, --SED - BUS_RX(2) => bussci_rx, --SCI Serdes - BUS_RX(3) => bustc_rx, --Clock switch - BUS_TX(0) => busflash_tx, - BUS_TX(1) => bussed_tx, - BUS_TX(2) => bussci_tx, - BUS_TX(3) => bustc_tx, + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bussci_rx, --SCI Serdes + BUS_RX(2) => bustc_rx, --Clock switch + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bussci_tx, + BUS_TX(2) => bustc_tx, STAT_DEBUG => open ); - --------------------------------------------------------------------------- --- Flash & Reboot +-- Control Tools --------------------------------------------------------------------------- - - THE_SPI_RELOAD : entity work.spi_flash_and_fpga_reload_record + THE_TOOLS: entity work.trb3sc_tools port map( - CLK_IN => clk_sys, - RESET_IN => reset_i, + CLK => clk_sys, + RESET => reset_i, - BUS_RX => busflash_rx, - BUS_TX => busflash_tx, + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => common_ctrl_reg(15), + --SPI + SPI_CS_OUT => open, + SPI_MOSI_OUT=> open, + SPI_MISO_IN => open, + SPI_CLK_OUT => open, + --UART + UART_TX => open, + UART_RX => open, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, - DO_REBOOT_IN => common_ctrl_reg(15), - PROGRAMN => PROGRAMN, - - SPI_CS_OUT => FLASH_CS, - SPI_SCK_OUT => FLASH_CLK, - SPI_SDO_OUT => FLASH_IN, - SPI_SDI_IN => FLASH_OUT + DEBUG_OUT => open ); ---------------------------------------------------------------------------- --- SED Detection ---------------------------------------------------------------------------- - THE_SED : entity work.sedcheck - port map( - CLK => clk_sys, - ERROR_OUT => sed_error_i, - BUS_RX => bussed_rx, - BUS_TX => bussed_tx, - DEBUG => open - ); - - --------------------------------------------------------------------------- -- Switches ---------------------------------------------------------------------------