From: Jan Michel <j.michel@gsi.de>
Date: Thu, 14 Jun 2018 14:53:08 +0000 (+0200)
Subject: fix reaction to timeout of reference time, remove parallel checks on reference time
X-Git-Tag: v2.3~13
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=5fa5e0c01680913eee5d3217e828726e785b71f2;p=tdc.git

fix reaction to timeout of reference time, remove parallel checks on reference time
---

diff --git a/releases/tdc_v2.3/Readout_record.vhd b/releases/tdc_v2.3/Readout_record.vhd
index a82f1ab..58d3e77 100644
--- a/releases/tdc_v2.3/Readout_record.vhd
+++ b/releases/tdc_v2.3/Readout_record.vhd
@@ -414,7 +414,7 @@ begin  -- behavioral
         rd_fsm_debug_fsm <= x"4";
 
       when WAIT_FOR_LVL1_TRG_A =>       -- wait for trigger data valid
-        if READOUT_RX.data_valid = '1' or READOUT_RX.trg_timeout = '1' then
+        if READOUT_RX.data_valid = '1' then -- or READOUT_RX.trg_timeout = '1'
           if READOUT_RX.trg_type /= x"1" and READOUT_RX.trg_type /= x"D" then
             unknown_trg_fsm <= '1';
           end if;
diff --git a/releases/tdc_v2.3/TDC_record.vhd b/releases/tdc_v2.3/TDC_record.vhd
index 1facb71..f9c9828 100644
--- a/releases/tdc_v2.3/TDC_record.vhd
+++ b/releases/tdc_v2.3/TDC_record.vhd
@@ -150,7 +150,7 @@ architecture TDC_record of TDC_record is
   
   signal hit_in_reg                   : std_logic_vector(CHANNEL_NUMBER-1 downto 1);
   signal ref_in_reg                   : std_logic;
-
+  signal trg_handler_trg_valid        : std_logic;
 
   attribute syn_keep                    : boolean;
   attribute syn_keep of reset_tdc       : signal is true;
@@ -246,7 +246,7 @@ begin
         if FPGA_TYPE = 3 then
           cal_cntr <= "11100";
         elsif FPGA_TYPE = 5 then
-          cal_cntr <= "01000";
+          cal_cntr <= "11000";
         end if;  
       else
         cal_cntr <= std_logic_vector(unsigned(cal_cntr) + to_unsigned(1, 5));
@@ -486,7 +486,7 @@ begin
       RESET_TRG             => reset_rdo,
       RESET_RDO             => reset_rdo,
       RESET_TDC             => reset_tdc,
-      VALID_TIMING_TRG_IN   => busreadout_rx.valid_timing_trg,
+      VALID_TIMING_TRG_IN   => trg_handler_trg_valid,
       VALID_NOTIMING_TRG_IN => busreadout_rx.valid_notiming_trg,
       TRG_TYPE_IN           => busreadout_rx.trg_type,
       TRG_RELEASE_IN        => busreadout_tx.busy_release,
@@ -504,7 +504,8 @@ begin
       DEBUG_OUT             => trg_handler_status_registers
       );
   trg_in <= REFERENCE_TIME;
-
+  trg_handler_trg_valid <= busreadout_rx.valid_timing_trg or busreadout_rx.invalid_trg;
+  
 -------------------------------------------------------------------------------
 -- Readout
 -------------------------------------------------------------------------------
diff --git a/releases/tdc_v2.3/TriggerHandler.vhd b/releases/tdc_v2.3/TriggerHandler.vhd
index f0271f5..4310b36 100644
--- a/releases/tdc_v2.3/TriggerHandler.vhd
+++ b/releases/tdc_v2.3/TriggerHandler.vhd
@@ -91,30 +91,32 @@ begin  -- architecture behavioral
   trg_in_2r <= trg_in_r  when rising_edge(CLK_TDC);
   trg_in_3r <= trg_in_2r when rising_edge(CLK_TDC);
 
-  GEN_TRIGGER : for i in 0 to TRIGGER_NUM-1 generate
-    Validation : process (CLK_TDC)
-    begin
-      if rising_edge(CLK_TDC) then
-
-        -- calculate trigger length
-        if trg_in_3r(i) = '0' then
-          trg_length(i) <= (others => '0');
-        else
-          trg_length(i) <= trg_length(i) + to_unsigned(1, 5);
-        end if;
-
-        -- accept trigger if it is longer than 100 ns
-        if RESET_TDC = '1' then
-          trg_pulse_tdc(i) <= '0';
-        elsif trg_length(i) = to_unsigned(15, 5) then
-          trg_pulse_tdc(i) <= '1';
-        else
-          trg_pulse_tdc(i) <= '0';
-        end if;
+--   GEN_TRIGGER : for i in 0 to TRIGGER_NUM-1 generate
+--     Validation : process (CLK_TDC)
+--     begin
+--       if rising_edge(CLK_TDC) then
+-- 
+--         -- calculate trigger length
+--         if trg_in_3r(i) = '0' then
+--           trg_length(i) <= (others => '0');
+--         else
+--           trg_length(i) <= trg_length(i) + to_unsigned(1, 5);
+--         end if;
+-- 
+--         -- accept trigger if it is longer than 100 ns
+--         if RESET_TDC = '1' then
+--           trg_pulse_tdc(i) <= '0';
+--         elsif trg_length(i) = to_unsigned(15, 5) then
+--           trg_pulse_tdc(i) <= '1';
+--         else
+--           trg_pulse_tdc(i) <= '0';
+--         end if;
+-- 
+--       end if;
+--     end process Validation;
+--   end generate GEN_TRIGGER;
+trg_pulse_tdc(0) <= valid_timing_200;
 
-      end if;
-    end process Validation;
-  end generate GEN_TRIGGER;
 
   -- sync the strobes to the readout clock domain
   GEN_TDC : for i in 0 to TRIGGER_NUM-1 generate
@@ -206,7 +208,7 @@ begin  -- architecture behavioral
 
     case STATE_TW_CURRENT is
       when IDLE =>
-        if trg_in_3r(0) = '1' then
+        if valid_timing_200 = '1' and trg_in_3r(0) = '1' then
           if TRG_WIN_EN_IN = '1' then
             STATE_TW_NEXT <= COUNT;
           else