From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Tue, 10 Feb 2015 09:13:26 +0000 (+0100)
Subject: ADC: Use 65MHz sampling rate
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=601070c4f0e482795f985f0f2e9562e33ba3c7b5;p=trb3.git

ADC: Use 65MHz sampling rate
---

diff --git a/ADC/config.vhd b/ADC/config.vhd
index 1108620..abb7dea 100644
--- a/ADC/config.vhd
+++ b/ADC/config.vhd
@@ -24,8 +24,8 @@ package config is
     constant INIT_ADDRESS           : std_logic_vector := x"F30a";
     constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b";
    
---ADC sampling frequency (only 40 MHz supported a.t.m.)
-    constant ADC_SAMPLING_RATE      : integer := 40;
+--ADC sampling frequency: 40 or 65 MHz supported
+    constant ADC_SAMPLING_RATE      : integer := 65;
     
 --These are currently used for the included features table only
     constant ADC_PROCESSING_TYPE    : integer := 0;
diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 3a1d16b..54d52e6 100644
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -6,6 +6,7 @@ library work;
 use work.trb_net_std.all;
 use work.trb3_components.all;
 use work.adc_package.all;
+use work.config.all;
 
 entity adc_ad9219 is
   generic(
@@ -63,12 +64,24 @@ signal lock            : std_logic_vector(1 downto 0);
 
 begin
 
+gen_40MHz : if ADC_SAMPLING_RATE = 40 generate
   THE_ADC_REF : entity work.pll_in200_out40
     port map(
       CLK   => CLK_ADCRAW,
       CLKOP => ADCCLK_OUT,
       LOCK  => lock(0)
       );
+end generate;
+
+gen_65MHz : if ADC_SAMPLING_RATE = 65 generate
+  THE_ADC_REF : entity work.pll_in200_out65
+    port map(
+      CLK   => CLK_ADCRAW,
+      CLKOP => ADCCLK_OUT,
+      LOCK  => lock(0)
+      );
+end generate;
+
 
   THE_ADC_PLL_0 : entity work.pll_adc10bit
     port map(