From: Ludwig Maier Date: Sat, 23 Aug 2014 15:22:01 +0000 (+0200) Subject: try modified nx_data_receiver merge handler, nx clock gets priority X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=60736c9cb0741140c6088a9d03aa2c81ea54d145;p=trb3.git try modified nx_data_receiver merge handler, nx clock gets priority --- diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index fa2638b..2d95b39 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -11,48 +11,51 @@ entity adc_ad9228 is DEBUG_ENABLE : boolean := false ); port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLK_ADCDAT_IN : in std_logic; + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_ADCDAT_IN : in std_logic; + RESET_ADCS : in std_logic; + ADC0_SCLK_IN : in std_logic; -- Sampling Clock ADC0 + ADC0_SCLK_OUT : out std_logic; + ADC0_DATA_A_IN : in std_logic; + ADC0_DATA_B_IN : in std_logic; + ADC0_DATA_C_IN : in std_logic; + ADC0_DATA_D_IN : in std_logic; + ADC0_DCLK_IN : in std_logic; -- Data Clock from ADC0 + ADC0_FCLK_IN : in std_logic; -- Frame Clock from ADC0 + + ADC1_SCLK_IN : in std_logic; -- Sampling Clock ADC1 + ADC1_SCLK_OUT : out std_logic; + ADC1_DATA_A_IN : in std_logic; + ADC1_DATA_B_IN : in std_logic; + ADC1_DATA_C_IN : in std_logic; + ADC1_DATA_D_IN : in std_logic; + ADC1_DCLK_IN : in std_logic; -- Data Clock from ADC1 + ADC1_FCLK_IN : in std_logic; -- Frame Clock from ADC1 + + ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_CLK_OUT : out std_logic; + + ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_CLK_OUT : out std_logic; + + ADC0_LOCKED_OUT : out std_logic; + ADC1_LOCKED_OUT : out std_logic; + + ADC0_SLOPPY_FRAME_IN : in std_logic; + ADC1_SLOPPY_FRAME_IN : in std_logic; + + ADC0_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC1_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); - ADC0_SCLK_IN : in std_logic; -- Sampling Clock ADC0 - ADC0_SCLK_OUT : out std_logic; - ADC0_DATA_A_IN : in std_logic; - ADC0_DATA_B_IN : in std_logic; - ADC0_DATA_C_IN : in std_logic; - ADC0_DATA_D_IN : in std_logic; - ADC0_DCLK_IN : in std_logic; -- Data Clock from ADC0 - ADC0_FCLK_IN : in std_logic; -- Frame Clock from ADC0 - - ADC1_SCLK_IN : in std_logic; -- Sampling Clock ADC1 - ADC1_SCLK_OUT : out std_logic; - ADC1_DATA_A_IN : in std_logic; - ADC1_DATA_B_IN : in std_logic; - ADC1_DATA_C_IN : in std_logic; - ADC1_DATA_D_IN : in std_logic; - ADC1_DCLK_IN : in std_logic; -- Data Clock from ADC1 - ADC1_FCLK_IN : in std_logic; -- Frame Clock from ADC1 - - ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_CLK_OUT : out std_logic; - - ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_CLK_OUT : out std_logic; - ADC0_LOCKED_OUT : out std_logic; - ADC1_LOCKED_OUT : out std_logic; - - ERROR_ADC0_OUT : out std_logic; - ERROR_ADC1_OUT : out std_logic; - ERROR_UNDEF_ADC0_OUT : out std_logic; - ERROR_UNDEF_ADC1_OUT : out std_logic; - DEBUG_IN : in std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) + DEBUG_IN : in std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end adc_ad9228; @@ -67,81 +70,33 @@ architecture Behavioral of adc_ad9228 is signal q_1_f : std_logic_vector(19 downto 0); signal q_1 : std_logic_vector(19 downto 0); - -- Merge Data - type adc_data_s is array(0 to 4) of std_logic_vector(13 downto 0); - type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); - - type BYTE_STATUS is (B_UNDEF, - B_BITSHIFTED, - B_ALIGNED, - B_SHIFTED - ); - -- ADC0 - signal adc0_data_shift : adc_data_s; - - signal adc0_data_m : adc_data_t; - signal adc0_data_clk_m : std_logic; - - signal adc0_byte_status : BYTE_STATUS; - signal adc0_byte_status_last : BYTE_STATUS; - - signal adc0_frame_clk_ok : std_logic; - signal adc0_frame_clk_ok_hist : std_logic_vector(15 downto 0); - signal adc0_frame_locked : std_logic; - signal adc0_error : std_logic; - signal adc0_error_undef : std_logic; - - -- ADC0 - signal adc1_data_shift : adc_data_s; + -- ADC Data Handler + signal adc0_error_status_c : std_logic_vector(2 downto 0); + signal adc1_error_status_c : std_logic_vector(2 downto 0); + signal adc0_error_status_sl : std_logic_vector(2 downto 0); + signal adc1_error_status_sl : std_logic_vector(2 downto 0); + signal adc0_error_status : std_logic_vector(2 downto 0); + signal adc1_error_status : std_logic_vector(2 downto 0); - signal adc1_data_m : adc_data_t; - signal adc1_data_clk_m : std_logic; - - signal adc1_byte_status : BYTE_STATUS; - signal adc1_byte_status_last : BYTE_STATUS; - - signal adc1_frame_clk_ok : std_logic; - signal adc1_frame_clk_ok_hist : std_logic_vector(15 downto 0); - signal adc1_frame_locked : std_logic; - signal adc1_error : std_logic; - signal adc1_error_undef : std_logic; - - -- Clock Transfer - signal adc0_fifo_empty : std_logic; - signal adc0_fifo_full : std_logic; - signal adc0_write_enable : std_logic; - signal adc0_read_enable : std_logic; - signal adc0_read_enable_t : std_logic; - signal adc0_read_enable_tt : std_logic; - signal adc0_locked_ff : std_logic; - signal adc0_locked_f : std_logic; - signal adc0_locked_o : std_logic; + signal adc0_sloppy_frame_f : std_logic; + signal adc0_sloppy_frame_c : std_logic; + signal adc1_sloppy_frame_f : std_logic; + signal adc1_sloppy_frame_c : std_logic; - signal adc1_fifo_empty : std_logic; - signal adc1_fifo_full : std_logic; - signal adc1_write_enable : std_logic; - signal adc1_read_enable : std_logic; - signal adc1_read_enable_t : std_logic; - signal adc1_read_enable_tt : std_logic; - signal adc1_locked_ff : std_logic; - signal adc1_locked_f : std_logic; - signal adc1_locked_o : std_logic; + -- Data Types + type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); - -- Error - signal error_adc0_o : std_logic; - signal error_adc1_o : std_logic; - signal error_undef_adc0_o : std_logic; - signal error_undef_adc1_o : std_logic; - -- Output signal adc0_data_clk_o : std_logic; - signal adc0_data_f : adc_data_t; signal adc0_data_o : adc_data_t; - + signal adc0_locked_o : std_logic; + signal adc0_error_o : std_logic; + signal adc1_data_clk_o : std_logic; - signal adc1_data_f : adc_data_t; signal adc1_data_o : adc_data_t; - + signal adc1_locked_o : std_logic; + signal adc1_error_o : std_logic; + -- RESET Handler type R_STATES is (R_IDLE, R_WAIT_CLKDIV, @@ -157,45 +112,32 @@ architecture Behavioral of adc_ad9228 is signal RESET_CLKDIV : std_logic; signal RESET_ADC0 : std_logic; signal RESET_ADC1 : std_logic; - - signal RESET_ADC0_CLKD_F : std_logic; - signal RESET_ADC0_CLKD : std_logic; - signal RESET_ADC1_CLKD_F : std_logic; - signal RESET_ADC1_CLKD : std_logic; -- attribute syn_keep : boolean; - attribute syn_keep of q_0_ff : signal is true; - attribute syn_keep of q_0_f : signal is true; - attribute syn_keep of q_1_ff : signal is true; - attribute syn_keep of q_1_f : signal is true; - - attribute syn_keep of adc0_locked_ff : signal is true; - attribute syn_keep of adc0_locked_f : signal is true; - attribute syn_keep of adc1_locked_ff : signal is true; - attribute syn_keep of adc1_locked_f : signal is true; - attribute syn_keep of RESET_ADC0_CLKD_F : signal is true; - attribute syn_keep of RESET_ADC0_CLKD : signal is true; - attribute syn_keep of RESET_ADC1_CLKD_F : signal is true; - attribute syn_keep of RESET_ADC1_CLKD : signal is true; + attribute syn_keep of q_0_ff : signal is true; + attribute syn_keep of q_0_f : signal is true; + attribute syn_keep of q_1_ff : signal is true; + attribute syn_keep of q_1_f : signal is true; + attribute syn_keep of adc0_sloppy_frame_f : signal is true; + attribute syn_keep of adc0_sloppy_frame_c : signal is true; + attribute syn_keep of adc1_sloppy_frame_f : signal is true; + attribute syn_keep of adc1_sloppy_frame_c : signal is true; + attribute syn_preserve : boolean; - attribute syn_preserve of q_0_ff : signal is true; - attribute syn_preserve of q_0_f : signal is true; - attribute syn_preserve of q_1_ff : signal is true; - attribute syn_preserve of q_1_f : signal is true; - attribute syn_preserve of adc0_locked_ff : signal is true; - attribute syn_preserve of adc0_locked_f : signal is true; - attribute syn_preserve of adc1_locked_ff : signal is true; - attribute syn_preserve of adc1_locked_f : signal is true; - - attribute syn_preserve of RESET_ADC0_CLKD_F : signal is true; - attribute syn_preserve of RESET_ADC0_CLKD : signal is true; - attribute syn_preserve of RESET_ADC1_CLKD_F : signal is true; - attribute syn_preserve of RESET_ADC1_CLKD : signal is true; - + attribute syn_preserve of q_0_ff : signal is true; + attribute syn_preserve of q_0_f : signal is true; + attribute syn_preserve of q_1_ff : signal is true; + attribute syn_preserve of q_1_f : signal is true; + + attribute syn_preserve of adc0_sloppy_frame_f : signal is true; + attribute syn_preserve of adc0_sloppy_frame_c : signal is true; + attribute syn_preserve of adc1_sloppy_frame_f : signal is true; + attribute syn_preserve of adc1_sloppy_frame_c : signal is true; + begin ----------------------------------------------------------------------------- @@ -203,8 +145,12 @@ begin ----------------------------------------------------------------------------- DFALSE: if (DEBUG_ENABLE = false) generate - DEBUG_OUT <= (others => '0'); - --DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(3 downto 1) <= adc0_error_status; + DEBUG_OUT(4) <= adc0_data_clk_o; + DEBUG_OUT(5) <= adc0_locked_o; + DEBUG_OUT(15 downto 6) <= (others => '0'); + --DEBUG_OUT(0) <= CLK_IN; --DEBUG_OUT(1) <= DDR_DATA_CLK; --DEBUG_OUT(2) <= adc0_write_enable; --DEBUG_OUT(3) <= adc0_fifo_full; @@ -226,57 +172,111 @@ begin PROC_DEBUG: process (DEBUG_IN) begin - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= DDR_DATA_CLK; + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= DDR_DATA_CLK; case DEBUG_IN is - when x"1" => - DEBUG_OUT(15 downto 2) <= adc0_data_shift(0); - - when x"2" => - DEBUG_OUT(15 downto 2) <= adc0_data_shift(1); - - when x"3" => - DEBUG_OUT(15 downto 2) <= adc0_data_shift(2); - - when x"4" => - DEBUG_OUT(15 downto 2) <= adc0_data_shift(3); - - when x"5" => - DEBUG_OUT(15 downto 2) <= adc0_data_shift(4); - when others => - -- DEBUG - DEBUG_OUT(2) <= adc0_write_enable; - DEBUG_OUT(3) <= adc0_fifo_full; - DEBUG_OUT(4) <= adc0_fifo_empty; - DEBUG_OUT(5) <= adc0_data_clk_m; - DEBUG_OUT(6) <= adc0_read_enable; - DEBUG_OUT(7) <= adc0_read_enable_t; - DEBUG_OUT(8) <= adc0_read_enable_tt; - DEBUG_OUT(9) <= adc0_data_clk_o; - DEBUG_OUT(10) <= adc0_error; - DEBUG_OUT(11) <= adc0_frame_locked; - DEBUG_OUT(12) <= adc0_frame_clk_ok; - DEBUG_OUT(13) <= wait_timer_done; - DEBUG_OUT(14) <= RESET_CLKDIV; - DEBUG_OUT(15) <= RESET_ADC0; - + DEBUG_OUT(15 downto 2) <= (others => '0'); + end case; end process PROC_DEBUG; end generate DTRUE; ----------------------------------------------------------------------------- + -- DDR Generic Interface to ADC + ----------------------------------------------------------------------------- + adc_ddr_generic_1: entity work.adc_ddr_generic + port map ( + clk_0 => ADC0_DCLK_IN, + clk_1 => ADC1_DCLK_IN, + clkdiv_reset => RESET_CLKDIV, + eclk => CLK_ADCDAT_IN, + reset_0 => RESET_ADC0, + reset_1 => RESET_ADC1, + sclk => DDR_DATA_CLK, + + datain_0(0) => ADC0_DATA_A_IN, + datain_0(1) => ADC0_DATA_B_IN, + datain_0(2) => ADC0_DATA_C_IN, + datain_0(3) => ADC0_DATA_D_IN, + datain_0(4) => ADC0_FCLK_IN, + + datain_1(0) => ADC1_DATA_A_IN, + datain_1(1) => ADC1_DATA_B_IN, + datain_1(2) => ADC1_DATA_C_IN, + datain_1(3) => ADC1_DATA_D_IN, + datain_1(4) => ADC1_FCLK_IN, + + q_0 => q_0_ff, + q_1 => q_1_ff + ); + + -- Two FIFOs to relaxe timing + q_0_f <= q_0_ff when rising_edge(DDR_DATA_CLK); + q_0 <= q_0_f when rising_edge(DDR_DATA_CLK); + + q_1_f <= q_1_ff when rising_edge(DDR_DATA_CLK); + q_1 <= q_1_f when rising_edge(DDR_DATA_CLK); - RESET_ADC0_CLKD_F <= RESET_ADC0 when rising_edge(DDR_DATA_CLK); - RESET_ADC0_CLKD <= RESET_ADC0_CLKD_F when rising_edge(DDR_DATA_CLK); + -- The ADC Data Handlers + adc0_sloppy_frame_f <= ADC0_SLOPPY_FRAME_IN when rising_edge(CLK_IN); + adc0_sloppy_frame_c <= adc0_sloppy_frame_f when rising_edge(CLK_IN); - RESET_ADC1_CLKD_F <= RESET_ADC1 when rising_edge(DDR_DATA_CLK); - RESET_ADC1_CLKD <= RESET_ADC1_CLKD_F when rising_edge(DDR_DATA_CLK); + adc_ad9228_data_handler_1: entity work.adc_ad9228_data_handler + generic map ( + DEBUG_ENABLE => DEBUG_ENABLE + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_ADC0, + DDR_DATA_CLK => DDR_DATA_CLK, + DDR_DATA_IN => q_0, + DATA_A_OUT => adc0_data_o(0), + DATA_B_OUT => adc0_data_o(1), + DATA_C_OUT => adc0_data_o(2), + DATA_D_OUT => adc0_data_o(3), + DATA_CLK_OUT => adc0_data_clk_o, + SLOPPY_FRAME_IN => adc0_sloppy_frame_c, + FRAME_LOCKED_OUT => adc0_locked_o, + ERROR_STATUS_OUT => adc0_error_status, + ERROR_STATUS_SL_OUT => adc0_error_status_sl, + DEBUG_OUT => open + ); + + adc1_sloppy_frame_f <= ADC1_SLOPPY_FRAME_IN when rising_edge(CLK_IN); + adc1_sloppy_frame_c <= adc1_sloppy_frame_f when rising_edge(CLK_IN); + + adc_ad9228_data_handler_2: entity work.adc_ad9228_data_handler + generic map ( + DEBUG_ENABLE => DEBUG_ENABLE + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_ADC1, + DDR_DATA_CLK => DDR_DATA_CLK, + DDR_DATA_IN => q_1, + DATA_A_OUT => adc1_data_o(0), + DATA_B_OUT => adc1_data_o(1), + DATA_C_OUT => adc1_data_o(2), + DATA_D_OUT => adc1_data_o(3), + DATA_CLK_OUT => adc1_data_clk_o, + SLOPPY_FRAME_IN => adc1_sloppy_frame_c, + FRAME_LOCKED_OUT => adc1_locked_o, + ERROR_STATUS_OUT => open, --ERROR_STATUS_OUT, + ERROR_STATUS_SL_OUT => open, --ERROR_STATUS_OUT, + DEBUG_OUT => open + ); ----------------------------------------------------------------------------- + -- Error Status Handler + ----------------------------------------------------------------------------- + + ----------------------------------------------------------------------------- + -- Reset Handler + ----------------------------------------------------------------------------- timer_static_RESET_TIMER: timer_static generic map ( @@ -294,12 +294,11 @@ begin begin if (rising_edge(CLK_IN)) then if (RESET_IN = '1') then - RESET_CLKDIV <= '1'; - RESET_ADC0 <= '1'; - RESET_ADC1 <= '1'; + RESET_CLKDIV <= '0'; + RESET_ADC0 <= '0'; + RESET_ADC1 <= '0'; wait_timer_start <= '0'; timer_reset <= '1'; - startup_reset <= '1'; R_STATE <= R_IDLE; else RESET_CLKDIV <= '0'; @@ -307,11 +306,10 @@ begin RESET_ADC1 <= '0'; wait_timer_start <= '0'; timer_reset <= '0'; - startup_reset <= '0'; - + case R_STATE is when R_IDLE => - if (startup_reset = '1') then + if (RESET_ADCS = '1') then -- Start Reset RESET_CLKDIV <= '1'; RESET_ADC0 <= '1'; @@ -360,451 +358,30 @@ begin end process PROC_DDR_RESET_HANDLER; ----------------------------------------------------------------------------- - - adc_ddr_generic_1: entity work.adc_ddr_generic - port map ( - clk_0 => ADC0_DCLK_IN, - clk_1 => ADC1_DCLK_IN, - clkdiv_reset => RESET_CLKDIV, - eclk => CLK_ADCDAT_IN, - reset_0 => RESET_ADC0, - reset_1 => RESET_ADC1, - sclk => DDR_DATA_CLK, - - datain_0(0) => ADC0_DATA_A_IN, - datain_0(1) => ADC0_DATA_B_IN, - datain_0(2) => ADC0_DATA_C_IN, - datain_0(3) => ADC0_DATA_D_IN, - datain_0(4) => ADC0_FCLK_IN, - - datain_1(0) => ADC1_DATA_A_IN, - datain_1(1) => ADC1_DATA_B_IN, - datain_1(2) => ADC1_DATA_C_IN, - datain_1(3) => ADC1_DATA_D_IN, - datain_1(4) => ADC1_FCLK_IN, - - q_0 => q_0_ff, - q_1 => q_1_ff - ); - - -- Two Input FIFOs to relaxe timing - q_0_f <= q_0_ff when rising_edge(DDR_DATA_CLK); - q_0 <= q_0_f when rising_edge(DDR_DATA_CLK); - - q_1_f <= q_1_ff when rising_edge(DDR_DATA_CLK); - q_1 <= q_1_f when rising_edge(DDR_DATA_CLK); - - ----------------------------------------------------------------------------- - - PROC_MERGE_DATA_ADC0: process(DDR_DATA_CLK) - begin - if (rising_edge(DDR_DATA_CLK)) then - if (RESET_ADC0_CLKD = '1') then - for I in 0 to 4 loop - adc0_data_shift(I) <= (others => '0'); - end loop; - - for I in 0 to 3 loop - adc0_data_m(I) <= (others => '0'); - end loop; - adc0_data_clk_m <= '0'; - - adc0_byte_status <= B_UNDEF; - adc0_byte_status_last <= B_UNDEF; - adc0_frame_clk_ok <= '0'; - adc0_frame_clk_ok_hist <= (others => '0'); - adc0_frame_locked <= '0'; - adc0_error <= '0'; - adc0_error_undef <= '0'; - else - -- Store new incoming Data in Shift Registers - for I in 0 to 4 loop - adc0_data_shift(I)(3) <= q_0(I + 0); - adc0_data_shift(I)(2) <= q_0(I + 5); - adc0_data_shift(I)(1) <= q_0(I + 10); - adc0_data_shift(I)(0) <= q_0(I + 15); - adc0_data_shift(I)(13 downto 4) <= adc0_data_shift(I)(9 downto 0); - end loop; - - -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock - case adc0_data_shift(4)(11 downto 0) is - when "111111000000" => - -- Input Data is correct and new Frame is available - for I in 0 to 3 loop - adc0_data_m(I) <= adc0_data_shift(I)(11 downto 0); - end loop; - adc0_data_clk_m <= '1'; - adc0_frame_clk_ok <= '1'; - adc0_byte_status <= B_ALIGNED; - - when "111100000011" => - -- Input Data is correct and new Frame is available, - -- but byte shifted by one - for I in 0 to 3 loop - adc0_data_m(I) <= adc0_data_shift(I)(13 downto 2); - end loop; - adc0_data_clk_m <= '1'; - adc0_frame_clk_ok <= '1'; - adc0_byte_status <= B_SHIFTED; - - when "110000001111" | "000011111100" => - -- Input Data is correct - adc0_data_clk_m <= '0'; - adc0_frame_clk_ok <= '1'; - adc0_byte_status <= B_ALIGNED; - - when "000000111111" | "001111110000" => - -- Input Data is correct - adc0_data_clk_m <= '0'; - adc0_frame_clk_ok <= '1'; - adc0_byte_status <= B_SHIFTED; - - when "000001111110" | - "000111111000" | - "011111100000" | - "111110000001" | - "111000000111" | - "100000011111" => - adc0_data_clk_m <= '0'; - adc0_frame_clk_ok <= '0'; - adc0_byte_status <= B_BITSHIFTED; - - when others => - -- Input Data is invalid, Fatal Error of DDR Data, needs reset. - adc0_data_clk_m <= '0'; - adc0_frame_clk_ok <= '0'; - adc0_byte_status <= B_UNDEF; - - end case; - - -- Determin ADC Frame Lock Status - adc0_frame_clk_ok_hist(0) <= adc0_frame_clk_ok; - adc0_frame_clk_ok_hist(15 downto 1) <= - adc0_frame_clk_ok_hist(14 downto 0); - - if (adc0_frame_clk_ok_hist = x"ffff") then - adc0_frame_locked <= '1'; - else - adc0_frame_locked <= '0'; - end if; - - -- Error Status - adc0_byte_status_last <= adc0_byte_status; - --if (adc0_byte_status /= adc0_byte_status_last and - -- adc0_byte_status /= B_UNDEF and - -- adc0_byte_status_last /= B_UNDEF) then - if (adc0_byte_status = B_BITSHIFTED) then - adc0_error <= '1'; - else - adc0_error <= '0'; - end if; - - if (adc0_byte_status = B_UNDEF) then - adc0_error_undef <= '1'; - else - adc0_error_undef <= '0'; - end if; - - end if; - - end if; - end process PROC_MERGE_DATA_ADC0; - - ----------------------------------------------------------------------------- - - PROC_MERGE_DATA_ADC1: process(DDR_DATA_CLK) - begin - if (rising_edge(DDR_DATA_CLK)) then - if (RESET_ADC1_CLKD = '1') then - for I in 0 to 4 loop - adc1_data_shift(I) <= (others => '0'); - end loop; - - for I in 0 to 3 loop - adc1_data_m(I) <= (others => '0'); - end loop; - adc1_data_clk_m <= '0'; - - adc1_byte_status <= B_UNDEF; - adc1_byte_status_last <= B_UNDEF; - adc1_frame_clk_ok <= '0'; - adc1_frame_clk_ok_hist <= (others => '0'); - adc1_frame_locked <= '0'; - adc1_error <= '0'; - else - - -- Store new incoming Data in Shift Registers - for I in 0 to 4 loop - adc1_data_shift(I)(3) <= q_1(I + 0); - adc1_data_shift(I)(2) <= q_1(I + 5); - adc1_data_shift(I)(1) <= q_1(I + 10); - adc1_data_shift(I)(0) <= q_1(I + 15); - - adc1_data_shift(I)(13 downto 4) <= adc1_data_shift(I)(9 downto 0); - end loop; - - -- Check Frame Lock and valid Status, Index 4 is THE Frame Clock - case adc1_data_shift(4)(11 downto 0) is - when "111111000000" => - -- Input Data is correct and new Frame is available - for I in 0 to 3 loop - adc1_data_m(I) <= adc1_data_shift(I)(11 downto 0); - end loop; - adc1_data_clk_m <= '1'; - adc1_frame_clk_ok <= '1'; - adc1_byte_status <= B_ALIGNED; - - when "111100000011" => - -- Input Data is correct and new Frame is available, - -- but byte shifted by one - for I in 0 to 3 loop - adc1_data_m(I) <= adc1_data_shift(I)(13 downto 2); - end loop; - adc1_data_clk_m <= '1'; - adc1_frame_clk_ok <= '1'; - adc1_byte_status <= B_SHIFTED; - - when "110000001111" | "000011111100" => - -- Input Data is correct - adc1_data_clk_m <= '0'; - adc1_frame_clk_ok <= '1'; - adc1_byte_status <= B_ALIGNED; - - when "000000111111" | "001111110000" => - -- Input Data is correct - adc1_data_clk_m <= '0'; - adc1_frame_clk_ok <= '1'; - adc1_byte_status <= B_SHIFTED; - - when others => - -- Input Data is invalid, Fatal Error of DDR Data, needs reset. - adc1_data_clk_m <= '0'; - adc1_frame_clk_ok <= '0'; - adc1_byte_status <= B_UNDEF; - - end case; - - -- Determin ADC Frame Lock Status - adc1_frame_clk_ok_hist(0) <= adc1_frame_clk_ok; - adc1_frame_clk_ok_hist(15 downto 1) <= - adc1_frame_clk_ok_hist(14 downto 0); - - if (adc1_frame_clk_ok_hist = x"ffff") then - adc1_frame_locked <= '1'; - else - adc1_frame_locked <= '0'; - end if; - - -- Error Status - adc1_byte_status_last <= adc1_byte_status; - if (adc1_byte_status /= adc1_byte_status_last) then - adc1_error <= '1'; - else - adc1_error <= '0'; - end if; - - if (adc1_byte_status = B_UNDEF) then - adc1_error_undef <= '1'; - else - adc1_error_undef <= '0'; - end if; - - end if; - end if; - end process PROC_MERGE_DATA_ADC1; - - - ----------------------------------------------------------------------------- - -- Tansfer to CLK_IN + -- Outputs ----------------------------------------------------------------------------- - - fifo_adc_48to48_dc_1: entity work.fifo_adc_48to48_dc - port map ( - Data(11 downto 0) => adc0_data_m(0), - Data(23 downto 12) => adc0_data_m(1), - Data(35 downto 24) => adc0_data_m(2), - Data(47 downto 36) => adc0_data_m(3), - WrClock => DDR_DATA_CLK, - RdClock => CLK_IN, - WrEn => adc0_write_enable, - RdEn => adc0_read_enable, - Reset => RESET_ADC0_CLKD, - RPReset => RESET_ADC0, - Q(11 downto 0) => adc0_data_f(0), - Q(23 downto 12) => adc0_data_f(1), - Q(35 downto 24) => adc0_data_f(2), - Q(47 downto 36) => adc0_data_f(3), - Empty => adc0_fifo_empty, - Full => adc0_fifo_full - ); - - -- Readout Handler - adc0_write_enable <= adc0_data_clk_m and not adc0_fifo_full; - adc0_read_enable <= not adc0_fifo_empty; - - PROC_ADC0_FIFO_READ: process(CLK_IN) - begin - if (rising_edge(CLK_IN)) then - adc0_read_enable_t <= adc0_read_enable; - if (RESET_ADC0_CLKD = '1') then - adc0_read_enable_tt <= '0'; - for I in 0 to 3 loop - adc0_data_o(I) <= (others => '0'); - end loop; - adc0_data_clk_o <= '0'; - else - -- Read enable - adc0_read_enable_tt <= adc0_read_enable_t; - - if (adc0_read_enable_tt = '1') then - for I in 0 to 3 loop - adc0_data_o(I) <= adc0_data_f(I); - end loop; - adc0_data_clk_o <= '1'; - else - adc0_data_clk_o <= '0'; - end if; - end if; - end if; - end process PROC_ADC0_FIFO_READ; - - ----------------------------------------------------------------------------- - - fifo_adc_48to48_dc_2: entity work.fifo_adc_48to48_dc - port map ( - Data(11 downto 0) => adc1_data_m(0), - Data(23 downto 12) => adc1_data_m(1), - Data(35 downto 24) => adc1_data_m(2), - Data(47 downto 36) => adc1_data_m(3), - WrClock => DDR_DATA_CLK, - RdClock => CLK_IN, - WrEn => adc1_write_enable, - RdEn => adc1_read_enable, - Reset => RESET_ADC1_CLKD, - RPReset => RESET_ADC1, - Q(11 downto 0) => adc1_data_f(0), - Q(23 downto 12) => adc1_data_f(1), - Q(35 downto 24) => adc1_data_f(2), - Q(47 downto 36) => adc1_data_f(3), - Empty => adc1_fifo_empty, - Full => adc1_fifo_full - ); - - -- Readout Handler - adc1_write_enable <= adc1_data_clk_m and not adc1_fifo_full; - adc1_read_enable <= not adc1_fifo_empty; - - PROC_ADC1_FIFO_READ: process(CLK_IN) - begin - if (rising_edge(CLK_IN)) then - if (RESET_ADC1_CLKD = '1') then - adc1_read_enable_t <= '0'; - adc1_read_enable_tt <= '0'; - for I in 0 to 3 loop - adc1_data_o(I) <= (others => '0'); - end loop; - adc1_data_clk_o <= '0'; - else - -- Read enable - adc1_read_enable_t <= adc1_read_enable; - adc1_read_enable_tt <= adc1_read_enable_t; - - if (adc1_read_enable_tt = '1') then - for I in 0 to 3 loop - adc1_data_o(I) <= adc1_data_f(I); - end loop; - adc1_data_clk_o <= '1'; - else - adc1_data_clk_o <= '0'; - end if; - end if; - end if; - end process PROC_ADC1_FIFO_READ; - - -- Domain Transfer - adc0_locked_ff <= adc0_frame_locked when rising_edge(CLK_IN); - adc0_locked_f <= adc0_locked_ff when rising_edge(CLK_IN); - adc0_locked_o <= adc0_locked_f when rising_edge(CLK_IN); - - adc1_locked_ff <= adc1_frame_locked when rising_edge(CLK_IN); - adc1_locked_f <= adc1_locked_ff when rising_edge(CLK_IN); - adc1_locked_o <= adc1_locked_f when rising_edge(CLK_IN); - - pulse_dtrans_ADC0_ERROR: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) - port map ( - CLK_A_IN => DDR_DATA_CLK, - RESET_A_IN => '0', - PULSE_A_IN => adc0_error, - CLK_B_IN => CLK_IN, - RESET_B_IN => '0', - PULSE_B_OUT => error_adc0_o - ); - - pulse_dtrans_ADC1_ERROR: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) - port map ( - CLK_A_IN => DDR_DATA_CLK, - RESET_A_IN => '0', - PULSE_A_IN => adc1_error, - CLK_B_IN => CLK_IN, - RESET_B_IN => '0', - PULSE_B_OUT => error_adc1_o - ); - - pulse_dtrans_ADC0_ERROR_UNDEF: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) - port map ( - CLK_A_IN => DDR_DATA_CLK, - RESET_A_IN => '0', - PULSE_A_IN => adc0_error_undef, - CLK_B_IN => CLK_IN, - RESET_B_IN => '0', - PULSE_B_OUT => error_undef_adc0_o - ); - - pulse_dtrans_ADC1_ERROR_UNDEF: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) - port map ( - CLK_A_IN => DDR_DATA_CLK, - RESET_A_IN => '0', - PULSE_A_IN => adc1_error_undef, - CLK_B_IN => CLK_IN, - RESET_B_IN => '0', - PULSE_B_OUT => error_undef_adc1_o - ); - - -- Output - ADC0_SCLK_OUT <= ADC0_SCLK_IN; - ADC1_SCLK_OUT <= ADC1_SCLK_IN; - - ADC0_DATA_A_OUT <= adc0_data_o(0); - ADC0_DATA_B_OUT <= adc0_data_o(1); - ADC0_DATA_C_OUT <= adc0_data_o(2); - ADC0_DATA_D_OUT <= adc0_data_o(3); - ADC0_DATA_CLK_OUT <= adc0_data_clk_o; - - ADC1_DATA_A_OUT <= adc1_data_o(0); - ADC1_DATA_B_OUT <= adc1_data_o(1); - ADC1_DATA_C_OUT <= adc1_data_o(2); - ADC1_DATA_D_OUT <= adc1_data_o(3); - ADC1_DATA_CLK_OUT <= adc1_data_clk_o; - - ADC0_LOCKED_OUT <= adc0_locked_o; - ADC1_LOCKED_OUT <= adc1_locked_o; - - ERROR_ADC0_OUT <= error_adc0_o; - ERROR_ADC1_OUT <= error_adc1_o; - - ERROR_UNDEF_ADC0_OUT <= error_undef_adc0_o; - ERROR_UNDEF_ADC1_OUT <= error_undef_adc1_o; + ADC0_SCLK_OUT <= ADC0_SCLK_IN; + ADC1_SCLK_OUT <= ADC1_SCLK_IN; + ADC0_DATA_A_OUT <= adc0_data_o(0); + ADC0_DATA_B_OUT <= adc0_data_o(1); + ADC0_DATA_C_OUT <= adc0_data_o(2); + ADC0_DATA_D_OUT <= adc0_data_o(3); + ADC0_DATA_CLK_OUT <= adc0_data_clk_o; + + ADC1_DATA_A_OUT <= adc1_data_o(0); + ADC1_DATA_B_OUT <= adc1_data_o(1); + ADC1_DATA_C_OUT <= adc1_data_o(2); + ADC1_DATA_D_OUT <= adc1_data_o(3); + ADC1_DATA_CLK_OUT <= adc1_data_clk_o; + + ADC0_LOCKED_OUT <= adc0_locked_o; + ADC1_LOCKED_OUT <= adc1_locked_o; + + ADC0_ERROR_STATUS_OUT <= adc0_error_status_c + when adc0_sloppy_frame_c = '0' + else adc0_error_status_sl; + ADC1_ERROR_STATUS_OUT <= adc1_error_status_c + when adc1_sloppy_frame_c = '0' + else adc1_error_status_sl; end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 94fcb86..78a1ea5 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -177,14 +177,13 @@ architecture Behavioral of nx_data_receiver is signal rate_timer_ctr : unsigned(27 downto 0); -- Error + signal adc_error_status_i : std_logic_vector(2 downto 0); signal adc_error_i : std_logic; - signal adc_error_undef_i : std_logic; - signal error_o : std_logic; - signal error_status_bits : std_logic_vector(15 downto 0); signal adc_notlock_counter : unsigned(27 downto 0); signal adc_error_counter : unsigned(27 downto 0); - signal adc_error_undef_counter : unsigned(27 downto 0); - + + signal error_o : std_logic; + signal error_status_bits : std_logic_vector(15 downto 0); -- Rate Errors signal nx_frame_rate_offline_last : std_logic; signal nx_frame_rate_offline : std_logic; @@ -238,7 +237,6 @@ architecture Behavioral of nx_data_receiver is signal reset_parity_error_ctr : std_logic; signal debug_mode : std_logic_vector(2 downto 0); signal reset_handler_start_r : std_logic; - signal adc_bit_shift : unsigned(3 downto 0); signal johnson_counter_sync_r : unsigned(1 downto 0); signal pll_adc_sample_clk_dphase_r : unsigned(3 downto 0); signal pll_adc_sample_clk_finedelb_r : unsigned(3 downto 0); @@ -247,8 +245,6 @@ architecture Behavioral of nx_data_receiver is signal nx_timestamp_delay_a : unsigned(2 downto 0); signal nx_timestamp_delay_s : unsigned(2 downto 0); signal nx_timestamp_delay_actr : unsigned(15 downto 0); - signal nx_frame_word_delay_rr : unsigned(1 downto 0); - signal nx_frame_word_delay_reg : unsigned(1 downto 0); signal fifo_full_rr : std_logic; signal fifo_full_r : std_logic; signal fifo_empty_rr : std_logic; @@ -269,6 +265,7 @@ architecture Behavioral of nx_data_receiver is -- Reset Handler ----------------------------------------------------------------------------- signal disable_resets : std_logic; + signal disable_adc_resets : std_logic; signal nx_online_ii : std_logic; signal nx_online_i : std_logic; signal adc_error : std_logic; @@ -317,6 +314,7 @@ architecture Behavioral of nx_data_receiver is signal adc_reset_handler_cnx_ff : std_logic; signal adc_reset_handler_cnx_f : std_logic; signal adc_reset_handler_cnx : std_logic; + -- Resync Counter Process signal resync_counter : unsigned(11 downto 0); signal resync_ctr_inc : std_logic; @@ -362,9 +360,6 @@ architecture Behavioral of nx_data_receiver is attribute syn_keep of nx_frame_word_f : signal is true; - attribute syn_keep of nx_frame_word_delay_rr : signal is true; - attribute syn_keep of nx_frame_word_delay_reg : signal is true; - attribute syn_preserve : boolean; attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true; attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true; @@ -389,9 +384,6 @@ architecture Behavioral of nx_data_receiver is attribute syn_preserve of nx_frame_word_f : signal is true; - attribute syn_preserve of nx_frame_word_delay_rr : signal is true; - attribute syn_preserve of nx_frame_word_delay_reg : signal is true; - begin DFALSE: if (DEBUG_ENABLE = false) generate @@ -917,6 +909,7 @@ begin PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_DATA_CLK_IN) begin if (rising_edge(NX_DATA_CLK_IN)) then + nx_frame_word_delay <= nx_frame_word_delay_f; nx_frame_word_delayed_t(0) <= nx_frame_word; nx_frame_clk_delayed_t(0) <= nx_frame_clk; @@ -937,7 +930,6 @@ begin PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_DATA_CLK_IN) begin if (rising_edge(NX_DATA_CLK_IN)) then - nx_frame_word_delay <= nx_frame_word_delay_f; adc_data_clk_last(0) <= adc_data_s_clk; if (RESET_NX_DATA_CLK_IN = '1') then @@ -995,24 +987,25 @@ begin adc_reset_handler_cnx <= adc_reset_handler_cnx_f when rising_edge(NX_DATA_CLK_IN); - ADC_RESET_AD9228 <= RESET_NX_DATA_CLK_IN or - adc_reset_handler_cnx; - - adc_debug_type_f <= adc_debug_type_r when rising_edge(NX_DATA_CLK_IN); adc_debug_type <= adc_debug_type_f when rising_edge(NX_DATA_CLK_IN); + ----------------------------------------------------------------------------- + + ADC_RESET_AD9228 <= RESET_NX_DATA_CLK_IN or adc_reset_handler_cnx; + adc_ad9228_1: adc_ad9228 generic map ( DEBUG_ENABLE => false ) port map ( CLK_IN => NX_DATA_CLK_IN, - RESET_IN => ADC_RESET_AD9228, + RESET_IN => RESET_NX_DATA_CLK_IN, CLK_ADCDAT_IN => ADC_CLK_DAT_IN, - + RESET_ADCS => ADC_RESET_AD9228, + ADC0_SCLK_IN => pll_adc_sampling_clk_o, ADC0_SCLK_OUT => ADC_SAMPLE_CLK_OUT, ADC0_DATA_A_IN => ADC_NX_IN(0), @@ -1046,11 +1039,11 @@ begin ADC0_LOCKED_OUT => adc_locked, ADC1_LOCKED_OUT => open, - ERROR_ADC0_OUT => adc_error_i, - ERROR_ADC1_OUT => open, + ADC0_SLOPPY_FRAME_IN => adc_sloppy_frame, + ADC1_SLOPPY_FRAME_IN => '0', - ERROR_UNDEF_ADC0_OUT => adc_error_undef_i, - ERROR_UNDEF_ADC1_OUT => open, + ADC0_ERROR_STATUS_OUT => adc_error_status_i, + ADC1_ERROR_STATUS_OUT => open, DEBUG_IN => adc_debug_type, DEBUG_OUT => ADC_DEBUG @@ -1467,7 +1460,7 @@ begin rs_timeout_timer_reset <= '0'; reset_handler_busy <= '1'; nx_timestamp_reset_o <= '0'; - + debug_state <= x"0"; if (disable_resets = '0') then @@ -1483,16 +1476,15 @@ begin -- Reset Timeout, retry RESET rs_timeout_timer_reset <= '1'; reset_timeout_flag <= '1'; - reset_handler_trigger(0) <= '0'; reset_handler_trigger(1) <= '1'; - reset_handler_trigger(15 downto 2) <= (others => '0'); R_STATE <= R_START; else case R_STATE is when R_IDLE => if (NX_CLOCK_ON_IN = '1') then - if ((disable_adc_r = '0' and + if ((disable_adc_r = '0' and + disable_adc_resets = '0' and (pll_adc_not_lock = '1' or adc_reset_sync = '1' or adc_frame_rate_error = '1' or @@ -1505,24 +1497,23 @@ begin nx_frame_rate_error = '1' or startup_reset = '1' or timestamp_dt_error = '1' or - parity_rate_error = '1' or - nx_frame_rate_error = '1' + parity_rate_error = '1' ) then - reset_handler_trigger(1 downto 0) <= (others => '0'); + reset_handler_trigger( 0) <= '0'; + reset_handler_trigger( 1) <= '0'; reset_handler_trigger( 2) <= nx_frame_rate_error; reset_handler_trigger( 3) <= startup_reset; reset_handler_trigger( 4) <= timestamp_dt_error; reset_handler_trigger( 5) <= parity_rate_error; - reset_handler_trigger( 6) <= nx_frame_rate_error; reset_handler_trigger( 7) <= pll_adc_not_lock; reset_handler_trigger( 8) <= adc_reset_sync; reset_handler_trigger( 9) <= adc_frame_rate_error; - reset_handler_trigger(10) <= adc_error; + reset_handler_trigger(10) <= '0'; --adc_error; reset_handler_trigger(11) <= adc_dt_error ; reset_handler_trigger(12) <= not adc_sclk_ok_c100; reset_handler_trigger(13) <= not adc_locked_c100; - reset_handler_trigger(15 downto 4) <= (others => '0'); + reset_handler_trigger(15 downto 14) <= (others => '0'); R_STATE <= R_RESET_TIMESTAMP; else @@ -1534,6 +1525,7 @@ begin else reset_timeout_flag <= '0'; rs_timeout_timer_reset <= '1'; + reset_handler_trigger <= (others => '0'); R_STATE <= R_IDLE; end if; debug_state <= x"1"; @@ -1627,7 +1619,7 @@ begin output_handler_reset <= '1'; fifo_reset_handler <= '1'; if (disable_adc_r = '0') then - R_STATE <= R_PLL_WAIT_LOCK; + R_STATE <= R_PLL_WAIT_LOCK; else R_STATE <= R_WAIT_DATA_HANDLER_OK; end if; @@ -1680,6 +1672,13 @@ begin debug_state <= x"b"; end case; end if; + + else + -- Reset Disabled + reset_timeout_flag <= '0'; + rs_timeout_timer_reset <= '1'; + reset_handler_trigger <= (others => '0'); + debug_state <= x"f"; end if; end if; end if; @@ -1695,7 +1694,8 @@ begin LEVEL_IN => not adc_locked_c100, PULSE_OUT => adc_notlocked_p ); - + + adc_error_i <= '0' when adc_error_status_i = "000" else '1'; pulse_dtrans_ADC_ERROR: pulse_dtrans generic map ( CLK_RATIO => 2 @@ -1709,20 +1709,6 @@ begin PULSE_B_OUT => adc_error ); - pulse_dtrans_ADC_ERROR_UNDEF: pulse_dtrans - generic map ( - CLK_RATIO => 2 - ) - port map ( - CLK_A_IN => NX_DATA_CLK_IN, - RESET_A_IN => RESET_NX_DATA_CLK_IN, - PULSE_A_IN => adc_error_undef_i, - CLK_B_IN => CLK_IN, - RESET_B_IN => RESET_IN, - PULSE_B_OUT => adc_error_undef - ); - - PROC_ERROR_STATUS: process(CLK_IN) variable error_mask : std_logic_vector(15 downto 0); begin @@ -1734,7 +1720,6 @@ begin error_o <= '0'; adc_notlock_counter <= (others => '0'); adc_error_counter <= (others => '0'); - adc_error_undef_counter <= (others => '0'); else adc_sclk_ok_c100 <= adc_sclk_ok_f; @@ -1751,10 +1736,10 @@ begin error_status_bits(10) <= timestamp_dt_error; error_status_bits(11) <= adc_dt_error; error_status_bits(12) <= reset_handler_busy; - error_status_bits(15 downto 13) <= (others => '0'); + error_status_bits(15 downto 13) <= adc_error_status_i; if (disable_adc_r = '1') then - error_mask := x"f437"; + error_mask := x"1437"; else error_mask := x"0000"; end if; @@ -1773,10 +1758,6 @@ begin adc_error_counter <= adc_error_counter + 1; end if; - if (adc_error_undef = '1') then - adc_error_undef_counter <= adc_error_undef_counter + 1; - end if; - end if; end if; end process PROC_ERROR_STATUS; @@ -1819,7 +1800,6 @@ begin fifo_full_rr <= fifo_full; fifo_empty_rr <= fifo_empty; nx_frame_synced_rr <= nx_frame_synced; - nx_frame_word_delay_rr <= nx_frame_word_delay_f; if (RESET_IN = '1') then fifo_full_r <= '0'; @@ -1829,7 +1809,6 @@ begin new_timestamp_dt_error_ctr_r <= (others => '0'); adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); - nx_frame_word_delay_reg <= (others => '0'); else fifo_full_r <= fifo_full_rr; fifo_empty_r <= fifo_empty_rr; @@ -1838,7 +1817,6 @@ begin new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr; adc_notlock_ctr_r <= adc_notlock_ctr; merge_error_ctr_r <= merge_error_ctr; - nx_frame_word_delay_reg <= nx_frame_word_delay_rr; end if; end if; end process PROC_SLAVE_BUS_BUFFER; @@ -1862,13 +1840,13 @@ begin nx_timestamp_delay_adjust <= '1'; nx_timestamp_delay_r <= "010"; reset_handler_start_r <= '0'; - adc_bit_shift <= x"0"; adc_debug_type_r <= (others => '0'); debug_mode <= (others => '0'); disable_adc_r <= '0'; adc_sloppy_frame <= '0'; reset_inhibit_r <= '0'; + disable_adc_resets <= '0'; disable_resets <= '0'; else slv_data_out_o <= (others => '0'); @@ -1890,8 +1868,9 @@ begin when x"0001" => slv_data_out_o(0) <= reset_handler_busy; slv_data_out_o(1) <= reset_timeout_flag; - slv_data_out_o(2) <= disable_resets; - slv_data_out_o(15 downto 3) <= (others => '0'); + slv_data_out_o(2) <= disable_adc_resets; + slv_data_out_o(3) <= disable_resets; + slv_data_out_o(15 downto 4) <= (others => '0'); slv_data_out_o(31 downto 16) <= reset_handler_trigger; slv_ack_o <= '1'; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 14c91d2..fc798a8 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -216,43 +216,44 @@ component adc_ad9228 generic ( DEBUG_ENABLE : boolean); port ( - CLK_IN : in std_logic; - RESET_IN : in std_logic; - CLK_ADCDAT_IN : in std_logic; - ADC0_SCLK_IN : in std_logic; - ADC0_SCLK_OUT : out std_logic; - ADC0_DATA_A_IN : in std_logic; - ADC0_DATA_B_IN : in std_logic; - ADC0_DATA_C_IN : in std_logic; - ADC0_DATA_D_IN : in std_logic; - ADC0_DCLK_IN : in std_logic; - ADC0_FCLK_IN : in std_logic; - ADC1_SCLK_IN : in std_logic; - ADC1_SCLK_OUT : out std_logic; - ADC1_DATA_A_IN : in std_logic; - ADC1_DATA_B_IN : in std_logic; - ADC1_DATA_C_IN : in std_logic; - ADC1_DATA_D_IN : in std_logic; - ADC1_DCLK_IN : in std_logic; - ADC1_FCLK_IN : in std_logic; - ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC0_DATA_CLK_OUT : out std_logic; - ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); - ADC1_DATA_CLK_OUT : out std_logic; - ADC0_LOCKED_OUT : out std_logic; - ADC1_LOCKED_OUT : out std_logic; - ERROR_ADC0_OUT : out std_logic; - ERROR_ADC1_OUT : out std_logic; - ERROR_UNDEF_ADC0_OUT : out std_logic; - ERROR_UNDEF_ADC1_OUT : out std_logic; - DEBUG_IN : in std_logic_vector(3 downto 0); - DEBUG_OUT : out std_logic_vector(15 downto 0) + CLK_IN : in std_logic; + RESET_IN : in std_logic; + CLK_ADCDAT_IN : in std_logic; + RESET_ADCS : in std_logic; + ADC0_SCLK_IN : in std_logic; + ADC0_SCLK_OUT : out std_logic; + ADC0_DATA_A_IN : in std_logic; + ADC0_DATA_B_IN : in std_logic; + ADC0_DATA_C_IN : in std_logic; + ADC0_DATA_D_IN : in std_logic; + ADC0_DCLK_IN : in std_logic; + ADC0_FCLK_IN : in std_logic; + ADC1_SCLK_IN : in std_logic; + ADC1_SCLK_OUT : out std_logic; + ADC1_DATA_A_IN : in std_logic; + ADC1_DATA_B_IN : in std_logic; + ADC1_DATA_C_IN : in std_logic; + ADC1_DATA_D_IN : in std_logic; + ADC1_DCLK_IN : in std_logic; + ADC1_FCLK_IN : in std_logic; + ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC0_DATA_CLK_OUT : out std_logic; + ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); + ADC1_DATA_CLK_OUT : out std_logic; + ADC0_LOCKED_OUT : out std_logic; + ADC1_LOCKED_OUT : out std_logic; + ADC0_SLOPPY_FRAME_IN : in std_logic; + ADC1_SLOPPY_FRAME_IN : in std_logic; + ADC0_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); + ADC1_ERROR_STATUS_OUT : out std_logic_vector(2 downto 0); + DEBUG_IN : in std_logic_vector(3 downto 0); + DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index 4f32fbd..7a22249 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -197,6 +197,7 @@ add_file -vhdl -lib "work" "source/adc_spi_master.vhd" add_file -vhdl -lib "work" "source/adc_spi_sendbyte.vhd" add_file -vhdl -lib "work" "source/adc_spi_readbyte.vhd" add_file -vhdl -lib "work" "source/adc_ad9228.vhd" +add_file -vhdl -lib "work" "source/adc_ad9228_data_handler.vhd" add_file -vhdl -lib "work" "source/nx_fpga_timestamp.vhd" add_file -vhdl -lib "work" "source/nx_trigger_generator.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index ba84272..37d592d 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -100,28 +100,22 @@ MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_handler_cn MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/reset_handler_start_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/johnson_counter_sync_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_delay_s*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_word_delay_reg*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_r*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_finedelb_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sample_clk_dphase_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/pll_adc_sampling_clk_reset*" 100 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_bit_shift*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_adc_dt_error_ctr_*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/new_timestamp_dt_error_ctr_*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_sclk_ok_f*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_r*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_timestamp_reset_o*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_full_rr*" 100 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/fifo_empty_rr*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/nx_frame_synced_rr*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/disable_adc_f*" 100 ns; MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_debug_type_f*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_error_status_i_*" 100 ns; + +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc_ad9228_data_handler*/adc_locked_o*" 100 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_sloppy_frame_c*" 200 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_CLKDIV*" 30 ns; -MULTICYCLE TO CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/RESET_ADC0_CLKD_F*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/adc0_locked_o*" 100 ns; - MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_mode_r_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/cts_trigger_delay_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_*" 100 ns;