From: Jan Michel Date: Fri, 16 Oct 2015 10:08:13 +0000 (+0200) Subject: PLL regenerated X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=60828efad00fa4421b7c879771134acfb45e1720;p=trb3.git PLL regenerated --- diff --git a/base/cores/pll_200_4.ipx b/base/cores/pll_200_4.ipx index 278881d..5aedab1 100644 --- a/base/cores/pll_200_4.ipx +++ b/base/cores/pll_200_4.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/pll_200_4.lpc b/base/cores/pll_200_4.lpc index d9d8853..93246ca 100644 --- a/base/cores/pll_200_4.lpc +++ b/base/cores/pll_200_4.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=PLL -CoreRevision=5.3 +CoreRevision=5.4 ModuleName=pll_200_4 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=10/07/2014 -Time=15:22:29 +Date=07/03/2015 +Time=18:18:12 [Parameters] Verilog=0 @@ -38,7 +38,7 @@ OP_Tol=0.0 OFrq=4.000000 DutyTrimP=Rising DelayMultP=0 -fb_mode=CLKOP +fb_mode=Internal Mult=1 Phase=0.0 Duty=8 diff --git a/base/cores/pll_200_4.vhd b/base/cores/pll_200_4.vhd index 6259145..451db0a 100644 --- a/base/cores/pll_200_4.vhd +++ b/base/cores/pll_200_4.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) --- Module Version: 5.3 ---/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -use_rst -noclkok2 -bw -e +-- VHDL netlist generated by SCUBA Diamond_3.0_Production (94) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/3.0_x64/ispfpga/bin/lin64/scuba -w -n pll_200_4 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 4 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -use_rst -noclkok2 -bw -e --- Tue Oct 7 15:22:29 2014 +-- Fri Jul 3 18:18:12 2015 library IEEE; use IEEE.std_logic_1164.all; @@ -25,6 +25,7 @@ architecture Structure of pll_200_4 is -- internal signal declarations signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -68,7 +69,7 @@ begin port map (Z=>scuba_vlo); PLLInst_0: EHXPLLF - generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", @@ -76,13 +77,13 @@ begin PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOK_DIV=> 2, CLKOP_DIV=> 128, CLKFB_DIV=> 1, CLKI_DIV=> 50, FIN=> "200.000000") - port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>RESET, RSTK=>scuba_vlo, + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>RESET, RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, - CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>open); + CLKOK2=>open, LOCK=>LOCK, CLKINTFB=>CLKFB_t); CLKOP <= CLKOP_t; end Structure;