From: hadaq Date: Fri, 28 Sep 2012 20:46:10 +0000 (+0000) Subject: just a breakpoint X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=60e0db9d73d02625dfbda86796fc260584656fe3;p=trb3.git just a breakpoint --- diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf index 54ea9ae..00f2264 100644 --- a/base/trb3_periph_nxyter.lpf +++ b/base/trb3_periph_nxyter.lpf @@ -89,188 +89,65 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=12; #even numbers are positive LVDS line, odd numbers are negative LVDS line #DQUL can be switched to 1.8V -LOCATE COMP "DQLL_0" SITE "P1"; #DQLL0_0 #1 -LOCATE COMP "DQLL_1" SITE "P2"; #DQLL0_1 #3 -LOCATE COMP "DQLL_2" SITE "T2"; #DQLL0_2 #5 -LOCATE COMP "DQLL_3" SITE "U3"; #DQLL0_3 #7 -LOCATE COMP "DQLL_4" SITE "R1"; #DQLL0_4 #9 -LOCATE COMP "DQLL_5" SITE "R2"; #DQLL0_5 #11 -LOCATE COMP "DQLL_6" SITE "N3"; #DQSLL0_T #13 -LOCATE COMP "DQLL_7" SITE "P3"; #DQSLL0_C #15 -LOCATE COMP "DQLL_8" SITE "P5"; #DQLL0_6 #17 -LOCATE COMP "DQLL_9" SITE "P6"; #DQLL0_7 #19 -LOCATE COMP "DQLL_10" SITE "N5"; #DQLL0_8 #21 -LOCATE COMP "DQLL_11" SITE "N6"; #DQLL0_9 #23 - -LOCATE COMP "DQLL_12" SITE "V1"; #DQLL1_0 #26 -LOCATE COMP "DQLL_13" SITE "U2"; #DQLL1_1 #28 -LOCATE COMP "DQLL_14" SITE "T1"; #DQLL1_2 #30 -LOCATE COMP "DQLL_15" SITE "U1"; #DQLL1_3 #32 -LOCATE COMP "DQLL_16" SITE "P4"; #DQLL1_4 #34 -LOCATE COMP "DQLL_17" SITE "R3"; #DQLL1_5 #36 -LOCATE COMP "DQLL_18" SITE "T3"; #DQSLL1_T #38 -LOCATE COMP "DQLL_19" SITE "R4"; #DQSLL1_C #40 -LOCATE COMP "DQLL_20" SITE "R5"; #DQLL1_6 #42 -LOCATE COMP "DQLL_21" SITE "R6"; #DQLL1_7 #44 -LOCATE COMP "DQLL_22" SITE "T7"; #DQLL1_8 #46 -LOCATE COMP "DQLL_23" SITE "T8"; #DQLL1_9 #48 - -LOCATE COMP "DQLL_24" SITE "AC2"; #DQLL2_0 #25 -LOCATE COMP "DQLL_25" SITE "AC3"; #DQLL2_1 #27 -LOCATE COMP "DQLL_26" SITE "AB1"; #DQLL2_2 #29 -LOCATE COMP "DQLL_27" SITE "AC1"; #DQLL2_3 #31 -LOCATE COMP "DQLL_28" SITE "AA1"; #DQLL2_4 #33 -LOCATE COMP "DQLL_29" SITE "AA2"; #DQLL2_5 #35 -LOCATE COMP "DQLL_30" SITE "W7"; #DQLL2_T #37 #should be DQSLL2 -LOCATE COMP "DQLL_31" SITE "W6"; #DQLL2_C #39 #should be DQSLL2 -LOCATE COMP "DQLL_32" SITE "Y5"; #DQLL2_6 #41 -LOCATE COMP "DQLL_33" SITE "AA5"; #DQLL2_7 #43 -LOCATE COMP "DQLL_34" SITE "V6"; #DQLL2_8 #45 -LOCATE COMP "DQLL_35" SITE "V7"; #DQLL2_9 #47 - -LOCATE COMP "DQLL_36" SITE "AD1"; #DQLL3_0 #2 -LOCATE COMP "DQLL_37" SITE "AD2"; #DQLL3_1 #4 -LOCATE COMP "DQLL_38" SITE "AB5"; #DQLL3_2 #6 -LOCATE COMP "DQLL_39" SITE "AB6"; #DQLL3_3 #8 -LOCATE COMP "DQLL_40" SITE "AB3"; #DQLL3_4 #10 -LOCATE COMP "DQLL_41" SITE "AB4"; #DQLL3_5 #12 -LOCATE COMP "DQLL_42" SITE "Y6"; #DQLL3_T #14 #should be DQSLL3 -LOCATE COMP "DQLL_43" SITE "Y7"; #DQLL3_C #16 #should be DQSLL3 -LOCATE COMP "DQLL_44" SITE "AA3"; #DQLL3_6 #18 -LOCATE COMP "DQLL_45" SITE "AA4"; #DQLL3_7 #20 -LOCATE COMP "DQLL_46" SITE "W8"; #DQLL3_8 #22 -LOCATE COMP "DQLL_47" SITE "W9"; #DQLL3_9 #24 - -LOCATE COMP "DQLR_0" SITE "AC26"; #DQLR0_0 #129 -LOCATE COMP "DQLR_1" SITE "AC25"; #DQLR0_1 #131 -LOCATE COMP "DQLR_2" SITE "Y19"; #DQLR0_2 #133 -LOCATE COMP "DQLR_3" SITE "Y20"; #DQLR0_3 #135 -LOCATE COMP "DQLR_4" SITE "AB24"; #DQLR0_4 #137 -LOCATE COMP "DQLR_5" SITE "AC24"; #DQLR0_5 #139 -LOCATE COMP "DQLR_6" SITE "Y22"; #DQSLR0_T #141 -LOCATE COMP "DQLR_7" SITE "AA22"; #DQSLR0_C #143 -LOCATE COMP "DQLR_8" SITE "AD24"; #DQLR0_6 #145 -LOCATE COMP "DQLR_9" SITE "AE24"; #DQLR0_7 #147 -LOCATE COMP "DQLR_10" SITE "AE25"; #DQLR0_8 #149 -LOCATE COMP "DQLR_11" SITE "AF24"; #DQLR0_9 #151 - -LOCATE COMP "DQLR_12" SITE "W23"; #DQLR1_0 #169 -LOCATE COMP "DQLR_13" SITE "W22"; #DQLR1_1 #171 -LOCATE COMP "DQLR_14" SITE "AA25"; #DQLR1_2 #173 -LOCATE COMP "DQLR_15" SITE "Y24"; #DQLR1_3 #175 -LOCATE COMP "DQLR_16" SITE "AA26"; #DQLR1_4 #177 -LOCATE COMP "DQLR_17" SITE "AB26"; #DQLR1_5 #179 -LOCATE COMP "DQLR_18" SITE "W21"; #DQSLR1_T #181 -LOCATE COMP "DQLR_19" SITE "W20"; #DQSLR1_C #183 -LOCATE COMP "DQLR_20" SITE "AA24"; #DQLR1_6 #185 -LOCATE COMP "DQLR_21" SITE "AA23"; #DQLR1_7 #187 -LOCATE COMP "DQLR_22" SITE "AD26"; #DQLR1_8 #189 -LOCATE COMP "DQLR_23" SITE "AD25"; #DQLR1_9 #191 - -LOCATE COMP "DQLR_24" SITE "R25"; #DQLR2_0 #170 -LOCATE COMP "DQLR_25" SITE "R26"; #DQLR2_1 #172 -LOCATE COMP "DQLR_26" SITE "T25"; #DQLR2_2 #174 -LOCATE COMP "DQLR_27" SITE "T24"; #DQLR2_3 #176 -LOCATE COMP "DQLR_28" SITE "T26"; #DQLR2_4 #178 -LOCATE COMP "DQLR_29" SITE "U26"; #DQLR2_5 #180 -LOCATE COMP "DQLR_30" SITE "V21"; #DQSLR2_T #182 -LOCATE COMP "DQLR_31" SITE "V22"; #DQSLR2_C #184 -LOCATE COMP "DQLR_32" SITE "U24"; #DQLR2_6 #186 -LOCATE COMP "DQLR_33" SITE "V24"; #DQLR2_7 #188 -LOCATE COMP "DQLR_34" SITE "U23"; #DQLR2_8 #190 -LOCATE COMP "DQLR_35" SITE "U22"; #DQLR2_9 #192 - -LOCATE COMP "DQUL_0" SITE "B2"; #DQUL0_0 #74 -LOCATE COMP "DQUL_1" SITE "B3"; #DQUL0_1 #76 -LOCATE COMP "DQUL_2" SITE "D4"; #DQUL0_2 #78 -LOCATE COMP "DQUL_3" SITE "E4"; #DQUL0_3 #80 -LOCATE COMP "DQUL_4" SITE "C3"; #DQUL0_4 #82 -LOCATE COMP "DQUL_5" SITE "D3"; #DQUL0_5 #84 -LOCATE COMP "DQUL_6" SITE "G5"; #DQSUL0_T #86 -LOCATE COMP "DQUL_7" SITE "G6"; #DQSUL0_C #88 -LOCATE COMP "DQUL_8" SITE "E3"; #DQUL0_6 #90 -LOCATE COMP "DQUL_9" SITE "F4"; #DQUL0_7 #92 -LOCATE COMP "DQUL_10" SITE "H6"; #DQUL0_8 #94 -LOCATE COMP "DQUL_11" SITE "J6"; #DQUL0_9 #96 - -LOCATE COMP "DQUL_12" SITE "G2"; #DQUL1_0 #73 -LOCATE COMP "DQUL_13" SITE "G3"; #DQUL1_1 #75 -LOCATE COMP "DQUL_14" SITE "F2"; #DQUL1_2 #77 -LOCATE COMP "DQUL_15" SITE "F3"; #DQUL1_3 #79 -LOCATE COMP "DQUL_16" SITE "C2"; #DQUL1_4 #81 -LOCATE COMP "DQUL_17" SITE "D2"; #DQUL1_5 #83 -LOCATE COMP "DQUL_18" SITE "K7"; #DQSUL1_T #85 -LOCATE COMP "DQUL_19" SITE "K6"; #DQSUL1_C #87 -LOCATE COMP "DQUL_20" SITE "H5"; #DQUL1_6 #89 -LOCATE COMP "DQUL_21" SITE "J5"; #DQUL1_7 #91 -LOCATE COMP "DQUL_22" SITE "K8"; #DQUL1_8 #93 -LOCATE COMP "DQUL_23" SITE "J7"; #DQUL1_9 #95 - -LOCATE COMP "DQUL_24" SITE "K2"; #DQUL2_0 #50 -LOCATE COMP "DQUL_25" SITE "K1"; #DQUL2_1 #52 -LOCATE COMP "DQUL_26" SITE "J4"; #DQUL2_2 #54 -LOCATE COMP "DQUL_27" SITE "J3"; #DQUL2_3 #56 -LOCATE COMP "DQUL_28" SITE "D1"; #DQUL2_4 #58 -LOCATE COMP "DQUL_29" SITE "C1"; #DQUL2_5 #60 -LOCATE COMP "DQUL_30" SITE "K4"; #DQSUL2_T #62 -LOCATE COMP "DQUL_31" SITE "K5"; #DQSUL2_C #64 -LOCATE COMP "DQUL_32" SITE "E1"; #DQUL2_6 #66 -LOCATE COMP "DQUL_33" SITE "F1"; #DQUL2_7 #68 -LOCATE COMP "DQUL_34" SITE "L5"; #DQUL2_8 #70 -LOCATE COMP "DQUL_35" SITE "L6"; #DQUL2_9 #72 - -LOCATE COMP "DQUL_36" SITE "H2"; #DQUL3_0 #49 -LOCATE COMP "DQUL_37" SITE "G1"; #DQUL3_1 #51 -LOCATE COMP "DQUL_38" SITE "K3"; #DQUL3_2 #53 -LOCATE COMP "DQUL_39" SITE "L3"; #DQUL3_3 #55 -LOCATE COMP "DQUL_40" SITE "H1"; #DQUL3_4 #57 -LOCATE COMP "DQUL_41" SITE "J1"; #DQUL3_5 #59 -LOCATE COMP "DQUL_42" SITE "M5"; #DQSUL3_T #61 -LOCATE COMP "DQUL_43" SITE "M6"; #DQSUL3_C #63 -LOCATE COMP "DQUL_44" SITE "L2"; #DQUL3_6 #65 -LOCATE COMP "DQUL_45" SITE "L1"; #DQUL3_7 #67 - - -LOCATE COMP "DQUR_0" SITE "J23"; #DQUR0_0 #105 -LOCATE COMP "DQUR_1" SITE "H23"; #DQUR0_1 #107 -LOCATE COMP "DQUR_2" SITE "G26"; #DQUR0_2 #109 -LOCATE COMP "DQUR_3" SITE "F26"; #DQUR0_3 #111 -LOCATE COMP "DQUR_4" SITE "F24"; #DQSUR0_T #113 -LOCATE COMP "DQUR_5" SITE "G24"; #DQSUR0_C #115 -LOCATE COMP "DQUR_6" SITE "H26"; #DQUR0_4 #117 -LOCATE COMP "DQUR_7" SITE "H25"; #DQUR0_5 #119 -LOCATE COMP "DQUR_8" SITE "K23"; #DQUR0_6 #121 -LOCATE COMP "DQUR_9" SITE "K22"; #DQUR0_7 #123 -# LOCATE COMP "DQUR_10" SITE "F25"; #DQUR0_8 #125 #input only -# LOCATE COMP "DQUR_11" SITE "E26"; #DQUR0_9 #127 #input only - -LOCATE COMP "DQUR_10" SITE "H24"; #DQUR1_0 #106 -LOCATE COMP "DQUR_11" SITE "G25"; #DQUR1_1 #108 -LOCATE COMP "DQUR_12" SITE "L20"; #DQUR1_2 #110 -LOCATE COMP "DQUR_13" SITE "M21"; #DQUR1_3 #112 -LOCATE COMP "DQUR_14" SITE "K24"; #DQUR1_4 #114 -LOCATE COMP "DQUR_15" SITE "J24"; #DQUR1_5 #116 -LOCATE COMP "DQUR_16" SITE "M23"; #DQSUR1_T #118 -LOCATE COMP "DQUR_17" SITE "M24"; #DQSUR1_C #120 -LOCATE COMP "DQUR_18" SITE "L24"; #DQUR1_6 #122 -LOCATE COMP "DQUR_19" SITE "K25"; #DQUR1_7 #124 -LOCATE COMP "DQUR_20" SITE "M22"; #DQUR1_8 #126 -LOCATE COMP "DQUR_21" SITE "N21"; #DQUR1_9 #128 -LOCATE COMP "DQUR_22" SITE "J26"; #DQUR2_0 #130 -LOCATE COMP "DQUR_23" SITE "K26"; #DQUR2_1 #132 -LOCATE COMP "DQUR_24" SITE "N23"; #DQUR2_2 #134 -LOCATE COMP "DQUR_25" SITE "N22"; #DQUR2_3 #136 -LOCATE COMP "DQUR_26" SITE "K19"; #DQUR2_4 #138 -LOCATE COMP "DQUR_27" SITE "L19"; #DQUR2_5 #140 -LOCATE COMP "DQUR_28" SITE "P23"; #DQSUR2_T #142 -LOCATE COMP "DQUR_29" SITE "R22"; #DQSUR2_C #144 -LOCATE COMP "DQUR_30" SITE "L25"; #DQUR2_6 #146 -LOCATE COMP "DQUR_31" SITE "L26"; #DQUR2_7 #148 -LOCATE COMP "DQUR_32" SITE "P21"; #DQUR2_8 #150 -LOCATE COMP "DQUR_33" SITE "P22"; #DQUR2_9 #152 - -DEFINE PORT GROUP "DQ_group" "DQ*" ; -IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; +# nXyter + +LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34 +LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36 +LOCATE COMP "NX1_I2C_SDA_INOUT" SITE "R5"; #DQLL1_6 #42 +LOCATE COMP "NX1_I2C_SCL_OUT" SITE "R6"; #DQLL1_7 #44 +LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46 +LOCATE COMP "NX1_CLK256A_OUT" SITE "AB1"; #DQLL2_2 #29 +LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45 + +LOCATE COMP "NX1_ADC_D_IN" SITE "B2"; #DQUL0_0 #74 +LOCATE COMP "NX1_ADC_A_IN" SITE "D4"; #DQUL0_2 #78 +LOCATE COMP "NX1_ADC_NX_IN" SITE "C3"; #DQUL0_4 #82 +LOCATE COMP "NX1_ADC_DCLK_IN" SITE "G5"; #DQSUL0_T #86 +LOCATE COMP "NX1_ADC_B_IN" SITE "E3"; #DQUL0_6 #90 +LOCATE COMP "NX1_ADC_FCLK_IN" SITE "H6"; #DQUL0_8 #94 + + +LOCATE COMP "NX1_SPI_SDIO_INOUT" SITE "G2"; #DQUL1_0 #73 +LOCATE COMP "NX1_SPI_SCLK_OUT" SITE "F2"; #DQUL1_2 #77 +LOCATE COMP "NX1_SPI_CSB_OUT" SITE "C2"; #DQUL1_4 #81 +LOCATE COMP "NX1_ADC_SC_CLK32_OUT" SITE "H5"; #DQUL1_6 #89 + +LOCATE COMP "NX1_TIMESTAMP_IN_0" SITE "K2"; #DQUL2_0 #50 +LOCATE COMP "NX1_TIMESTAMP_IN_1" SITE "J4"; #DQUL2_2 #54 +LOCATE COMP "NX1_TIMESTAMP_IN_2" SITE "D1"; #DQUL2_4 #58 +#LOCATE COMP "NX1_CLK128_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE +LOCATE COMP "NX1_TIMESTAMP_IN_3" SITE "E1"; #DQUL2_6 #66 +LOCATE COMP "NX1_TIMESTAMP_IN_4" SITE "L5"; #DQUL2_8 #70 + +LOCATE COMP "NX1_TIMESTAMP_IN_5" SITE "H2"; #DQUL3_0 #49 +LOCATE COMP "NX1_TIMESTAMP_IN_6" SITE "K3"; #DQUL3_2 #53 +LOCATE COMP "NX1_TIMESTAMP_IN_7" SITE "H1"; #DQUL3_4 #57 + + +DEFINE PORT GROUP "LVDS_group1" "NX1_TIMESTAMP_IN_*" ; +IOBUF GROUP "LVDS_group1" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +DEFINE PORT GROUP "LVDS_group2" "NX1_ADC_*_IN" ; +IOBUF GROUP "LVDS_group2" IO_TYPE=LVDS25 DIFFRESISTOR=100; + +IOBUF PORT "NX1_ADC_SC_CLK32_OUT" IO_TYPE=IO_TYPE=LVDS25; + +IOBUF PORT "NX1_CLK128_IN" IO_TYPE=IO_TYPE=LVDS25 DIFFRESISTOR=100; + +IOBUF PORT "NX1_TESTPULSE_OUT" IO_TYPE=IO_TYPE=LVDS25; +IOBUF PORT "NX1_CLK256A_OUT" IO_TYPE=IO_TYPE=LVDS25; +IOBUF PORT "NX1_RESET_OUT" IO_TYPE=IO_TYPE=LVDS25; + +IOBUF PORT "NX1_I2C_SM_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "NX1_I2C_REG_RESET_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "NX1_I2C_SDA_INOUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "NX1_I2C_SCL_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; + +IOBUF PORT "NX1_SPI_SDIO_INOUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "NX1_SPI_SCLK_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; +IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=NONE; + + ################################################################# # Additional Lines to AddOn @@ -279,12 +156,12 @@ IOBUF GROUP "DQ_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; #Lines 0/1 are terminated with 100 Ohm, pads available on 0-3 #all lines are input only #line 4/5 go to PLL input -LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 -LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 -LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 -LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 -LOCATE COMP "SPARE_LINE_4" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -LOCATE COMP "SPARE_LINE_5" SITE "M2"; #DQUL3_9_OUTOFLANE_FPGA__3 #71 +#LOCATE COMP "SPARE_LINE_0" SITE "M25"; #194 +#LOCATE COMP "SPARE_LINE_1" SITE "M26"; #196 +#LOCATE COMP "SPARE_LINE_2" SITE "W4"; #198 +#LOCATE COMP "SPARE_LINE_3" SITE "W5"; #200 +LOCATE COMP "NX1_CLK128_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 + ################################################################# # Flash ROM and Reboot diff --git a/nxyter/compile_munich.pl b/nxyter/compile_munich.pl index 9bcb4d2..0be68b6 100755 --- a/nxyter/compile_munich.pl +++ b/nxyter/compile_munich.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond'; +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/new'; my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index 6d239da..e6d7022 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -13,8 +13,8 @@ use work.adcmv3_components.all; entity nXyter_FEE_board is port ( - CLK_IN : in std_logic_vector; - RESET_IN : in std_logic_vector; + CLK_IN : in std_logic; + RESET_IN : in std_logic; -- I2C Ports I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line @@ -29,7 +29,7 @@ entity nXyter_FEE_board is -- nXyter Timestamp Ports NX_CLK128_IN : in std_logic; - NX_IN : in std_logic_vector (7 downto 0); + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_RESET_OUT : out std_logic; NX_CLK256A_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 1e884bc..0c40310 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -10,8 +10,8 @@ package nxyter_components is component nXyter_FEE_board port ( - CLK_IN : in std_logic_vector; - RESET_IN : in std_logic_vector; + CLK_IN : in std_logic; + RESET_IN : in std_logic; I2C_SDA_INOUT : inout std_logic; I2C_SCL_OUT : out std_logic; @@ -23,7 +23,7 @@ component nXyter_FEE_board SPI_CSB_OUT : out std_logic; NX_CLK128_IN : in std_logic; - NX_IN : in std_logic_vector (7 downto 0); + NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_RESET_OUT : out std_logic; NX_CLK256A_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; diff --git a/nxyter/source/slave_bus.vhd b/nxyter/source/slave_bus.vhd index 2925802..1ff5db4 100755 --- a/nxyter/source/slave_bus.vhd +++ b/nxyter/source/slave_bus.vhd @@ -71,7 +71,7 @@ architecture Behavioral of slave_bus is signal onewire_debug : std_logic_vector(63 downto 0); -- do not know at the moment, have no backplanes, needed by Slave-Bus - signal bp_module_qq : std_logic_vector(3 downto 0); + signal bp_module_qq : std_logic_vector(2 downto 0); -- Pedestal and threshold stuff type reg_18bit_t is array (0 to 15) of std_logic_vector(17 downto 0); @@ -139,6 +139,7 @@ begin DAT_WRITE_ACK_OUT => REGIO_WRITE_ACK_OUT, DAT_NO_MORE_DATA_OUT => REGIO_NO_MORE_DATA_OUT, DAT_UNKNOWN_ADDR_OUT => REGIO_UNKNOWN_ADDR_OUT, + -- pedestal memories BUS_READ_ENABLE_OUT(0) => slv_read(0), BUS_WRITE_ENABLE_OUT(0) => slv_write(0), @@ -150,6 +151,7 @@ begin BUS_WRITE_ACK_IN(0) => slv_ack(0), BUS_NO_MORE_DATA_IN(0) => slv_busy(0), BUS_UNKNOWN_ADDR_IN(0) => '0', + -- threshold memories BUS_READ_ENABLE_OUT(1) => slv_read(1), BUS_WRITE_ENABLE_OUT(1) => slv_write(1), @@ -161,6 +163,7 @@ begin BUS_WRITE_ACK_IN(1) => slv_ack(1), BUS_NO_MORE_DATA_IN(1) => slv_busy(1), BUS_UNKNOWN_ADDR_IN(1) => '0', + -- I2C master BUS_READ_ENABLE_OUT(2) => slv_read(2), BUS_WRITE_ENABLE_OUT(2) => slv_write(2), diff --git a/nxyter/todo.txt b/nxyter/todo.txt index 5948721..dba365c 100644 --- a/nxyter/todo.txt +++ b/nxyter/todo.txt @@ -7,5 +7,5 @@ - change ../base/trb3_periph_nxyter.lpf to the pin names used for the nxyter addon (starting from line 92), remove all DQ* signals - add the signal names for the nxyter addon in the entity declaration of the top-level trb3_periph.vhd -- add your vhdl files to trb3_periph_prj +- add your vhdl files to trb3_periph.prj - Edit trb3_periph_constraints.lpf to contain the correct names of clock nets & pins - see the two comments in the second block. diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index efb7ee4..0a93884 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -147,7 +147,7 @@ add_file -vhdl -lib "work" "./source/nxyter_components.vhd" add_file -vhdl -lib "work" "./source/nxyter.vhd" add_file -vhdl -lib "work" "./source/slave_bus.vhd" -add_file -vhdl -lib "work" "./source/slv_ped_thr_mem.vhd" +#add_file -vhdl -lib "work" "./source/slv_ped_thr_mem.vhd" add_file -vhdl -lib "work" "./source/slv_register.vhd" #add_file -vhdl -lib "work" "./source/gray_decoder.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 6970201..9aec957 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -31,14 +31,11 @@ entity trb3_periph is FPGA5_COMM : inout std_logic_vector(11 downto 0); --Bit 0/1 input, serial link RX active --Bit 2/3 output, serial link TX active - - - --------------------------------------------------------------------------- -- BEGIN AddonBoard nXyter --------------------------------------------------------------------------- - --Connections to NXYTER-FEB + --Connections to NXYTER-FEB 1 NX1_RESET_OUT : out std_logic; NX1_I2C_SDA_INOUT : inout std_logic; @@ -49,8 +46,7 @@ entity trb3_periph is NX1_SPI_SDIO_INOUT : in std_logic; NX1_SPI_CSB_OUT : out std_logic; NX1_CLK128_IN : in std_logic; - NX1_IN : in std_logic_vector (7 downto 0); - NX1_RESET_OUT : out std_logic; + NX1_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX1_CLK256A_OUT : out std_logic; NX1_TESTPULSE_OUT : out std_logic; NX1_ADC_FCLK_IN : in std_logic; @@ -60,6 +56,29 @@ entity trb3_periph is NX1_ADC_B_IN : in std_logic; NX1_ADC_NX_IN : in std_logic; NX1_ADC_D_IN : in std_logic; + + --Connections to NXYTER-FEB 2 + + NX2_RESET_OUT : out std_logic; + NX2_I2C_SDA_INOUT : inout std_logic; + NX2_I2C_SCL_OUT : out std_logic; + NX2_I2C_SM_RESET_OUT : out std_logic; + NX2_I2C_REG_RESET_OUT : out std_logic; + NX2_SPI_SCLK_OUT : out std_logic; + NX2_SPI_SDIO_INOUT : in std_logic; + NX2_SPI_CSB_OUT : out std_logic; + NX2_CLK128_IN : in std_logic; + NX2_IN : in std_logic_vector (7 downto 0); + NX2_CLK256A_OUT : out std_logic; + NX2_TESTPULSE_OUT : out std_logic; + NX2_ADC_FCLK_IN : in std_logic; + NX2_ADC_DCLK_IN : in std_logic; + NX2_ADC_SC_CLK32_OUT : out std_logic; + NX2_ADC_A_IN : in std_logic; + NX2_ADC_B_IN : in std_logic; + NX2_ADC_NX_IN : in std_logic; + NX2_ADC_D_IN : in std_logic; + --------------------------------------------------------------------------- -- END AddonBoard nXyter @@ -83,6 +102,7 @@ entity trb3_periph is --Test Connectors TEST_LINE : out std_logic_vector(15 downto 0) ); + attribute syn_useioff : boolean; --no IO-FF for LEDs relaxes timing constraints attribute syn_useioff of LED_GREEN : signal is false; @@ -101,12 +121,12 @@ entity trb3_periph is attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_useioff of TEST_LINE : signal is true; - attribute syn_useioff of INP : signal is false; - attribute syn_useioff of SPARE_LINE : signal is true; - attribute syn_useioff of DAC_SDO : signal is true; - attribute syn_useioff of DAC_SDI : signal is true; - attribute syn_useioff of DAC_SCK : signal is true; - attribute syn_useioff of DAC_CS : signal is true; + --attribute syn_useioff of INP : signal is false; + --attribute syn_useioff of SPARE_LINE : signal is true; + --attribute syn_useioff of DAC_SDO : signal is true; + --attribute syn_useioff of DAC_SDI : signal is true; + --attribute syn_useioff of DAC_SCK : signal is true; + --attribute syn_useioff of DAC_CS : signal is true; end entity; @@ -232,8 +252,29 @@ architecture trb3_periph_arch of trb3_periph is signal time_counter : unsigned(31 downto 0); - -- nXyter - + -- nXyter 1 Regio Bus + signal nx1_regio_addr_in : std_logic_vector (15 downto 0); + signal nx1_regio_data_in : std_logic_vector (31 downto 0); + signal nx1_regio_data_out : std_logic_vector (31 downto 0); + signal nx1_regio_read_enable_in : std_logic; + signal nx1_regio_write_enable_in : std_logic; + signal nx1_regio_timeout_in : std_logic; + signal nx1_regio_dataready_out : std_logic; + signal nx1_regio_write_ack_out : std_logic; + signal nx1_regio_no_more_data_out : std_logic; + signal nx1_regio_unknown_addr_out : std_logic; + + -- nXyter 1 Regio Bus + signal nx2_regio_addr_in : std_logic_vector (15 downto 0); + signal nx2_regio_data_in : std_logic_vector (31 downto 0); + signal nx2_regio_data_out : std_logic_vector (31 downto 0); + signal nx2_regio_read_enable_in : std_logic; + signal nx2_regio_write_enable_in : std_logic; + signal nx2_regio_timeout_in : std_logic; + signal nx2_regio_dataready_out : std_logic; + signal nx2_regio_write_ack_out : std_logic; + signal nx2_regio_no_more_data_out : std_logic; + signal nx2_regio_unknown_addr_out : std_logic; begin --------------------------------------------------------------------------- @@ -439,12 +480,16 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, + PORT_NUMBER => 4, PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", + 2 => x"8000", + 3 => x"9000", others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, + 2 => 15, + 3 => 15, others => 0) ) port map( @@ -474,6 +519,7 @@ begin BUS_WRITE_ACK_IN(0) => spictrl_ack, BUS_NO_MORE_DATA_IN(0) => spictrl_busy, BUS_UNKNOWN_ADDR_IN(0) => '0', + --Bus Handler (SPI Memory) BUS_READ_ENABLE_OUT(1) => spimem_read_en, BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, @@ -487,12 +533,29 @@ begin BUS_NO_MORE_DATA_IN(1) => '0', BUS_UNKNOWN_ADDR_IN(1) => '0', - ------------------------------------------------------------------------- - -- Hier meine register..... - -- Macht aber das nxyter entity - ------------------------------------------------------------------------- - - + --Bus Handler (nXyter1 trb_net16_regio_bus_handler) + BUS_READ_ENABLE_OUT(2) => nx1_regio_read_enable_in, + BUS_WRITE_ENABLE_OUT(2) => nx1_regio_write_enable_in, + BUS_DATA_OUT(2*32+31 downto 2*32) => nx1_regio_data_in, + BUS_ADDR_OUT(2*16+15 downto 2*16) => nx1_regio_addr_in, + BUS_TIMEOUT_OUT(2) => nx1_regio_timeout_in, + BUS_DATA_IN(2*32+31 downto 2*32) => nx1_regio_data_out, + BUS_DATAREADY_IN(2) => nx1_regio_dataready_out, + BUS_WRITE_ACK_IN(2) => nx1_regio_write_ack_out, + BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out, + BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out, + + --Bus Handler (nXyter2 trb_net16_regio_bus_handler) + BUS_READ_ENABLE_OUT(3) => nx2_regio_read_enable_in, + BUS_WRITE_ENABLE_OUT(3) => nx2_regio_write_enable_in, + BUS_DATA_OUT(3*32+31 downto 3*32) => nx2_regio_data_in, + BUS_ADDR_OUT(3*16+15 downto 3*16) => nx2_regio_addr_in, + BUS_TIMEOUT_OUT(3) => nx2_regio_timeout_in, + BUS_DATA_IN(3*32+31 downto 3*32) => nx2_regio_data_out, + BUS_DATAREADY_IN(3) => nx2_regio_dataready_out, + BUS_WRITE_ACK_IN(3) => nx2_regio_write_ack_out, + BUS_NO_MORE_DATA_IN(3) => nx2_regio_no_more_data_out, + BUS_UNKNOWN_ADDR_IN(3) => nx2_regio_unknown_addr_out, STAT_DEBUG => open ); @@ -589,7 +652,7 @@ begin SPI_CSB_OUT => NX1_SPI_CSB_OUT, NX_CLK128_IN => NX1_CLK128_IN, - NX_IN => NX1_IN, + NX_TIMESTAMP_IN => NX1_TIMESTAMP_IN, NX_RESET_OUT => NX1_RESET_OUT, NX_CLK256A_OUT => NX1_CLK256A_OUT, NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, @@ -602,16 +665,16 @@ begin ADC_NX_IN => NX1_ADC_NX_IN, ADC_D_IN => NX1_ADC_D_IN, - REGIO_ADDR_IN => regio_addr_out, - REGIO_DATA_IN => regio_data_out, - REGIO_DATA_OUT => regio_data_in, - REGIO_READ_ENABLE_IN => regio_read_enable_out, - REGIO_WRITE_ENABLE_IN => regio_write_enable_out, - REGIO_TIMEOUT_IN => regio_timeout_out, - REGIO_DATAREADY_OUT => regio_dataready_in, - REGIO_WRITE_ACK_OUT => regio_write_ack_in, - REGIO_NO_MORE_DATA_OUT => regio_no_more_data_in, - REGIO_UNKNOWN_ADDR_OUT => regio_unknown_addr_in + REGIO_ADDR_IN => nx1_regio_addr_in, + REGIO_DATA_IN => nx1_regio_data_in, + REGIO_DATA_OUT => nx1_regio_data_out, + REGIO_READ_ENABLE_IN => nx1_regio_read_enable_in, + REGIO_WRITE_ENABLE_IN => nx1_regio_write_enable_in, + REGIO_TIMEOUT_IN => nx1_regio_timeout_in, + REGIO_DATAREADY_OUT => nx1_regio_dataready_out, + REGIO_WRITE_ACK_OUT => nx1_regio_write_ack_out, + REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out, + REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out ); --------------------------------------------------------------------------- diff --git a/nxyter/wichtigedateien.txt b/nxyter/wichtigedateien.txt new file mode 100644 index 0000000..abcc791 --- /dev/null +++ b/nxyter/wichtigedateien.txt @@ -0,0 +1,7 @@ +Zum debuggen: see workdir/* +.srr +.mrp +.par +.twr.setup + +dateien