From: Thomas Gessler Date: Mon, 24 Aug 2020 13:52:06 +0000 (+0200) Subject: Change settings for Xilinx CDC FIFO X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6226b19ad4fe2cf3a21ac9d3c7c721d6291ed0a4;p=trbnet.git Change settings for Xilinx CDC FIFO Add safety circuit and change the full-flag reset value. These settings were found to prevent slow control-related crashes. --- diff --git a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci index a52feb1..ed2915a 100644 --- a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci +++ b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xci @@ -165,7 +165,7 @@ 18 0 1 - 0 + 1 0 0 0 @@ -174,7 +174,7 @@ 0 0 kintexu - 1 + 0 0 0 1 @@ -369,7 +369,7 @@ false false true - false + true false true Data_FIFO @@ -385,7 +385,7 @@ Common_Clock_Block_RAM Common_Clock_Block_RAM Independent_Clocks_Block_RAM - 1 + 0 7 1023 1023 diff --git a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml index d713376..9cfac03 100644 --- a/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml +++ b/xilinx/xcku/fifo_18x16_dualport_oreg_xcku/fifo_18x16_dualport_oreg_xcku.xml @@ -3134,7 +3134,7 @@ - false + true @@ -3156,7 +3156,7 @@ - false + true @@ -7839,7 +7839,7 @@ C_FULL_FLAGS_RST_VAL - 1 + 0 C_HAS_ALMOST_EMPTY @@ -8051,7 +8051,7 @@ C_EN_SAFETY_CKT - 0 + 1 C_ERROR_INJECTION_TYPE @@ -8958,7 +8958,7 @@ Full_Flags_Reset_Value - 1 + 0 @@ -10655,7 +10655,7 @@ Enable_Safety_Circuit - false + true