From: hadeshyp <hadeshyp>
Date: Fri, 16 Oct 2009 15:43:34 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~363
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6260c386bdc116146999d657a83a12074db8b932;p=trbnet.git

*** empty log message ***
---

diff --git a/lattice/ecp2m/ddr_off.lpc b/lattice/ecp2m/ddr_off.lpc
new file mode 100644
index 0000000..7bc17e9
--- /dev/null
+++ b/lattice/ecp2m/ddr_off.lpc
@@ -0,0 +1,47 @@
+[Device]
+Family=latticeecp2m
+PartType=LFE2M20E
+PartName=LFE2M20E-5F256C
+SpeedGrade=-5
+Package=FPBGA256
+OperatingCondition=COM
+Status=P
+
+[IP]
+VendorName=Lattice Semiconductor Corporation
+CoreType=LPM
+CoreStatus=Demo
+CoreName=DDR_GENERIC
+CoreRevision=4.0
+ModuleName=ddr_off
+SourceFormat=Schematic/VHDL
+ParameterFileVersion=1.0
+Date=07/06/2009
+Time=17:16:30
+
+[Parameters]
+Verilog=0
+VHDL=1
+EDIF=1
+Destination=Synplicity
+Expression=BusA(0 to 7)
+Order=Big Endian [MSB:LSB]
+IO=0
+mode=Output
+width=1
+reg=DDR
+gear=1x
+rst=Edge
+del=Dynamic
+cdel=0
+fdel=0
+cdiv=1
+clk1x=0
+clk2x=0
+ail=0
+step=2
+ckedge=1
+swap=Off
+bf=Off
+AilAW=400
+val=0
diff --git a/lattice/ecp2m/ddr_off.vhd b/lattice/ecp2m/ddr_off.vhd
new file mode 100644
index 0000000..2c3733b
--- /dev/null
+++ b/lattice/ecp2m/ddr_off.vhd
@@ -0,0 +1,67 @@
+-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23)
+-- Module  Version: 4.0
+--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n ddr_off -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type iol -mode out -width 1 -gear 1 -e 
+
+-- Mon Jul  6 17:16:30 2009
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+-- synopsys translate_off
+library ecp2m;
+use ecp2m.components.all;
+-- synopsys translate_on
+
+entity ddr_off is
+    port (
+        Clk: in  std_logic; 
+        Data: in  std_logic_vector(1 downto 0); 
+        Q: out  std_logic_vector(0 downto 0));
+ attribute dont_touch : string;
+ attribute dont_touch of ddr_off : entity is "true";
+end ddr_off;
+
+architecture Structure of ddr_off is
+
+    -- internal signal declarations
+    signal scuba_vlo: std_logic;
+    signal buf_Q0: std_logic;
+
+    -- local component declarations
+    component VLO
+        port (Z: out  std_logic);
+    end component;
+    component OB
+        port (I: in  std_logic; O: out  std_logic);
+    end component;
+    component ODDRXC
+        port (DA: in  std_logic; DB: in  std_logic; CLK: in  std_logic; 
+            RST: in  std_logic; Q: out  std_logic);
+    end component;
+    attribute syn_noprune : boolean;
+    attribute syn_noprune of Structure : architecture is true;
+
+begin
+    -- component instantiation statements
+    scuba_vlo_inst: VLO
+        port map (Z=>scuba_vlo);
+
+    ud_0: ODDRXC
+        port map (DA=>Data(0), DB=>Data(1), CLK=>Clk, RST=>scuba_vlo, 
+            Q=>buf_Q0);
+
+    buf_Q0_out_inst: OB
+        port map (I=>buf_Q0, O=>Q(0));
+
+end Structure;
+
+-- synopsys translate_off
+library ecp2m;
+configuration Structure_CON of ddr_off is
+    for Structure
+        for all:VLO use entity ecp2m.VLO(V); end for;
+        for all:OB use entity ecp2m.OB(V); end for;
+        for all:ODDRXC use entity ecp2m.ODDRXC(V); end for;
+    end for;
+end Structure_CON;
+
+-- synopsys translate_on