From: hadeshyp <hadeshyp>
Date: Thu, 21 Jun 2012 21:07:18 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~59
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=629eb0b60370cf58a0b95f91fda05f18bb073098;p=trbnet.git

*** empty log message ***
---

diff --git a/gbe2_ecp3/ipcores_ecp3/msg_file.log b/gbe2_ecp3/ipcores_ecp3/msg_file.log
index 1f9753d..0fba5db 100755
--- a/gbe2_ecp3/ipcores_ecp3/msg_file.log
+++ b/gbe2_ecp3/ipcores_ecp3/msg_file.log
@@ -1,5 +1,5 @@
-SCUBA, Version Diamond_1.3_Production (92)
-Mon Dec  5 22:40:38 2011
+SCUBA, Version Diamond_1.4_Production (87)
+Sat May 19 15:06:38 2012
   
 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
 Copyright (c) 1995 AT&T Corp.   All rights reserved.
@@ -9,23 +9,25 @@ Copyright (c) 2002-2011 Lattice Semiconductor Corporation,  All rights reserved.
   
 BEGIN SCUBA Module Synthesis
   
-    Issued command   : /opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -n statts_mem -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -device LFE3-150EA -type ramdps -raddr_width 10 -rwidth 8 -waddr_width 8 -wwidth 32 -rnum_words 1020 -wnum_words 255 -cascade -1 -e 
-    Circuit name     : statts_mem
-    Module type      : RAM_DP
-    Module Version   : 6.1
+    Issued command   : /opt/lattice/diamond/1.4/ispfpga/bin/lin/scuba -w -n fifo_65536x18x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 15 -data_width 18 -num_words 32768 -rdata_width 9 -no_enable -pe -1 -pf -1 -e 
+    Circuit name     : fifo_65536x18x9
+    Module type      : ebfifo
+    Module Version   : 5.4
     Ports            : 
-    Inputs       : WrAddress[7:0], RdAddress[9:0], Data[31:0], WE, RdClock, RdClockEn, Reset, WrClock, WrClockEn
-    Outputs      : Q[7:0]
+    Inputs       : Data[17:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset
+    Outputs      : Q[8:0], Empty, Full
     I/O buffer       : not inserted
     EDIF output      : suppressed
-    VHDL output      : statts_mem.vhd
-    VHDL template    : statts_mem_tmpl.vhd
-    VHDL testbench   : tb_statts_mem_tmpl.vhd
+    VHDL output      : fifo_65536x18x9.vhd
+    VHDL template    : fifo_65536x18x9_tmpl.vhd
+    VHDL testbench   : tb_fifo_65536x18x9_tmpl.vhd
     VHDL purpose     : for synthesis and simulation
     Bus notation     : big endian
-    Report output    : statts_mem.srp
+    Report output    : fifo_65536x18x9.srp
     Estimated Resource Usage:
-            EBR : 1
+            LUT : 367
+            EBR : 32
+            Reg : 172
   
 END   SCUBA Module Synthesis