From: hadeshyp Date: Wed, 19 Oct 2011 16:16:15 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=62ae0ca4da040eba9aa57880112ff3cd59e15a0b;p=trb3.git *** empty log message *** --- diff --git a/base/trb3_central.lpf b/base/trb3_central.lpf index 2e34a50..b1bbcbb 100644 --- a/base/trb3_central.lpf +++ b/base/trb3_central.lpf @@ -6,7 +6,7 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 20; + SYSCONFIG MCCLK_FREQ = 2.5; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; @@ -292,8 +292,8 @@ IOBUF PORT "ADDON_TO_TRB_CLK" IO_TYPE=LVDS25 ; LOCATE COMP "TRB_TO_ADDON_CLK" SITE "K16"; IOBUF PORT "TRB_TO_ADDON_CLK" IO_TYPE=LVCMOS25 ; -LOCATE COMP "TRB_TO_ADDON_CLKb" SITE "L16"; -IOBUF PORT "TRB_TO_ADDON_CLKb" IO_TYPE=LVCMOS25 ; + + LOCATE COMP "ADO_LV_0" SITE "D5"; diff --git a/base/trb3_central.p2t b/base/trb3_central.p2t index c037b03..995161f 100644 --- a/base/trb3_central.p2t +++ b/base/trb3_central.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 12 +-t 11 -c 1 -e 2 -m nodelist.txt diff --git a/base/trb3_central.prj b/base/trb3_central.prj index 61c4b04..e69c731 100644 --- a/base/trb3_central.prj +++ b/base/trb3_central.prj @@ -112,13 +112,16 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full_125.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../base/cores/pll_in125_out125.vhd" add_file -vhdl -lib work "./trb3_central.vhd" diff --git a/base/trb3_central.vhd b/base/trb3_central.vhd index 6359c1d..c805a77 100644 --- a/base/trb3_central.vhd +++ b/base/trb3_central.vhd @@ -12,6 +12,9 @@ use work.version.all; entity trb3_central is + generic( + FREQUENCY : integer range 125 to 200 := 200 + ); port( --Clocks CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45 @@ -81,7 +84,7 @@ entity trb3_central is --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; - FLASH_CIN : out std_logic; + FLASH_DIN : out std_logic; FLASH_DOUT : in std_logic; PROGRAMN : out std_logic := '1'; --reboot FPGA @@ -120,7 +123,7 @@ entity trb3_central is --important signals _with_ IO-FF attribute syn_useioff of FLASH_CLK : signal is true; attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_CIN : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA1_COMM : signal is true; attribute syn_useioff of FPGA2_COMM : signal is true; @@ -137,15 +140,14 @@ architecture trb3_central_arch of trb3_central is signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL signal pll_lock : std_logic; --Internal PLL locked. E.g. used to reset all internal logic. + signal clk_serdes : std_logic; --wrapper for serdes clock + signal clk_system : std_logic; --wrapper for system clock signal clear_i : std_logic; signal reset_i : std_logic; signal GSR_N : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; - --FPGA Test - signal time_counter : unsigned(31 downto 0); - --Media Interface signal med_stat_op : std_logic_vector (5*16-1 downto 0); signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); @@ -193,6 +195,7 @@ architecture trb3_central_arch of trb3_central is signal spi_bram_wr_d : std_logic_vector(7 downto 0); signal spi_bram_rd_d : std_logic_vector(7 downto 0); signal spi_bram_we : std_logic; + signal spi_debug : std_logic_vector(31 downto 0); begin @@ -210,8 +213,8 @@ THE_RESET_HANDLER : trb_net_reset_handler port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock + CLK_IN => clk_serdes, -- raw master clock, NOT from PLL/DLL! + SYSCLK_IN => clk_system, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) TRB_RESET_IN => med_stat_op(4*16+13), -- TRBnet reset signal (SYSCLK) @@ -223,14 +226,29 @@ THE_RESET_HANDLER : trb_net_reset_handler --------------------------------------------------------------------------- -- Clock Handling --------------------------------------------------------------------------- -THE_MAIN_PLL : pll_in200_out100 - port map( - CLK => CLK_GPLL_LEFT, - CLKOP => clk_100_i, - CLKOK => clk_200_i, - LOCK => pll_lock - ); - +gen_200_CLK : if FREQUENCY = 200 generate + THE_MAIN_PLL : pll_in200_out100 + port map( + CLK => CLK_GPLL_LEFT, + CLKOP => clk_100_i, + CLKOK => clk_200_i, + LOCK => pll_lock + ); + clk_serdes <= clk_200_i; + clk_system <= clk_100_i; +end generate; + +gen_125_CLK : if FREQUENCY = 125 generate + THE_MAIN_PLL : pll_in125_out125 + port map( + CLK => CLK_GPLL_RIGHT, + CLKOP => clk_100_i, --125 from PLL + CLKOK => clk_200_i, --125 bypass + LOCK => pll_lock + ); + clk_serdes <= CLK_GPLL_LEFT; + clk_system <= clk_100_i; +end generate; --------------------------------------------------------------------------- -- The TrbNet media interface (Uplink) @@ -239,11 +257,12 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp generic map( SERDES_NUM => 0, --number of serdes in quad EXT_CLOCK => c_NO, --use internal clock - USE_200_MHZ => c_YES --run on 200 MHz clock + USE_200_MHZ => c_YES, --run on 200 MHz clock + USE_125_MHZ => c_NO ) port map( - CLK => clk_200_i, - SYSCLK => clk_100_i, + CLK => clk_serdes, + SYSCLK => clk_system, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -283,8 +302,8 @@ SFP_TXDIS(8 downto 2) <= (others => '1'); --------------------------------------------------------------------------- THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard port map( - CLK => clk_200_i, - SYSCLK => clk_100_i, + CLK => clk_serdes, + SYSCLK => clk_system, RESET => reset_i, CLEAR => clear_i, CLK_EN => '1', @@ -348,7 +367,7 @@ THE_HUB : trb_net16_hub_base BROADCAST_SPECIAL_ADDR => x"40" ) port map ( - CLK => clk_100_i, + CLK => clk_system, RESET => reset_i, CLK_EN => '1', @@ -398,7 +417,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) ) port map( - CLK => clk_100_i, + CLK => clk_system, RESET => reset_i, DAT_ADDR_IN => regio_addr_out, @@ -446,7 +465,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler THE_SPI_MASTER: spi_master port map( - CLK_IN => clk_100_i, + CLK_IN => clk_system, RESET_IN => reset_i, -- Slave bus BUS_READ_IN => spictrl_read_en, @@ -459,7 +478,7 @@ THE_SPI_MASTER: spi_master -- SPI connections SPI_CS_OUT => FLASH_CS, SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_CIN, + SPI_SDO_OUT => FLASH_DIN, --open, SPI_SCK_OUT => FLASH_CLK, -- BRAM for read/write data BRAM_A_OUT => spi_bram_addr, @@ -467,13 +486,13 @@ THE_SPI_MASTER: spi_master BRAM_RD_D_OUT => spi_bram_rd_d, BRAM_WE_OUT => spi_bram_we, -- Status lines - STAT => open + STAT => spi_debug ); -- data memory for SPI accesses THE_SPI_MEMORY: spi_databus_memory port map( - CLK_IN => clk_100_i, + CLK_IN => clk_system, RESET_IN => reset_i, -- Slave bus BUS_ADDR_IN => spimem_addr, @@ -496,7 +515,7 @@ THE_SPI_MEMORY: spi_databus_memory --------------------------------------------------------------------------- THE_FPGA_REBOOT : fpga_reboot port map( - CLK => clk_100_i, + CLK => clk_system, RESET => reset_i, DO_REBOOT => common_ctrl_regs(15), PROGRAMN => PROGRAMN @@ -559,21 +578,18 @@ THE_FPGA_REBOOT : fpga_reboot -- Test Connector --------------------------------------------------------------------------- - TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); - TEST_LINE(8) <= med_dataready_in(0); - TEST_LINE(9) <= med_dataready_out(0); - - - TEST_LINE(31 downto 10) <= (others => '0'); - + TEST_LINE <= spi_debug; +-- TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); +-- TEST_LINE(8) <= med_dataready_in(0); +-- TEST_LINE(9) <= med_dataready_out(0); +-- +-- +-- TEST_LINE(31 downto 10) <= (others => '0'); +-- FLASH_DIN <= not med_stat_op(10); --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - process - begin - wait until rising_edge(clk_100_i); - time_counter <= time_counter + 1; - end process; + end architecture; \ No newline at end of file diff --git a/base/trb3_central_constraints.lpf b/base/trb3_central_constraints.lpf index 06e5adb..8983b56 100644 --- a/base/trb3_central_constraints.lpf +++ b/base/trb3_central_constraints.lpf @@ -6,7 +6,6 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; @@ -16,20 +15,100 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT CLK_EXT_4 10 MHz; ################################################################# -# Reset Nets +# Reset Nets & other slow stuff ################################################################# GSR_NET NET "GSR_N"; +MULTICYCLE FROM CELL "THE_HUB/proc_SYNC_RESET*" 20 ns; +MULTICYCLE FROM CELL "THE_HUB/reset_i*" 20 ns; +MULTICYCLE FROM CELL "THE_HUB/gen_internal_reset*" 20 ns; +MULTICYCLE FROM CELL "med_stat_op_*" 30 ns; +MULTICYCLE FROM CELL "reset_i*" 20 ns; ################################################################# # Locate Serdes and media interfaces ################################################################# LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_MEDIA_ONBOARD/THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; -REGION "MEDIA_UPLINK" "R98C95" 17 27; -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +REGION "MEDIA_UPLINK" "R98C95D" 17 27 DEVSIZE; +REGION "MEDIA_ONBOARD" "R95C122D" 20 40 DEVSIZE; + +REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE; + +# REGION "REGION_MUX" "R84C90D" 32 80 DEVSIZE; +REGION "REGION_IOBUF" "R20C96D" 88 86 DEVSIZE; -REGION "MEDIA_ONBOARD" "R90C122" 25 40; LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ; +LOCATE UGROUP "THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +LOCATE UGROUP "THE_HUB/gen_muxes_4_MPLEX/MUX_group" REGION "REGION_IOBUF" ; + +################################################################# +# Locate Hub entities +################################################################# + +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; +# PGROUP "THE_HUB/hub_control/the_addresses/HUBLOGIC_group" +# PGROUP "THE_HUB/hub_control/RegIO_group" +# PGROUP "THE_HUB/gen_ctrl_api_CTRL_API/API_group" +# PGROUP "THE_BUS_HANDLER/Bus_handler_group" +# PGROUP "THE_HUB/THE_BUS_HANDLER/Bus_handler_group" +LOCATE UGROUP "THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +LOCATE UGROUP "THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; + + + + diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 8c1d102..8733655 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -12,10 +12,18 @@ component pll_in200_out100 port ( CLK: in std_logic; CLKOP: out std_logic; --100 MHz - CLKOK: out std_logic; --200 MHz + CLKOK: out std_logic; --200 MHz, bypass LOCK: out std_logic ); end component; - + +component pll_in125_out125 + port ( + CLK: in std_logic; + CLKOP: out std_logic; --125 MHz + CLKOK: out std_logic; --125 MHz, bypass + LOCK: out std_logic + ); + end component; end package; \ No newline at end of file diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf index ab5ecb5..f126c9e 100644 --- a/base/trb3_periph.lpf +++ b/base/trb3_periph.lpf @@ -6,7 +6,7 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 20; + SYSCONFIG MCCLK_FREQ = 2.5; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; diff --git a/base/trb3_periph.vhd b/base/trb3_periph.vhd index 2efe5c0..bf35bd1 100644 --- a/base/trb3_periph.vhd +++ b/base/trb3_periph.vhd @@ -50,7 +50,7 @@ entity trb3_periph is --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; - FLASH_CIN : out std_logic; + FLASH_DIN : out std_logic; FLASH_DOUT : in std_logic; PROGRAMN : out std_logic; --reboot FPGA @@ -83,7 +83,7 @@ entity trb3_periph is --important signals _with_ IO-FF attribute syn_useioff of FLASH_CLK : signal is true; attribute syn_useioff of FLASH_CS : signal is true; - attribute syn_useioff of FLASH_CIN : signal is true; + attribute syn_useioff of FLASH_DIN : signal is true; attribute syn_useioff of FLASH_DOUT : signal is true; attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_useioff of TEST_LINE : signal is true; @@ -229,9 +229,9 @@ THE_RESET_HANDLER : trb_net_reset_handler --------------------------------------------------------------------------- -- Clock Handling --------------------------------------------------------------------------- -THE_MAIN_PLL : pll_in200_out100 +THE_MAIN_PLL : pll_in125_out125 port map( - CLK => CLK_GPLL_RIGHT, + CLK => CLK_GPLL_LEFT, --CLK_GPLL_RIGHT CLKOP => clk_100_i, CLKOK => clk_200_i, LOCK => pll_lock @@ -289,11 +289,12 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS,--3, --8 cotrol reg ADDRESS_MASK => x"FFFF", BROADCAST_BITMASK => x"FF", + BROADCAST_SPECIAL_ADDR => x"45", REGIO_COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), REGIO_HARDWARE_VERSION => x"91000001", REGIO_INIT_ADDRESS => x"f300", REGIO_USE_VAR_ENDPOINT_ID => c_YES, - CLOCK_FREQUENCY => 100, + CLOCK_FREQUENCY => 125, TIMING_TRIGGER_RAW => c_YES, --Configure data handler DATA_INTERFACE_NUMBER => 1, @@ -463,7 +464,7 @@ THE_SPI_MASTER: spi_master -- SPI connections SPI_CS_OUT => FLASH_CS, SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_CIN, + SPI_SDO_OUT => FLASH_DIN, SPI_SCK_OUT => FLASH_CLK, -- BRAM for read/write data BRAM_A_OUT => spi_bram_addr, diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf index e6f2d33..01a0b7b 100644 --- a/base/trb3_periph_constraints.lpf +++ b/base/trb3_periph_constraints.lpf @@ -6,8 +6,6 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 20; - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; diff --git a/central_hub2/trb3_central.vhd b/central_hub2/trb3_central.vhd index 6359c1d..d5409b2 100644 --- a/central_hub2/trb3_central.vhd +++ b/central_hub2/trb3_central.vhd @@ -81,7 +81,7 @@ entity trb3_central is --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; - FLASH_CIN : out std_logic; + FLASH_DIN : out std_logic; FLASH_DOUT : in std_logic; PROGRAMN : out std_logic := '1'; --reboot FPGA @@ -459,7 +459,7 @@ THE_SPI_MASTER: spi_master -- SPI connections SPI_CS_OUT => FLASH_CS, SPI_SDI_IN => FLASH_DOUT, - SPI_SDO_OUT => FLASH_CIN, + SPI_SDO_OUT => FLASH_DIN, SPI_SCK_OUT => FLASH_CLK, -- BRAM for read/write data BRAM_A_OUT => spi_bram_addr, diff --git a/central_hub2/trb3_central_constraints.lpf b/central_hub2/trb3_central_constraints.lpf index 06e5adb..fd2ee17 100644 --- a/central_hub2/trb3_central_constraints.lpf +++ b/central_hub2/trb3_central_constraints.lpf @@ -6,7 +6,6 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 20; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; diff --git a/fpgatest/projects/trb3_central.ldf b/fpgatest/projects/trb3_central.ldf index c88fa26..a1a3287 100644 --- a/fpgatest/projects/trb3_central.ldf +++ b/fpgatest/projects/trb3_central.ldf @@ -182,14 +182,15 @@ - - + - - + + + + diff --git a/trb3_gbe_test/trb3_central.ldf b/trb3_gbe_test/trb3_central.ldf index 02042ab..40c1bef 100644 --- a/trb3_gbe_test/trb3_central.ldf +++ b/trb3_gbe_test/trb3_central.ldf @@ -1,7 +1,7 @@ - + @@ -36,9 +36,11 @@ + + + - diff --git a/trb3_gbe_test/trb3_central.vhd b/trb3_gbe_test/trb3_central.vhd index ffd7273..0b0f4a8 100644 --- a/trb3_gbe_test/trb3_central.vhd +++ b/trb3_gbe_test/trb3_central.vhd @@ -7,8 +7,8 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.trb_net16_hub_func.all; -use work.version.all; +--use work.trb_net16_hub_func.all; +--use work.version.all;