From: Ludwig Maier Date: Mon, 17 Feb 2014 02:13:00 +0000 (+0100) Subject: nxyter histogram bug removed, i2c handler update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=63c5ac9afe8023ab348be9ff66f7a7e28e6c231c;p=trb3.git nxyter histogram bug removed, i2c handler update --- diff --git a/nxyter/source/nx_histogram.vhd b/nxyter/source/nx_histogram.vhd index e27229f..5c67abd 100644 --- a/nxyter/source/nx_histogram.vhd +++ b/nxyter/source/nx_histogram.vhd @@ -67,10 +67,11 @@ architecture Behavioral of nx_histogram is -- Hist Read Handler signal read_address : std_logic_vector(BUS_WIDTH - 1 downto 0); signal read_data : std_logic_vector(DATA_WIDTH - 1 downto 0); + signal read_enable_p : std_logic; signal read_enable : std_logic; signal channel_data_o : std_logic_vector(DATA_WIDTH - 1 downto 0); signal channel_data_valid_o : std_logic; - signal channel_data_valid_o_f : std_logic; + signal channel_data_valid_o_f : std_logic_vector(2 downto 0); signal channel_read_busy_o : std_logic; begin @@ -83,12 +84,10 @@ begin DEBUG_OUT(3) <= write_enable_hist; DEBUG_OUT(4) <= channel_read_busy_o; DEBUG_OUT(5) <= CHANNEL_READ_IN; - DEBUG_OUT(6) <= read_enable_hist; + DEBUG_OUT(6) <= read_enable; DEBUG_OUT(7) <= channel_data_valid_o; --- DEBUG_OUT(15 downto 8) <= channel_data_o(7 downto 0); - DEBUG_OUT(14 downto 8) <= CHANNEL_ID_IN; - DEBUG_OUT(15) <= '0'; - + DEBUG_OUT(15 downto 8) <= channel_data_o(7 downto 0); + ----------------------------------------------------------------------------- ram_dp_128x40_hist: ram_dp_128x40 @@ -127,20 +126,54 @@ begin pulse_to_level_1: pulse_to_level generic map ( - NUM_CYCLES => 3 + NUM_CYCLES => 2 ) port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - PULSE_IN => read_enable, - LEVEL_OUT => channel_read_busy_o + PULSE_IN => read_enable_p, + LEVEL_OUT => read_enable ); - read_enable <= CHANNEL_READ_IN; - read_address <= CHANNEL_ID_READ_IN; - channel_data_valid_o_f <= CHANNEL_READ_IN when rising_edge(CLK_IN); - channel_data_valid_o <= channel_data_valid_o_f when rising_edge(CLK_IN); - channel_data_o <= read_data; + PROC_HIST_READ: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + read_enable_p <= '0'; + read_address <= (others => '0'); + channel_data_valid_o_f <= (others => '0'); + channel_data_valid_o <= '0'; + channel_data_o <= (others => '0'); + channel_read_busy_o <= '0'; + else + channel_data_valid_o_f(2) <= '0'; + channel_data_valid_o_f(1) <= channel_data_valid_o_f(2); + channel_data_valid_o_f(0) <= channel_data_valid_o_f(1); + + read_enable_p <= '0'; + read_address <= (others => '0'); + channel_data_o <= (others => '0'); + channel_data_valid_o <= '0'; + channel_read_busy_o <= '0'; + + if (CHANNEL_READ_IN = '1') then + read_enable_p <= '1'; + read_address <= CHANNEL_ID_READ_IN; + channel_data_valid_o_f(2) <= '1'; + end if; + + if (channel_data_valid_o_f(0) = '1') then + channel_data_o <= read_data; + channel_data_valid_o <= '1'; + end if; + if (channel_data_valid_o_f = "000" and CHANNEL_READ_IN = '0') then + channel_read_busy_o <= '0'; + else + channel_read_busy_o <= '1'; + end if; + end if; + end if; + end process PROC_HIST_READ; PROC_HIST_HANDLER_TRANSFER: process(CLK_IN) begin @@ -177,27 +210,25 @@ begin write_address <= (others => '0'); write_data <= (others => '0'); write_enable <= '0'; + channel_write_busy_o <= '0'; if (CHANNEL_ADD_IN = '1') then read_address_hist <= CHANNEL_ID_IN; read_enable_hist <= '1'; address_hist_m_x <= CHANNEL_ID_IN; data_hist_m_x <= CHANNEL_DATA_IN; - channel_write_busy_o <= '1'; H_NEXT_STATE <= H_WRITEADD_CHANNEL; elsif (CHANNEL_WRITE_IN = '1') then read_address_hist <= (others => '0'); read_enable_hist <= '0'; address_hist_m_x <= CHANNEL_ID_IN; data_hist_m_x <= CHANNEL_DATA_IN; - channel_write_busy_o <= '1'; H_NEXT_STATE <= H_WRITE_CHANNEL; else read_address_hist <= (others => '0'); read_enable_hist <= '0'; address_hist_m_x <= (others => '0'); data_hist_m_x <= (others => '0'); - channel_write_busy_o <= '0'; H_NEXT_STATE <= H_IDLE; end if; @@ -265,3 +296,4 @@ begin CHANNEL_READ_BUSY_OUT <= channel_read_busy_o; end Behavioral; + diff --git a/nxyter/source/nx_histograms.vhd b/nxyter/source/nx_histograms.vhd index 6d471f5..582f9bc 100644 --- a/nxyter/source/nx_histograms.vhd +++ b/nxyter/source/nx_histograms.vhd @@ -110,18 +110,18 @@ begin --------------------------------------------------------------------------- - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= CHANNEL_FILL_IN; - DEBUG_OUT(2) <= hit_write_busy; - DEBUG_OUT(3) <= pileup_write_busy; - DEBUG_OUT(4) <= ovfl_write_busy; - DEBUG_OUT(5) <= adc_write_busy; - - DEBUG_OUT(6) <= hit_read_busy; - DEBUG_OUT(7) <= pileup_read_busy; - DEBUG_OUT(8) <= ovfl_read_busy; - DEBUG_OUT(9) <= adc_read_busy; - DEBUG_OUT(15 downto 10) <= (others => '0'); + -- DEBUG_OUT(0) <= CLK_IN; + -- DEBUG_OUT(1) <= CHANNEL_FILL_IN; + -- DEBUG_OUT(2) <= hit_write_busy; + -- DEBUG_OUT(3) <= pileup_write_busy; + -- DEBUG_OUT(4) <= ovfl_write_busy; + -- DEBUG_OUT(5) <= adc_write_busy; + -- + -- DEBUG_OUT(6) <= hit_read_busy; + -- DEBUG_OUT(7) <= pileup_read_busy; + -- DEBUG_OUT(8) <= ovfl_read_busy; + -- DEBUG_OUT(9) <= adc_read_busy; + -- DEBUG_OUT(15 downto 10) <= (others => '0'); -- DEBUG_OUT(15 downto 1) <= SLV_ADDR_IN(14 downto 0); @@ -147,7 +147,7 @@ begin CHANNEL_DATA_VALID_OUT => hit_read_data_valid, CHANNEL_READ_BUSY_OUT => hit_read_busy, - DEBUG_OUT => open + DEBUG_OUT => DEBUG_OUT --open ); nx_histogram_adc: nx_histogram @@ -220,69 +220,74 @@ begin -- Fill Histograms ----------------------------------------------------------------------------- - - PROC_FILL_HISTOGRAMS: process(CHANNEL_FILL_IN, - CHANNEL_PILEUP_IN, - CHANNEL_OVERFLOW_IN - ) + PROC_FILL_HISTOGRAMS: process(CLK_IN) begin - if (CHANNEL_FILL_IN = '1') then - if (hit_write_busy = '0') then - hit_write_id <= "0000000"; --CHANNEL_ID_IN; - hit_write_data <= x"0000_0001"; + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + hit_write_id <= (others => '0'); + hit_write_data <= (others => '0'); hit_write <= '0'; - hit_add <= '1'; - - adc_write_id <= CHANNEL_ID_IN; - adc_write_data(11 downto 0) <= CHANNEL_ADC_IN; - adc_write_data(31 downto 12) <= (others => '0'); + hit_add <= '0'; + + adc_write_id <= (others => '0'); + adc_write_data <= (others => '0'); adc_write <= '0'; - adc_add <= '1'; + adc_add <= '0'; - if (CHANNEL_PILEUP_IN = '1') then - pileup_write_id <= CHANNEL_ID_IN; - pileup_write_data <= x"0000_0001"; - pileup_write <= '0'; - pileup_add <= '1'; - else - pileup_write_id <= (others => '0'); - pileup_write_data <= (others => '0'); - pileup_write <= '0'; - pileup_add <= '0'; - end if; - - if (CHANNEL_OVERFLOW_IN = '1') then - ovfl_write_id <= CHANNEL_ID_IN; - ovfl_write_data <= x"0000_0001"; - ovfl_write <= '0'; - ovfl_add <= '1'; - else - ovfl_write_id <= (others => '0'); - ovfl_write_data <= (others => '0'); - ovfl_write <= '0'; - ovfl_add <= '0'; + pileup_write_id <= (others => '0'); + pileup_write_data <= (others => '0'); + pileup_write <= '0'; + pileup_add <= '0'; + + ovfl_write_id <= (others => '0'); + ovfl_write_data <= (others => '0'); + ovfl_write <= '0'; + ovfl_add <= '0'; + else + hit_write_id <= (others => '0'); + hit_write_data <= (others => '0'); + hit_write <= '0'; + hit_add <= '0'; + + adc_write_id <= (others => '0'); + adc_write_data <= (others => '0'); + adc_write <= '0'; + adc_add <= '0'; + + pileup_write_id <= (others => '0'); + pileup_write_data <= (others => '0'); + pileup_write <= '0'; + pileup_add <= '0'; + + ovfl_write_id <= (others => '0'); + ovfl_write_data <= (others => '0'); + ovfl_write <= '0'; + ovfl_add <= '0'; + + if (CHANNEL_FILL_IN = '1' and hit_write_busy = '0') then + hit_write_id <= CHANNEL_ID_IN; + hit_write_data <= x"0000_0001"; + hit_add <= '1'; + + adc_write_id <= CHANNEL_ID_IN; + adc_write_data(11 downto 0) <= CHANNEL_ADC_IN; + adc_write_data(31 downto 12) <= (others => '0'); + adc_add <= '1'; + + if (CHANNEL_PILEUP_IN = '1') then + pileup_write_id <= CHANNEL_ID_IN; + pileup_write_data <= x"0000_0001"; + pileup_add <= '1'; + end if; + + if (CHANNEL_OVERFLOW_IN = '1') then + ovfl_write_id <= CHANNEL_ID_IN; + ovfl_write_data <= x"0000_0001"; + ovfl_add <= '1'; + end if; + end if; end if; - else - hit_write_id <= (others => '0'); - hit_write_data <= (others => '0'); - hit_write <= '0'; - hit_add <= '0'; - - adc_write_id <= (others => '0'); - adc_write_data <= (others => '0'); - adc_write <= '0'; - adc_add <= '0'; - - pileup_write_id <= (others => '0'); - pileup_write_data <= (others => '0'); - pileup_write <= '0'; - pileup_add <= '0'; - - ovfl_write_id <= (others => '0'); - ovfl_write_data <= (others => '0'); - ovfl_write <= '0'; - ovfl_add <= '0'; end if; end process PROC_FILL_HISTOGRAMS; @@ -361,8 +366,8 @@ begin slv_ack_o <= '0'; elsif (unsigned(SLV_ADDR_IN) >= x"0100" and unsigned(SLV_ADDR_IN) <= x"017f") then - adc_read_id <= SLV_ADDR_IN(6 downto 0); - adc_read <= '1'; + ovfl_read_id <= SLV_ADDR_IN(6 downto 0); + ovfl_read <= '1'; slv_ack_o <= '0'; elsif (unsigned(SLV_ADDR_IN) >= x"0200" and unsigned(SLV_ADDR_IN) <= x"027f") then @@ -371,8 +376,8 @@ begin slv_ack_o <= '0'; elsif (unsigned(SLV_ADDR_IN) >= x"0300" and unsigned(SLV_ADDR_IN) <= x"037f") then - ovfl_read_id <= SLV_ADDR_IN(6 downto 0); - ovfl_read <= '1'; + adc_read_id <= SLV_ADDR_IN(6 downto 0); + adc_read <= '1'; slv_ack_o <= '0'; else case SLV_ADDR_IN is @@ -386,40 +391,40 @@ begin slv_data_out_o(0) <= hit_average_enable; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - + when x"0180" => slv_data_out_o(2 downto 0) <= - std_logic_vector(adc_num_averages); + std_logic_vector(pileup_num_averages); slv_data_out_o(31 downto 3) <= (others => '0'); slv_ack_o <= '1'; when x"0181" => - slv_data_out_o(0) <= adc_average_enable; + slv_data_out_o(0) <= pileup_average_enable; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; when x"0280" => slv_data_out_o(2 downto 0) <= - std_logic_vector(pileup_num_averages); + std_logic_vector(ovfl_num_averages); slv_data_out_o(31 downto 3) <= (others => '0'); slv_ack_o <= '1'; when x"0281" => - slv_data_out_o(0) <= pileup_average_enable; + slv_data_out_o(0) <= ovfl_average_enable; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; when x"0380" => slv_data_out_o(2 downto 0) <= - std_logic_vector(ovfl_num_averages); + std_logic_vector(adc_num_averages); slv_data_out_o(31 downto 3) <= (others => '0'); slv_ack_o <= '1'; when x"0381" => - slv_data_out_o(0) <= ovfl_average_enable; + slv_data_out_o(0) <= adc_average_enable; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; @@ -437,31 +442,31 @@ begin when x"0081" => hit_average_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; - + when x"0180" => - adc_num_averages <= SLV_DATA_IN(2 downto 0); + pileup_num_averages <= SLV_DATA_IN(2 downto 0); slv_ack_o <= '1'; when x"0181" => - adc_average_enable <= SLV_DATA_IN(0); + pileup_average_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; when x"0280" => - pileup_num_averages <= SLV_DATA_IN(2 downto 0); + ovfl_num_averages <= SLV_DATA_IN(2 downto 0); slv_ack_o <= '1'; when x"0281" => - pileup_average_enable <= SLV_DATA_IN(0); + ovfl_average_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; when x"0380" => - ovfl_num_averages <= SLV_DATA_IN(2 downto 0); + adc_num_averages <= SLV_DATA_IN(2 downto 0); slv_ack_o <= '1'; when x"0381" => - ovfl_average_enable <= SLV_DATA_IN(0); + adc_average_enable <= SLV_DATA_IN(0); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; diff --git a/nxyter/source/nx_setup.vhd b/nxyter/source/nx_setup.vhd index 665448c..272ea14 100644 --- a/nxyter/source/nx_setup.vhd +++ b/nxyter/source/nx_setup.vhd @@ -75,16 +75,16 @@ architecture Behavioral of nx_setup is type i2c_ram_t is array(0 to 45) of std_logic_vector(7 downto 0); signal i2c_ram : i2c_ram_t; - type register_access_type_t is array(0 to 45) of std_logic; + type register_access_type_t is array(0 to 45) of std_logic_vector(1 downto 0); constant register_access_type : register_access_type_t := - ('1', '1', '1', '1', '1', '1', '1', '1', -- 0 -> 7 - '1', '1', '1', '1', '1', '1', '1', '1', -- 8 -> 15 - '1', '1', '1', '1', '1', '1', '1', '1', -- 16 -> 23 - '1', '1', '1', '1', '1', '1', '0', '0', -- 24 -> 31 - '1', '1', '0', '0', '0', '0', '1', '1', -- 32 -> 39 - '0', '0', '0', '1', '1', '1' -- 40 -> 45 + ("11", "11", "11", "11", "11", "11", "11", "11", -- 0 -> 7 + "11", "11", "11", "11", "11", "11", "11", "11", -- 8 -> 15 + "11", "11", "11", "11", "11", "11", "11", "11", -- 16 -> 23 + "11", "11", "11", "11", "11", "11", "00", "00", -- 24 -> 31 + "11", "11", "10", "10", "10", "10", "11", "11", -- 32 -> 39 + "00", "00", "00", "11", "11", "11" -- 40 -> 45 ); - + -- I2C RAM Handler signal ram_index_0 : integer; signal ram_index_1 : integer; @@ -271,12 +271,13 @@ begin i2c_write_token_r <= (others => '0'); do_write <= '0'; - if (ram_write_0 = '1' and register_access_type(ram_index_0) = '1') then + if (ram_write_0 = '1' and + register_access_type(ram_index_0)(0) = '1') then i2c_ram(ram_index_0) <= ram_data_0; i2c_write_token_r(ram_index_0) <= '1'; do_write <= '1'; elsif (ram_write_1 = '1' and - register_access_type(ram_index_1) = '1' and + register_access_type(ram_index_1)(0) = '1' and i2c_write_token(ram_index_1) = '0') then i2c_ram(ram_index_1) <= ram_data_1; do_write <= '1'; @@ -563,8 +564,8 @@ begin case T_STATE is when T_IDLE_TOKEN => - if (register_access_type(index) = '1') then - if (i2c_write_token(index) = '1') then + if (register_access_type(index)(0) = '1') then + if (i2c_write_token(index) = '1') then T_STATE <= T_WRITE_I2C_REGISTER; elsif (i2c_read_token(index) = '1') then T_STATE <= T_READ_I2C_REGISTER; @@ -1039,7 +1040,7 @@ begin int_data_o(7 downto 0) <= i2c_ram(index); int_data_o(28 downto 8) <= (others => '0'); int_data_o(29) <= - not register_access_type(index); + not register_access_type(index)(0); int_data_o(30) <= i2c_read_token(index); int_data_o(31) <= i2c_write_token(index); else @@ -1210,7 +1211,13 @@ begin elsif (SLV_ADDR_IN >= x"0100" and SLV_ADDR_IN <= x"0180") then -- Write value to ram - index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0))); + index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0))); + if (index = 0) then + index := 128; + else + index := index - 1; + end if; + if (i2c_disable_memory = '0') then dac_ram_index_0 <= index; dac_ram_data_0 <= SLV_DATA_IN(5 downto 0); @@ -1292,7 +1299,7 @@ begin slv_data_out_o(7 downto 0) <= i2c_ram(index); slv_data_out_o(28 downto 8) <= (others => '0'); slv_data_out_o(29) <= - not register_access_type(index); + not register_access_type(index)(0); slv_data_out_o(30) <= i2c_read_token(index); slv_data_out_o(31) <= i2c_write_token(index); else @@ -1301,7 +1308,13 @@ begin slv_ack_o <= '1'; elsif (SLV_ADDR_IN >= x"0100" and SLV_ADDR_IN <= x"0180") then - index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0))); + index := to_integer(unsigned(SLV_ADDR_IN(7 downto 0))); + if (index = 0) then + index := 128; + else + index := index - 1; + end if; + if (i2c_disable_memory = '0') then slv_data_out_o(5 downto 0) <= dac_ram(index); slv_data_out_o(29 downto 6) <= (others => '0'); @@ -1391,6 +1404,98 @@ begin slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; + when x"0060" => + -- Update Register I2C Status + if (unsigned(i2c_read_token) = 0) then + slv_data_out_o <= (others => '0'); + else + slv_data_out_o <= x"0000_0001"; + end if; + slv_ack_o <= '1'; + + when x"0061" => + -- Update Register DAC Status + if (unsigned(dac_read_token) = 0) then + slv_data_out_o <= (others => '0'); + else + slv_data_out_o <= x"0000_0001"; + end if; + slv_ack_o <= '1'; + + when x"0062" => + -- Update Register I2C and DAC Status + if (unsigned(i2c_read_token) = 0 and + unsigned(dac_read_token) = 0) then + slv_data_out_o <= (others => '0'); + else + slv_data_out_o <= x"0000_0001"; + end if; + slv_ack_o <= '1'; + + when x"0070" => + -- WriteToken + slv_data_out_o <= i2c_write_token(31 downto 0); + slv_ack_o <= '1'; + when x"0071" => + -- WriteToken + slv_data_out_o(13 downto 0) <= i2c_write_token(45 downto 32); + slv_data_out_o(31 downto 14) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0072" => + -- ReadToken + slv_data_out_o <= i2c_read_token(31 downto 0); + slv_ack_o <= '1'; + when x"0073" => + -- ReadToken + slv_data_out_o(13 downto 0) <= i2c_read_token(45 downto 32); + slv_data_out_o(31 downto 14) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0074" => + -- WriteTokenDAC + slv_data_out_o <= dac_write_token(31 downto 0); + slv_ack_o <= '1'; + when x"0075" => + -- WriteTokenDAC + slv_data_out_o <= dac_write_token(63 downto 32); + slv_ack_o <= '1'; + when x"0076" => + -- WriteTokenDAC + slv_data_out_o <= dac_write_token(95 downto 64); + slv_ack_o <= '1'; + when x"0077" => + -- WriteTokenDAC + slv_data_out_o <= dac_write_token(127 downto 96); + slv_ack_o <= '1'; + when x"0078" => + -- WriteTokenDAC + slv_data_out_o(0) <= dac_write_token(128); + slv_data_out_o(31 downto 1) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0079" => + -- ReadTokenDAC + slv_data_out_o <= dac_read_token(31 downto 0); + slv_ack_o <= '1'; + when x"007a" => + -- ReadTokenDAC + slv_data_out_o <= dac_read_token(63 downto 32); + slv_ack_o <= '1'; + when x"007b" => + -- ReadTokenDAC + slv_data_out_o <= dac_read_token(95 downto 64); + slv_ack_o <= '1'; + when x"007c" => + -- ReadTokenDAC + slv_data_out_o <= dac_read_token(127 downto 96); + slv_ack_o <= '1'; + when x"007d" => + -- ReadTokenDAC + slv_data_out_o(0) <= dac_read_token(128); + slv_data_out_o(31 downto 1) <= (others => '0'); + slv_ack_o <= '1'; + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; @@ -1398,7 +1503,7 @@ begin end if; else - slv_ack_o <= '0'; + slv_ack_o <= '0'; end if; end if; diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 89d9c23..40cb841 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -218,7 +218,7 @@ begin if( RESET_IN = '1' ) then reg_trigger_period <= x"00ff"; reg_trigger_num_cycles <= x"01"; - reg_testpulse_length <= x"001"; + reg_testpulse_length <= x"064"; reg_ts_reset_on <= '0'; slv_data_out_o <= (others => '0'); slv_no_more_data_o <= '0'; diff --git a/nxyter/source/nx_trigger_handler.vhd b/nxyter/source/nx_trigger_handler.vhd index d2fd595..71900cb 100644 --- a/nxyter/source/nx_trigger_handler.vhd +++ b/nxyter/source/nx_trigger_handler.vhd @@ -606,8 +606,9 @@ begin slv_ack_o <= '1'; when x"0001" => - reg_testpulse_delay <= unsigned(SLV_DATA_IN(11 downto 0)); - slv_ack_o <= '1'; + reg_testpulse_delay <= + unsigned(SLV_DATA_IN(11 downto 0)); + slv_ack_o <= '1'; when x"0003" => invalid_t_trigger_ctr_clear <= '1'; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index efc964e..71a7ceb 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -31,8 +31,9 @@ 2: 2,6,.. 3: 3,7,..) 0x8256 : r Nxyter I2C Online 0x8260 : w Read all I2C Registers into Memory -0x8261 : w Read Trim DAC Register(129 deep FIFO) into Memory -0x8262 : w Read ALL: Read Trim DAC Register(129 deep FIFO) into Memory +0x8261 : w Read Trim DAC Registers (129 deep FIFO) into Memory +0x8262 : w Read ALL: Read all I2C and all Trim DAC Registers into Memory +0x8270 : r Token register, 14 in a row -- Trigger Generator 0x8140 : r/w Length of Trigger TestPulse (12 Bit, in 4ns) @@ -171,10 +172,10 @@ 0x8060 : Access to SPI Interface -- Histogram Handler -0x8800 : r/w r: Read Channel HIt Statistic (128 channel in a row) -0x8900 : r Read Channel Trigger Rate (128 channel in a row, 1/s) -0x8a00 : r Read Channel averaged ADC Value (128 channel in a row) -0x8b00 : r Read Channel PileUp Rate (128 channel in a row, 1/s) +0x8800 : r Read Channel Hit Statistic (128 channel in a row) +0x8900 : r Read Channel Pileup Rate (128 channel in a row, 1/s) +0x8a00 : r Read Channel Overflow Rate (128 channel in a row, 1/s) +0x8b00 : r Read Channel averaged ADC Value (128 channel in a row) 0x8880 : r/w Hit Rate num averages (3 Bit) 0x8881 : r/w Hit Rate average enable