From: hadeshyp <hadeshyp>
Date: Thu, 3 Jan 2013 17:23:57 +0000 (+0000)
Subject: SPI master multi-write mode, JM
X-Git-Tag: oldGBE~22
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=644deb2c0fffc132b20b3baa51a6df21394e34ff;p=trbnet.git

SPI master multi-write mode, JM
---

diff --git a/gbe2_ecp3/trb_net16_ipu2gbe.vhd b/gbe2_ecp3/trb_net16_ipu2gbe.vhd
index 0f220a3..1337897 100755
--- a/gbe2_ecp3/trb_net16_ipu2gbe.vhd
+++ b/gbe2_ecp3/trb_net16_ipu2gbe.vhd
@@ -433,6 +433,7 @@ begin
 		-- gk 06.11.2012
 		when RESET_FIFO =>
 			saveNextState <= SIDLE;
+			state <= x"E";
 		-- gk 29.03.10 new states during which the subsub bytes are saved
 		when ADD_SUBSUB1 =>
 			state <= x"6";
diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd
index 57c3f70..4d2d2b3 100644
--- a/special/spi_ltc2600.vhd
+++ b/special/spi_ltc2600.vhd
@@ -29,7 +29,7 @@ architecture spi_ltc2600_arch of spi_ltc2600 is
   type ram_t is array(0 to 15) of std_logic_vector(31 downto 0);
   signal ram : ram_t;
   
-  signal ram_addr : integer range 0 to 15;
+  signal ram_addr : integer range 0 to 31;
   signal ram_data : std_logic_vector(31 downto 0);
   signal ctrl_reg : std_logic_vector(31 downto 0);
   signal start    : std_logic;
@@ -44,7 +44,7 @@ architecture spi_ltc2600_arch of spi_ltc2600 is
   signal time_count : integer range 0 to 7;
   signal readback   : std_logic_vector(31 downto 0);
   
-  type fsm_t is (IDLE, WAIT_STATE, SET, FINISH);
+  type fsm_t is (IDLE, WAIT_STATE, SET, TOGGLE_CS, TOGGLE_CS_0, TOGGLE_CS_1, TOGGLE_CS_2,  FINISH);
   signal fsm_state : fsm_t;
   
 begin
@@ -60,20 +60,18 @@ begin
       start        <= '0';
       
       if BUS_WRITE_IN = '1' then
-        if BUS_ADDR_IN(4) = '0' then
-          ram(addr) <= BUS_DATA_IN;
+        if fsm_state = IDLE then
           BUS_ACK_OUT <= '1';
-        elsif BUS_ADDR_IN(0) = '1' then
-          if fsm_state = IDLE then
+          if BUS_ADDR_IN(4) = '0' then
+            ram(addr) <= BUS_DATA_IN;
+          elsif BUS_ADDR_IN(0) = '1' then
             ctrl_reg    <= BUS_DATA_IN;
-            BUS_ACK_OUT <= '1';
             start       <= '1';
-          else
-            BUS_BUSY_OUT <= '1';
+          else --if BUS_ADDR_IN(0) = '0' then
+            chipselect_reg <= BUS_DATA_IN(15 downto 0);
           end if;
-        else --if BUS_ADDR_IN(1) = '0' then
-          chipselect_reg <= BUS_DATA_IN(15 downto 0);
-          BUS_ACK_OUT <= '1';
+        else
+          BUS_BUSY_OUT <= '1';
         end if;
       end if;
 
@@ -105,7 +103,7 @@ begin
       
         if start = '1' then
           ram_addr   <= 0;
-          word_count <= to_integer(unsigned(ctrl_reg(3 downto 0)));
+          word_count <= to_integer(unsigned(ctrl_reg(4 downto 0)));
           bit_count  <= 31;
           time_count <= 7;
           fsm_state  <= WAIT_STATE;
@@ -135,7 +133,11 @@ begin
             ram_addr  <= ram_addr + 1;
             bit_count <= 31;
             if ram_addr /= word_count -1 then
-              fsm_state <= WAIT_STATE;
+              if ctrl_reg(7) = '0' then --one CS phase
+                fsm_state <= WAIT_STATE;
+              else                      --one CS per word
+                fsm_state <= TOGGLE_CS; 
+              end if;
             else
               fsm_state <= FINISH;
             end if;
@@ -144,6 +146,38 @@ begin
           fsm_state  <= WAIT_STATE;
           readback   <= readback(30 downto 0) & SPI_SDI_IN;          
         end if;
+      when TOGGLE_CS =>
+        if time_count = 0 and spi_sck = '0' then
+          time_count <= 7;
+          spi_sck    <= not spi_sck;
+          readback   <= readback(30 downto 0) & SPI_SDI_IN;          
+        elsif time_count = 0 and spi_sck = '1' then
+          fsm_state  <= TOGGLE_CS_0;
+        else
+          time_count   <= time_count - 1;
+        end if;
+      when TOGGLE_CS_0 =>
+         time_count <= time_count - 1;
+         if time_count = 0 then
+           spi_cs     <= x"ffff";
+           fsm_state  <= TOGGLE_CS_1;
+           time_count <= 7;
+         end if;  
+      when TOGGLE_CS_1 =>
+         time_count <= time_count - 1;
+         if time_count = 0 then
+           spi_cs  <= not chipselect_reg;
+           bit_count <= 31;
+           fsm_state <= WAIT_STATE;
+           time_count <= 7;
+         end if;  
+      when TOGGLE_CS_2 =>           
+         time_count <= time_count - 1;
+         if time_count = 0 then
+           spi_sck <= not spi_sck;
+           fsm_state <= WAIT_STATE;
+           time_count <= 7;
+         end if;
       when FINISH =>
         if time_count = 0 and spi_sck = '0' then
           time_count <= 7;