From: Peter Lemmens Date: Tue, 19 Aug 2014 13:23:41 +0000 (+0200) Subject: Discussion update X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=64d59b9cdf42e43c6de9c5b6e7202826e699a6a1;p=soda.git Discussion update --- diff --git a/code/ip/serdes_4_sync_downstream.txt b/code/ip/serdes_4_sync_downstream.txt deleted file mode 100644 index 8e076a7..0000000 --- a/code/ip/serdes_4_sync_downstream.txt +++ /dev/null @@ -1,163 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "G8B10B" -CH1_PROTOCOL "G8B10B" -CH2_PROTOCOL "G8B10B" -CH3_PROTOCOL "G8B10B" -CH0_MODE "RXTX" -CH1_MODE "RXTX" -CH2_MODE "RXTX" -CH3_MODE "RXTX" -CH0_CDR_SRC "REFCLK_CORE" -CH1_CDR_SRC "REFCLK_CORE" -CH2_CDR_SRC "REFCLK_CORE" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH0_RX_DATARATE_RANGE "MEDHIGH" -CH1_RX_DATARATE_RANGE "MEDHIGH" -CH2_RX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200 -CH0_RX_DATA_RATE "FULL" -CH1_RX_DATA_RATE "FULL" -CH2_RX_DATA_RATE "FULL" -CH3_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH1_TX_DATA_RATE "FULL" -CH2_TX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH1_TX_DATA_WIDTH "8" -CH2_TX_DATA_WIDTH "8" -CH3_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH1_RX_DATA_WIDTH "8" -CH2_RX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH0_TX_FIFO "DISABLED" -CH1_TX_FIFO "DISABLED" -CH2_TX_FIFO "DISABLED" -CH3_TX_FIFO "DISABLED" -CH0_RX_FIFO "ENABLED" -CH1_RX_FIFO "ENABLED" -CH2_RX_FIFO "ENABLED" -CH3_RX_FIFO "ENABLED" -CH0_TDRV "0" -CH1_TDRV "0" -CH2_TDRV "0" -CH3_TDRV "0" -#CH0_TX_FICLK_RATE 200 -#CH1_TX_FICLK_RATE 200 -#CH2_TX_FICLK_RATE 200 -#CH3_TX_FICLK_RATE 200 -#CH0_RXREFCLK_RATE "200" -#CH1_RXREFCLK_RATE "200" -#CH2_RXREFCLK_RATE "200" -#CH3_RXREFCLK_RATE "200" -#CH0_RX_FICLK_RATE 200 -#CH1_RX_FICLK_RATE 200 -#CH2_RX_FICLK_RATE 200 -#CH3_RX_FICLK_RATE 200 -CH0_TX_PRE "DISABLED" -CH1_TX_PRE "DISABLED" -CH2_TX_PRE "DISABLED" -CH3_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH1_RTERM_TX "50" -CH2_RTERM_TX "50" -CH3_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH1_RX_EQ "DISABLED" -CH2_RX_EQ "DISABLED" -CH3_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH1_RTERM_RX "50" -CH2_RTERM_RX "50" -CH3_RTERM_RX "50" -CH0_RX_DCC "DC" -CH1_RX_DCC "DC" -CH2_RX_DCC "DC" -CH3_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "2" -CH1_LOS_THRESHOLD_LO "2" -CH2_LOS_THRESHOLD_LO "2" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "DC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH1_TX_SB "DISABLED" -CH2_TX_SB "DISABLED" -CH3_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH1_RX_SB "DISABLED" -CH2_RX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH1_TX_8B10B "ENABLED" -CH2_TX_8B10B "ENABLED" -CH3_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH1_RX_8B10B "ENABLED" -CH2_RX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH1_COMMA_A "1100000101" -CH2_COMMA_A "1100000101" -CH3_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH1_COMMA_B "0011111010" -CH2_COMMA_B "0011111010" -CH3_COMMA_B "0011111010" -CH0_COMMA_M "1111111100" -CH1_COMMA_M "1111111100" -CH2_COMMA_M "1111111100" -CH3_COMMA_M "1111111100" -CH0_RXWA "ENABLED" -CH1_RXWA "ENABLED" -CH2_RXWA "ENABLED" -CH3_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH1_ILSM "ENABLED" -CH2_ILSM "ENABLED" -CH3_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH1_CTC "DISABLED" -CH2_CTC "DISABLED" -CH3_CTC "DISABLED" -CH0_CC_MATCH4 "0000011100" -CH1_CC_MATCH4 "0000011100" -CH2_CC_MATCH4 "0000011100" -CH3_CC_MATCH4 "0000011100" -CH0_CC_MATCH_MODE "1" -CH1_CC_MATCH_MODE "1" -CH2_CC_MATCH_MODE "1" -CH3_CC_MATCH_MODE "1" -CH0_CC_MIN_IPG "3" -CH1_CC_MIN_IPG "3" -CH2_CC_MIN_IPG "3" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH1_SSLB "DISABLED" -CH2_SSLB "DISABLED" -CH3_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH1_SPLBPORTS "DISABLED" -CH2_SPLBPORTS "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -CH1_PCSLBPORTS "DISABLED" -CH2_PCSLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/code/ip/serdes_sync_client_upstream.ipx b/code/ip/serdes_sync_client_upstream.ipx deleted file mode 100644 index c1cdc76..0000000 --- a/code/ip/serdes_sync_client_upstream.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/code/ip/serdes_sync_client_upstream.lpc b/code/ip/serdes_sync_client_upstream.lpc deleted file mode 100644 index afb8e8d..0000000 --- a/code/ip/serdes_sync_client_upstream.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_sync_client_upstream -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/09/2014 -Time=15:42:39 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=RXTX -_mode1=DISABLED -_mode2=DISABLED -_mode3=DISABLED -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=2.0 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=200.0 -_tx_protocol0=G8B10B -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=DISABLED -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=DISABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=ENABLED -_tx_ficlk_rate0=200.0 -_tx_ficlk_rate1=200.0 -_tx_ficlk_rate2=200.0 -_tx_ficlk_rate3=200.0 -_pll_rxsrc0=INTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2.0 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=2.0 -_rx_protocol0=G8B10B -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=DISABLED -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=200.0 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=200.0 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=DISABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=ENABLED -_rx_ficlk_rate0=200.0 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=200.0 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=DC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=AC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=00 -_k01=00 -_k02=00 -_k03=00 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=01 -_byten00=00000000 -_byten01=00000000 -_byten02=00000000 -_byten03=00000000 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=ENABLED -_sci_int_port=ENABLED -_refck2core=DISABLED -Regen=module -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_sync_client_upstream.pp=pp -serdes_sync_client_upstream.tft=tft -serdes_sync_client_upstream.txt=pcs_module -serdes_sync_client_upstream.sym=sym diff --git a/code/ip/serdes_sync_client_upstream.vhd b/code/ip/serdes_sync_client_upstream.vhd deleted file mode 100644 index d94cde4..0000000 --- a/code/ip/serdes_sync_client_upstream.vhd +++ /dev/null @@ -1,2698 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_sync_client_upstream.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_CORE"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_sync_client_upstream is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_client_upstream.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - tx_force_disp_ch0 : in std_logic; - tx_disp_sel_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - sci_int : out std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_sync_client_upstream; - - -architecture serdes_sync_client_upstream_arch of serdes_sync_client_upstream is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH0_CDR_SRC: string; - attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100.000"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100.000"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch0_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - rx_los_low_ch0_s <= rx_los_low_ch0_sig; - rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch0 <= tx_full_clk_ch0_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH0_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => hdoutp_ch0, - HDOUTN0 => hdoutn_ch0, - HDINP0 => hdinp_ch0, - HDINN0 => hdinn_ch0, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => sci_sel_ch0, - SCIENCH0 => fpsc_vhi, - FF_RXI_CLK_0 => fpsc_vlo, - FF_TXI_CLK_0 => txiclk_ch0, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => rx_full_clk_ch0, - FF_RX_H_CLK_0 => rx_half_clk_ch0, - FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, - FF_TX_H_CLK_0 => tx_half_clk_ch0, - FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, - FF_TX_D_0_0 => txdata_ch0(0), - FF_TX_D_0_1 => txdata_ch0(1), - FF_TX_D_0_2 => txdata_ch0(2), - FF_TX_D_0_3 => txdata_ch0(3), - FF_TX_D_0_4 => txdata_ch0(4), - FF_TX_D_0_5 => txdata_ch0(5), - FF_TX_D_0_6 => txdata_ch0(6), - FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0, - FF_TX_D_0_9 => tx_force_disp_ch0, - FF_TX_D_0_10 => tx_disp_sel_ch0, - FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => rxdata_ch0(0), - FF_RX_D_0_1 => rxdata_ch0(1), - FF_RX_D_0_2 => rxdata_ch0(2), - FF_RX_D_0_3 => rxdata_ch0(3), - FF_RX_D_0_4 => rxdata_ch0(4), - FF_RX_D_0_5 => rxdata_ch0(5), - FF_RX_D_0_6 => rxdata_ch0(6), - FF_RX_D_0_7 => rxdata_ch0(7), - FF_RX_D_0_8 => rx_k_ch0, - FF_RX_D_0_9 => rx_disp_err_ch0, - FF_RX_D_0_10 => rx_cv_err_ch0, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => rx_serdes_rst_ch0_c, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, - FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c, - FFC_TXPWDNB_0 => tx_pwrup_ch0_c, - FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, - FFC_RXPWDNB_0 => rx_pwrup_ch0_c, - FFS_RLOS_LO_0 => rx_los_low_ch0_sig, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => rx_cdr_lol_ch0_sig, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => open, - HDOUTN3 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_TX_F_CLK_3 => open, - FF_TX_H_CLK_3 => open, - FFC_CK_CORE_RX_3 => fpsc_vlo, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => sci_wrdata(7), - SCIWDATA6 => sci_wrdata(6), - SCIWDATA5 => sci_wrdata(5), - SCIWDATA4 => sci_wrdata(4), - SCIWDATA3 => sci_wrdata(3), - SCIWDATA2 => sci_wrdata(2), - SCIWDATA1 => sci_wrdata(1), - SCIWDATA0 => sci_wrdata(0), - SCIADDR5 => sci_addr(5), - SCIADDR4 => sci_addr(4), - SCIADDR3 => sci_addr(3), - SCIADDR2 => sci_addr(2), - SCIADDR1 => sci_addr(1), - SCIADDR0 => sci_addr(0), - SCIRDATA7 => sci_rddata(7), - SCIRDATA6 => sci_rddata(6), - SCIRDATA5 => sci_rddata(5), - SCIRDATA4 => sci_rddata(4), - SCIRDATA3 => sci_rddata(3), - SCIRDATA2 => sci_rddata(2), - SCIRDATA1 => sci_rddata(1), - SCIRDATA0 => sci_rddata(0), - SCIENAUX => fpsc_vhi, - SCISELAUX => sci_sel_quad, - SCIRD => sci_rd, - SCIWSTN => sci_wrn, - CYAWSTN => fpsc_vlo, - SCIINT => sci_int, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_sync_client_upstream_arch ; diff --git a/code/ip/serdes_sync_downstream.vhd b/code/ip/serdes_sync_downstream.vhd deleted file mode 100644 index 10f2d1a..0000000 --- a/code/ip/serdes_sync_downstream.vhd +++ /dev/null @@ -1,2701 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_sync_downstream.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_CORE"; --- CH1_CDR_SRC : String := "REFCLK_CORE"; --- CH2_CDR_SRC : String := "REFCLK_CORE"; --- CH3_CDR_SRC : String := "REFCLK_CORE"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_sync_downstream is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_downstream.txt"); - port ( ------------------- --- CH0 -- - hdinp_ch0, hdinn_ch0 : in std_logic; - hdoutp_ch0, hdoutn_ch0 : out std_logic; - sci_sel_ch0 : in std_logic; - txiclk_ch0 : in std_logic; - rx_full_clk_ch0 : out std_logic; - rx_half_clk_ch0 : out std_logic; - tx_full_clk_ch0 : out std_logic; - tx_half_clk_ch0 : out std_logic; - fpga_rxrefclk_ch0 : in std_logic; - txdata_ch0 : in std_logic_vector (7 downto 0); - tx_k_ch0 : in std_logic; - tx_force_disp_ch0 : in std_logic; - tx_disp_sel_ch0 : in std_logic; - rxdata_ch0 : out std_logic_vector (7 downto 0); - rx_k_ch0 : out std_logic; - rx_disp_err_ch0 : out std_logic; - rx_cv_err_ch0 : out std_logic; - rx_serdes_rst_ch0_c : in std_logic; - sb_felb_ch0_c : in std_logic; - sb_felb_rst_ch0_c : in std_logic; - tx_pcs_rst_ch0_c : in std_logic; - tx_pwrup_ch0_c : in std_logic; - rx_pcs_rst_ch0_c : in std_logic; - rx_pwrup_ch0_c : in std_logic; - rx_los_low_ch0_s : out std_logic; - lsm_status_ch0_s : out std_logic; - rx_cdr_lol_ch0_s : out std_logic; - tx_div2_mode_ch0_c : in std_logic; - rx_div2_mode_ch0_c : in std_logic; --- CH1 -- --- CH2 -- --- CH3 -- ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - refclk2fpga : out std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_sync_downstream; - - -architecture serdes_sync_downstream_arch of serdes_sync_downstream is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH0_CDR_SRC: string; - attribute CH0_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch0_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - refclk2fpga <= refclk2fpga_sig; - rx_los_low_ch0_s <= rx_los_low_ch0_sig; - rx_cdr_lol_ch0_s <= rx_cdr_lol_ch0_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch0 <= tx_full_clk_ch0_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH0_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => hdoutp_ch0, - HDOUTN0 => hdoutn_ch0, - HDINP0 => hdinp_ch0, - HDINN0 => hdinn_ch0, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => sci_sel_ch0, - SCIENCH0 => fpsc_vhi, - FF_RXI_CLK_0 => fpsc_vlo, - FF_TXI_CLK_0 => txiclk_ch0, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => rx_full_clk_ch0, - FF_RX_H_CLK_0 => rx_half_clk_ch0, - FF_TX_F_CLK_0 => tx_full_clk_ch0_sig, - FF_TX_H_CLK_0 => tx_half_clk_ch0, - FFC_CK_CORE_RX_0 => fpga_rxrefclk_ch0, - FF_TX_D_0_0 => txdata_ch0(0), - FF_TX_D_0_1 => txdata_ch0(1), - FF_TX_D_0_2 => txdata_ch0(2), - FF_TX_D_0_3 => txdata_ch0(3), - FF_TX_D_0_4 => txdata_ch0(4), - FF_TX_D_0_5 => txdata_ch0(5), - FF_TX_D_0_6 => txdata_ch0(6), - FF_TX_D_0_7 => txdata_ch0(7), - FF_TX_D_0_8 => tx_k_ch0, - FF_TX_D_0_9 => tx_force_disp_ch0, - FF_TX_D_0_10 => tx_disp_sel_ch0, - FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => rxdata_ch0(0), - FF_RX_D_0_1 => rxdata_ch0(1), - FF_RX_D_0_2 => rxdata_ch0(2), - FF_RX_D_0_3 => rxdata_ch0(3), - FF_RX_D_0_4 => rxdata_ch0(4), - FF_RX_D_0_5 => rxdata_ch0(5), - FF_RX_D_0_6 => rxdata_ch0(6), - FF_RX_D_0_7 => rxdata_ch0(7), - FF_RX_D_0_8 => rx_k_ch0, - FF_RX_D_0_9 => rx_disp_err_ch0, - FF_RX_D_0_10 => rx_cv_err_ch0, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => rx_serdes_rst_ch0_c, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => sb_felb_ch0_c, - FFC_PFIFO_CLR_0 => sb_felb_rst_ch0_c, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => tx_pcs_rst_ch0_c, - FFC_TXPWDNB_0 => tx_pwrup_ch0_c, - FFC_LANE_RX_RST_0 => rx_pcs_rst_ch0_c, - FFC_RXPWDNB_0 => rx_pwrup_ch0_c, - FFS_RLOS_LO_0 => rx_los_low_ch0_sig, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => lsm_status_ch0_s, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => rx_cdr_lol_ch0_sig, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => tx_div2_mode_ch0_c, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => rx_div2_mode_ch0_c, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => open, - HDOUTN3 => open, - HDINP3 => fpsc_vlo, - HDINN3 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => fpsc_vlo, - SCIENCH3 => fpsc_vlo, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => fpsc_vlo, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => open, - FF_RX_H_CLK_3 => open, - FF_TX_F_CLK_3 => open, - FF_TX_H_CLK_3 => open, - FFC_CK_CORE_RX_3 => fpsc_vlo, - FF_TX_D_3_0 => fpsc_vlo, - FF_TX_D_3_1 => fpsc_vlo, - FF_TX_D_3_2 => fpsc_vlo, - FF_TX_D_3_3 => fpsc_vlo, - FF_TX_D_3_4 => fpsc_vlo, - FF_TX_D_3_5 => fpsc_vlo, - FF_TX_D_3_6 => fpsc_vlo, - FF_TX_D_3_7 => fpsc_vlo, - FF_TX_D_3_8 => fpsc_vlo, - FF_TX_D_3_9 => fpsc_vlo, - FF_TX_D_3_10 => fpsc_vlo, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => open, - FF_RX_D_3_1 => open, - FF_RX_D_3_2 => open, - FF_RX_D_3_3 => open, - FF_RX_D_3_4 => open, - FF_RX_D_3_5 => open, - FF_RX_D_3_6 => open, - FF_RX_D_3_7 => open, - FF_RX_D_3_8 => open, - FF_RX_D_3_9 => open, - FF_RX_D_3_10 => open, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => fpsc_vlo, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => fpsc_vlo, - FFC_PFIFO_CLR_3 => fpsc_vlo, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => fpsc_vlo, - FFC_TXPWDNB_3 => fpsc_vlo, - FFC_LANE_RX_RST_3 => fpsc_vlo, - FFC_RXPWDNB_3 => fpsc_vlo, - FFS_RLOS_LO_3 => open, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => open, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => open, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => fpsc_vlo, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => fpsc_vlo, - ------ Auxilliary ---- - SCIWDATA7 => sci_wrdata(7), - SCIWDATA6 => sci_wrdata(6), - SCIWDATA5 => sci_wrdata(5), - SCIWDATA4 => sci_wrdata(4), - SCIWDATA3 => sci_wrdata(3), - SCIWDATA2 => sci_wrdata(2), - SCIWDATA1 => sci_wrdata(1), - SCIWDATA0 => sci_wrdata(0), - SCIADDR5 => sci_addr(5), - SCIADDR4 => sci_addr(4), - SCIADDR3 => sci_addr(3), - SCIADDR2 => sci_addr(2), - SCIADDR1 => sci_addr(1), - SCIADDR0 => sci_addr(0), - SCIRDATA7 => sci_rddata(7), - SCIRDATA6 => sci_rddata(6), - SCIRDATA5 => sci_rddata(5), - SCIRDATA4 => sci_rddata(4), - SCIRDATA3 => sci_rddata(3), - SCIRDATA2 => sci_rddata(2), - SCIRDATA1 => sci_rddata(1), - SCIRDATA0 => sci_rddata(0), - SCIENAUX => fpsc_vhi, - SCISELAUX => sci_sel_quad, - SCIRD => sci_rd, - SCIWSTN => sci_wrn, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_sync_downstream_arch ; diff --git a/code/ip/serdes_sync_hub_upstream.ipx b/code/ip/serdes_sync_hub_upstream.ipx deleted file mode 100644 index 38d8cdb..0000000 --- a/code/ip/serdes_sync_hub_upstream.ipx +++ /dev/null @@ -1,11 +0,0 @@ - - - - - - - - - - - diff --git a/code/ip/serdes_sync_hub_upstream.lpc b/code/ip/serdes_sync_hub_upstream.lpc deleted file mode 100644 index a9affff..0000000 --- a/code/ip/serdes_sync_hub_upstream.lpc +++ /dev/null @@ -1,258 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN672C -SpeedGrade=8 -Package=FPBGA672 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PCS -CoreRevision=8.1 -ModuleName=serdes_sync_hub_upstream -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=04/16/2014 -Time=13:13:54 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=BusA(0 to 7) -Order=Big Endian [MSB:LSB] -IO=0 -_mode0=DISABLED -_mode1=DISABLED -_mode2=DISABLED -_mode3=RXTX -_protocol0=G8B10B -_protocol1=G8B10B -_protocol2=G8B10B -_protocol3=G8B10B -_ldr0=DISABLED -_ldr1=DISABLED -_ldr2=DISABLED -_ldr3=DISABLED -_datarange=2 -_pll_txsrc=INTERNAL -_refclk_mult=10X -_refclk_rate=200 -_tx_protocol0=DISABLED -_tx_protocol1=DISABLED -_tx_protocol2=DISABLED -_tx_protocol3=G8B10B -_tx_data_rate0=FULL -_tx_data_rate1=FULL -_tx_data_rate2=FULL -_tx_data_rate3=FULL -_tx_data_width0=8 -_tx_data_width1=8 -_tx_data_width2=8 -_tx_data_width3=8 -_tx_fifo0=ENABLED -_tx_fifo1=ENABLED -_tx_fifo2=ENABLED -_tx_fifo3=DISABLED -_tx_ficlk_rate0=200 -_tx_ficlk_rate1=200 -_tx_ficlk_rate2=200 -_tx_ficlk_rate3=200 -_pll_rxsrc0=EXTERNAL -_pll_rxsrc1=EXTERNAL -_pll_rxsrc2=EXTERNAL -_pll_rxsrc3=INTERNAL -Multiplier0= -Multiplier1= -Multiplier2= -Multiplier3= -_rx_datarange0=2.5 -_rx_datarange1=2.5 -_rx_datarange2=2.5 -_rx_datarange3=2 -_rx_protocol0=DISABLED -_rx_protocol1=DISABLED -_rx_protocol2=DISABLED -_rx_protocol3=G8B10B -_rx_data_rate0=FULL -_rx_data_rate1=FULL -_rx_data_rate2=FULL -_rx_data_rate3=FULL -_rxrefclk_rate0=250.0 -_rxrefclk_rate1=250.0 -_rxrefclk_rate2=250.0 -_rxrefclk_rate3=200 -_rx_data_width0=8 -_rx_data_width1=8 -_rx_data_width2=8 -_rx_data_width3=8 -_rx_fifo0=ENABLED -_rx_fifo1=ENABLED -_rx_fifo2=ENABLED -_rx_fifo3=DISABLED -_rx_ficlk_rate0=250.0 -_rx_ficlk_rate1=250.0 -_rx_ficlk_rate2=250.0 -_rx_ficlk_rate3=200 -_tdrv_ch0=0 -_tdrv_ch1=0 -_tdrv_ch2=0 -_tdrv_ch3=0 -_tx_pre0=DISABLED -_tx_pre1=DISABLED -_tx_pre2=DISABLED -_tx_pre3=DISABLED -_rterm_tx0=50 -_rterm_tx1=50 -_rterm_tx2=50 -_rterm_tx3=50 -_rx_eq0=DISABLED -_rx_eq1=DISABLED -_rx_eq2=DISABLED -_rx_eq3=DISABLED -_rterm_rx0=50 -_rterm_rx1=50 -_rterm_rx2=50 -_rterm_rx3=50 -_rx_dcc0=AC -_rx_dcc1=AC -_rx_dcc2=AC -_rx_dcc3=DC -_los_threshold_mode0=LOS_E -_los_threshold_mode1=LOS_E -_los_threshold_mode2=LOS_E -_los_threshold_mode3=LOS_E -_los_threshold_lo0=2 -_los_threshold_lo1=2 -_los_threshold_lo2=2 -_los_threshold_lo3=2 -_los_threshold_hi0=7 -_los_threshold_hi1=7 -_los_threshold_hi2=7 -_los_threshold_hi3=7 -_pll_term=50 -_pll_dcc=AC -_pll_lol_set=0 -_tx_sb0=DISABLED -_tx_sb1=DISABLED -_tx_sb2=DISABLED -_tx_sb3=DISABLED -_tx_8b10b0=ENABLED -_tx_8b10b1=ENABLED -_tx_8b10b2=ENABLED -_tx_8b10b3=ENABLED -_rx_sb0=DISABLED -_rx_sb1=DISABLED -_rx_sb2=DISABLED -_rx_sb3=DISABLED -_ird0=DISABLED -_ird1=DISABLED -_ird2=DISABLED -_ird3=DISABLED -_rx_8b10b0=ENABLED -_rx_8b10b1=ENABLED -_rx_8b10b2=ENABLED -_rx_8b10b3=ENABLED -_rxwa0=ENABLED -_rxwa1=ENABLED -_rxwa2=ENABLED -_rxwa3=ENABLED -_ilsm0=ENABLED -_ilsm1=ENABLED -_ilsm2=ENABLED -_ilsm3=ENABLED -_scomma0=K28P157 -_scomma1=K28P157 -_scomma2=K28P157 -_scomma3=K28P157 -_comma_a0=1100000101 -_comma_a1=1100000101 -_comma_a2=1100000101 -_comma_a3=1100000101 -_comma_b0=0011111010 -_comma_b1=0011111010 -_comma_b2=0011111010 -_comma_b3=0011111010 -_comma_m0=1111111100 -_comma_m1=1111111100 -_comma_m2=1111111100 -_comma_m3=1111111100 -_ctc0=DISABLED -_ctc1=DISABLED -_ctc2=DISABLED -_ctc3=DISABLED -_cc_match_mode0=1 -_cc_match_mode1=1 -_cc_match_mode2=1 -_cc_match_mode3=1 -_k00=00 -_k01=00 -_k02=00 -_k03=01 -_k10=00 -_k11=00 -_k12=00 -_k13=00 -_k20=01 -_k21=01 -_k22=01 -_k23=01 -_k30=01 -_k31=01 -_k32=01 -_k33=01 -_byten00=00000000 -_byten01=00000000 -_byten02=00000000 -_byten03=00011100 -_byten10=00000000 -_byten11=00000000 -_byten12=00000000 -_byten13=00000000 -_byten20=00011100 -_byten21=00011100 -_byten22=00011100 -_byten23=00011100 -_byten30=00011100 -_byten31=00011100 -_byten32=00011100 -_byten33=00011100 -_cc_min_ipg0=3 -_cc_min_ipg1=3 -_cc_min_ipg2=3 -_cc_min_ipg3=3 -_cchmark=9 -_cclmark=7 -_loopback=DISABLED -_lbtype0=DISABLED -_lbtype1=DISABLED -_lbtype2=DISABLED -_lbtype3=DISABLED -_teidle_ch0=DISABLED -_teidle_ch1=DISABLED -_teidle_ch2=DISABLED -_teidle_ch3=DISABLED -_rst_gen=DISABLED -_rx_los_port0=Internal -_rx_los_port1=Internal -_rx_los_port2=Internal -_rx_los_port3=Internal -_sci_ports=ENABLED -_sci_int_port=DISABLED -_refck2core=ENABLED -Regen=module -PAR1=0 -PARTrace1=0 -PAR3=0 -PARTrace3=0 - -[FilesGenerated] -serdes_sync_hub_upstream.pp=pp -serdes_sync_hub_upstream.tft=tft -serdes_sync_hub_upstream.txt=pcs_module -serdes_sync_hub_upstream.sym=sym diff --git a/code/ip/serdes_sync_hub_upstream.vhd b/code/ip/serdes_sync_hub_upstream.vhd deleted file mode 100644 index 7bd6faa..0000000 --- a/code/ip/serdes_sync_hub_upstream.vhd +++ /dev/null @@ -1,2701 +0,0 @@ - - - ---synopsys translate_off - -library pcsd_work; -use pcsd_work.all; -library IEEE; -use IEEE.std_logic_1164.all; - -entity PCSD is -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String --- CONFIG_FILE : String := "serdes_sync_hub_upstream.txt"; --- QUAD_MODE : String := "SINGLE"; --- CH0_CDR_SRC : String := "REFCLK_EXT"; --- CH1_CDR_SRC : String := "REFCLK_EXT"; --- CH2_CDR_SRC : String := "REFCLK_EXT"; --- CH3_CDR_SRC : String := "REFCLK_CORE"; --- PLL_SRC : String := "REFCLK_CORE" - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); - -end PCSD; - -architecture PCSD_arch of PCSD is - - -component PCSD_sim -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String; - CH1_CDR_SRC : String; - CH2_CDR_SRC : String; - CH3_CDR_SRC : String; - PLL_SRC : String - ); -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - -begin - -PCSD_sim_inst : PCSD_sim -generic map ( - CONFIG_FILE => CONFIG_FILE, - QUAD_MODE => QUAD_MODE, - CH0_CDR_SRC => CH0_CDR_SRC, - CH1_CDR_SRC => CH1_CDR_SRC, - CH2_CDR_SRC => CH2_CDR_SRC, - CH3_CDR_SRC => CH3_CDR_SRC, - PLL_SRC => PLL_SRC - ) -port map ( - HDINN0 => HDINN0, - HDINN1 => HDINN1, - HDINN2 => HDINN2, - HDINN3 => HDINN3, - HDINP0 => HDINP0, - HDINP1 => HDINP1, - HDINP2 => HDINP2, - HDINP3 => HDINP3, - REFCLKN => REFCLKN, - REFCLKP => REFCLKP, - CIN11 => CIN11, - CIN10 => CIN10, - CIN9 => CIN9, - CIN8 => CIN8, - CIN7 => CIN7, - CIN6 => CIN6, - CIN5 => CIN5, - CIN4 => CIN4, - CIN3 => CIN3, - CIN2 => CIN2, - CIN1 => CIN1, - CIN0 => CIN0, - CYAWSTN => CYAWSTN, - FF_EBRD_CLK_3 => FF_EBRD_CLK_3, - FF_EBRD_CLK_2 => FF_EBRD_CLK_2, - FF_EBRD_CLK_1 => FF_EBRD_CLK_1, - FF_EBRD_CLK_0 => FF_EBRD_CLK_0, - FF_RXI_CLK_3 => FF_RXI_CLK_3, - FF_RXI_CLK_2 => FF_RXI_CLK_2, - FF_RXI_CLK_1 => FF_RXI_CLK_1, - FF_RXI_CLK_0 => FF_RXI_CLK_0, - FF_TX_D_0_0 => FF_TX_D_0_0, - FF_TX_D_0_1 => FF_TX_D_0_1, - FF_TX_D_0_2 => FF_TX_D_0_2, - FF_TX_D_0_3 => FF_TX_D_0_3, - FF_TX_D_0_4 => FF_TX_D_0_4, - FF_TX_D_0_5 => FF_TX_D_0_5, - FF_TX_D_0_6 => FF_TX_D_0_6, - FF_TX_D_0_7 => FF_TX_D_0_7, - FF_TX_D_0_8 => FF_TX_D_0_8, - FF_TX_D_0_9 => FF_TX_D_0_9, - FF_TX_D_0_10 => FF_TX_D_0_10, - FF_TX_D_0_11 => FF_TX_D_0_11, - FF_TX_D_0_12 => FF_TX_D_0_12, - FF_TX_D_0_13 => FF_TX_D_0_13, - FF_TX_D_0_14 => FF_TX_D_0_14, - FF_TX_D_0_15 => FF_TX_D_0_15, - FF_TX_D_0_16 => FF_TX_D_0_16, - FF_TX_D_0_17 => FF_TX_D_0_17, - FF_TX_D_0_18 => FF_TX_D_0_18, - FF_TX_D_0_19 => FF_TX_D_0_19, - FF_TX_D_0_20 => FF_TX_D_0_20, - FF_TX_D_0_21 => FF_TX_D_0_21, - FF_TX_D_0_22 => FF_TX_D_0_22, - FF_TX_D_0_23 => FF_TX_D_0_23, - FF_TX_D_1_0 => FF_TX_D_1_0, - FF_TX_D_1_1 => FF_TX_D_1_1, - FF_TX_D_1_2 => FF_TX_D_1_2, - FF_TX_D_1_3 => FF_TX_D_1_3, - FF_TX_D_1_4 => FF_TX_D_1_4, - FF_TX_D_1_5 => FF_TX_D_1_5, - FF_TX_D_1_6 => FF_TX_D_1_6, - FF_TX_D_1_7 => FF_TX_D_1_7, - FF_TX_D_1_8 => FF_TX_D_1_8, - FF_TX_D_1_9 => FF_TX_D_1_9, - FF_TX_D_1_10 => FF_TX_D_1_10, - FF_TX_D_1_11 => FF_TX_D_1_11, - FF_TX_D_1_12 => FF_TX_D_1_12, - FF_TX_D_1_13 => FF_TX_D_1_13, - FF_TX_D_1_14 => FF_TX_D_1_14, - FF_TX_D_1_15 => FF_TX_D_1_15, - FF_TX_D_1_16 => FF_TX_D_1_16, - FF_TX_D_1_17 => FF_TX_D_1_17, - FF_TX_D_1_18 => FF_TX_D_1_18, - FF_TX_D_1_19 => FF_TX_D_1_19, - FF_TX_D_1_20 => FF_TX_D_1_20, - FF_TX_D_1_21 => FF_TX_D_1_21, - FF_TX_D_1_22 => FF_TX_D_1_22, - FF_TX_D_1_23 => FF_TX_D_1_23, - FF_TX_D_2_0 => FF_TX_D_2_0, - FF_TX_D_2_1 => FF_TX_D_2_1, - FF_TX_D_2_2 => FF_TX_D_2_2, - FF_TX_D_2_3 => FF_TX_D_2_3, - FF_TX_D_2_4 => FF_TX_D_2_4, - FF_TX_D_2_5 => FF_TX_D_2_5, - FF_TX_D_2_6 => FF_TX_D_2_6, - FF_TX_D_2_7 => FF_TX_D_2_7, - FF_TX_D_2_8 => FF_TX_D_2_8, - FF_TX_D_2_9 => FF_TX_D_2_9, - FF_TX_D_2_10 => FF_TX_D_2_10, - FF_TX_D_2_11 => FF_TX_D_2_11, - FF_TX_D_2_12 => FF_TX_D_2_12, - FF_TX_D_2_13 => FF_TX_D_2_13, - FF_TX_D_2_14 => FF_TX_D_2_14, - FF_TX_D_2_15 => FF_TX_D_2_15, - FF_TX_D_2_16 => FF_TX_D_2_16, - FF_TX_D_2_17 => FF_TX_D_2_17, - FF_TX_D_2_18 => FF_TX_D_2_18, - FF_TX_D_2_19 => FF_TX_D_2_19, - FF_TX_D_2_20 => FF_TX_D_2_20, - FF_TX_D_2_21 => FF_TX_D_2_21, - FF_TX_D_2_22 => FF_TX_D_2_22, - FF_TX_D_2_23 => FF_TX_D_2_23, - FF_TX_D_3_0 => FF_TX_D_3_0, - FF_TX_D_3_1 => FF_TX_D_3_1, - FF_TX_D_3_2 => FF_TX_D_3_2, - FF_TX_D_3_3 => FF_TX_D_3_3, - FF_TX_D_3_4 => FF_TX_D_3_4, - FF_TX_D_3_5 => FF_TX_D_3_5, - FF_TX_D_3_6 => FF_TX_D_3_6, - FF_TX_D_3_7 => FF_TX_D_3_7, - FF_TX_D_3_8 => FF_TX_D_3_8, - FF_TX_D_3_9 => FF_TX_D_3_9, - FF_TX_D_3_10 => FF_TX_D_3_10, - FF_TX_D_3_11 => FF_TX_D_3_11, - FF_TX_D_3_12 => FF_TX_D_3_12, - FF_TX_D_3_13 => FF_TX_D_3_13, - FF_TX_D_3_14 => FF_TX_D_3_14, - FF_TX_D_3_15 => FF_TX_D_3_15, - FF_TX_D_3_16 => FF_TX_D_3_16, - FF_TX_D_3_17 => FF_TX_D_3_17, - FF_TX_D_3_18 => FF_TX_D_3_18, - FF_TX_D_3_19 => FF_TX_D_3_19, - FF_TX_D_3_20 => FF_TX_D_3_20, - FF_TX_D_3_21 => FF_TX_D_3_21, - FF_TX_D_3_22 => FF_TX_D_3_22, - FF_TX_D_3_23 => FF_TX_D_3_23, - FF_TXI_CLK_0 => FF_TXI_CLK_0, - FF_TXI_CLK_1 => FF_TXI_CLK_1, - FF_TXI_CLK_2 => FF_TXI_CLK_2, - FF_TXI_CLK_3 => FF_TXI_CLK_3, - FFC_CK_CORE_RX_0 => FFC_CK_CORE_RX_0, - FFC_CK_CORE_RX_1 => FFC_CK_CORE_RX_1, - FFC_CK_CORE_RX_2 => FFC_CK_CORE_RX_2, - FFC_CK_CORE_RX_3 => FFC_CK_CORE_RX_3, - FFC_CK_CORE_TX => FFC_CK_CORE_TX, - FFC_EI_EN_0 => FFC_EI_EN_0, - FFC_EI_EN_1 => FFC_EI_EN_1, - FFC_EI_EN_2 => FFC_EI_EN_2, - FFC_EI_EN_3 => FFC_EI_EN_3, - FFC_ENABLE_CGALIGN_0 => FFC_ENABLE_CGALIGN_0, - FFC_ENABLE_CGALIGN_1 => FFC_ENABLE_CGALIGN_1, - FFC_ENABLE_CGALIGN_2 => FFC_ENABLE_CGALIGN_2, - FFC_ENABLE_CGALIGN_3 => FFC_ENABLE_CGALIGN_3, - FFC_FB_LOOPBACK_0 => FFC_FB_LOOPBACK_0, - FFC_FB_LOOPBACK_1 => FFC_FB_LOOPBACK_1, - FFC_FB_LOOPBACK_2 => FFC_FB_LOOPBACK_2, - FFC_FB_LOOPBACK_3 => FFC_FB_LOOPBACK_3, - FFC_LANE_RX_RST_0 => FFC_LANE_RX_RST_0, - FFC_LANE_RX_RST_1 => FFC_LANE_RX_RST_1, - FFC_LANE_RX_RST_2 => FFC_LANE_RX_RST_2, - FFC_LANE_RX_RST_3 => FFC_LANE_RX_RST_3, - FFC_LANE_TX_RST_0 => FFC_LANE_TX_RST_0, - FFC_LANE_TX_RST_1 => FFC_LANE_TX_RST_1, - FFC_LANE_TX_RST_2 => FFC_LANE_TX_RST_2, - FFC_LANE_TX_RST_3 => FFC_LANE_TX_RST_3, - FFC_MACRO_RST => FFC_MACRO_RST, - FFC_PCI_DET_EN_0 => FFC_PCI_DET_EN_0, - FFC_PCI_DET_EN_1 => FFC_PCI_DET_EN_1, - FFC_PCI_DET_EN_2 => FFC_PCI_DET_EN_2, - FFC_PCI_DET_EN_3 => FFC_PCI_DET_EN_3, - FFC_PCIE_CT_0 => FFC_PCIE_CT_0, - FFC_PCIE_CT_1 => FFC_PCIE_CT_1, - FFC_PCIE_CT_2 => FFC_PCIE_CT_2, - FFC_PCIE_CT_3 => FFC_PCIE_CT_3, - FFC_PFIFO_CLR_0 => FFC_PFIFO_CLR_0, - FFC_PFIFO_CLR_1 => FFC_PFIFO_CLR_1, - FFC_PFIFO_CLR_2 => FFC_PFIFO_CLR_2, - FFC_PFIFO_CLR_3 => FFC_PFIFO_CLR_3, - FFC_QUAD_RST => FFC_QUAD_RST, - FFC_RRST_0 => FFC_RRST_0, - FFC_RRST_1 => FFC_RRST_1, - FFC_RRST_2 => FFC_RRST_2, - FFC_RRST_3 => FFC_RRST_3, - FFC_RXPWDNB_0 => FFC_RXPWDNB_0, - FFC_RXPWDNB_1 => FFC_RXPWDNB_1, - FFC_RXPWDNB_2 => FFC_RXPWDNB_2, - FFC_RXPWDNB_3 => FFC_RXPWDNB_3, - FFC_SB_INV_RX_0 => FFC_SB_INV_RX_0, - FFC_SB_INV_RX_1 => FFC_SB_INV_RX_1, - FFC_SB_INV_RX_2 => FFC_SB_INV_RX_2, - FFC_SB_INV_RX_3 => FFC_SB_INV_RX_3, - FFC_SB_PFIFO_LP_0 => FFC_SB_PFIFO_LP_0, - FFC_SB_PFIFO_LP_1 => FFC_SB_PFIFO_LP_1, - FFC_SB_PFIFO_LP_2 => FFC_SB_PFIFO_LP_2, - FFC_SB_PFIFO_LP_3 => FFC_SB_PFIFO_LP_3, - FFC_SIGNAL_DETECT_0 => FFC_SIGNAL_DETECT_0, - FFC_SIGNAL_DETECT_1 => FFC_SIGNAL_DETECT_1, - FFC_SIGNAL_DETECT_2 => FFC_SIGNAL_DETECT_2, - FFC_SIGNAL_DETECT_3 => FFC_SIGNAL_DETECT_3, - FFC_SYNC_TOGGLE => FFC_SYNC_TOGGLE, - FFC_TRST => FFC_TRST, - FFC_TXPWDNB_0 => FFC_TXPWDNB_0, - FFC_TXPWDNB_1 => FFC_TXPWDNB_1, - FFC_TXPWDNB_2 => FFC_TXPWDNB_2, - FFC_TXPWDNB_3 => FFC_TXPWDNB_3, - FFC_RATE_MODE_RX_0 => FFC_RATE_MODE_RX_0, - FFC_RATE_MODE_RX_1 => FFC_RATE_MODE_RX_1, - FFC_RATE_MODE_RX_2 => FFC_RATE_MODE_RX_2, - FFC_RATE_MODE_RX_3 => FFC_RATE_MODE_RX_3, - FFC_RATE_MODE_TX_0 => FFC_RATE_MODE_TX_0, - FFC_RATE_MODE_TX_1 => FFC_RATE_MODE_TX_1, - FFC_RATE_MODE_TX_2 => FFC_RATE_MODE_TX_2, - FFC_RATE_MODE_TX_3 => FFC_RATE_MODE_TX_3, - FFC_DIV11_MODE_RX_0 => FFC_DIV11_MODE_RX_0, - FFC_DIV11_MODE_RX_1 => FFC_DIV11_MODE_RX_1, - FFC_DIV11_MODE_RX_2 => FFC_DIV11_MODE_RX_2, - FFC_DIV11_MODE_RX_3 => FFC_DIV11_MODE_RX_3, - FFC_DIV11_MODE_TX_0 => FFC_DIV11_MODE_TX_0, - FFC_DIV11_MODE_TX_1 => FFC_DIV11_MODE_TX_1, - FFC_DIV11_MODE_TX_2 => FFC_DIV11_MODE_TX_2, - FFC_DIV11_MODE_TX_3 => FFC_DIV11_MODE_TX_3, - LDR_CORE2TX_0 => LDR_CORE2TX_0, - LDR_CORE2TX_1 => LDR_CORE2TX_1, - LDR_CORE2TX_2 => LDR_CORE2TX_2, - LDR_CORE2TX_3 => LDR_CORE2TX_3, - FFC_LDR_CORE2TX_EN_0 => FFC_LDR_CORE2TX_EN_0, - FFC_LDR_CORE2TX_EN_1 => FFC_LDR_CORE2TX_EN_1, - FFC_LDR_CORE2TX_EN_2 => FFC_LDR_CORE2TX_EN_2, - FFC_LDR_CORE2TX_EN_3 => FFC_LDR_CORE2TX_EN_3, - PCIE_POWERDOWN_0_0 => PCIE_POWERDOWN_0_0, - PCIE_POWERDOWN_0_1 => PCIE_POWERDOWN_0_1, - PCIE_POWERDOWN_1_0 => PCIE_POWERDOWN_1_0, - PCIE_POWERDOWN_1_1 => PCIE_POWERDOWN_1_1, - PCIE_POWERDOWN_2_0 => PCIE_POWERDOWN_2_0, - PCIE_POWERDOWN_2_1 => PCIE_POWERDOWN_2_1, - PCIE_POWERDOWN_3_0 => PCIE_POWERDOWN_3_0, - PCIE_POWERDOWN_3_1 => PCIE_POWERDOWN_3_1, - PCIE_RXPOLARITY_0 => PCIE_RXPOLARITY_0, - PCIE_RXPOLARITY_1 => PCIE_RXPOLARITY_1, - PCIE_RXPOLARITY_2 => PCIE_RXPOLARITY_2, - PCIE_RXPOLARITY_3 => PCIE_RXPOLARITY_3, - PCIE_TXCOMPLIANCE_0 => PCIE_TXCOMPLIANCE_0, - PCIE_TXCOMPLIANCE_1 => PCIE_TXCOMPLIANCE_1, - PCIE_TXCOMPLIANCE_2 => PCIE_TXCOMPLIANCE_2, - PCIE_TXCOMPLIANCE_3 => PCIE_TXCOMPLIANCE_3, - PCIE_TXDETRX_PR2TLB_0 => PCIE_TXDETRX_PR2TLB_0, - PCIE_TXDETRX_PR2TLB_1 => PCIE_TXDETRX_PR2TLB_1, - PCIE_TXDETRX_PR2TLB_2 => PCIE_TXDETRX_PR2TLB_2, - PCIE_TXDETRX_PR2TLB_3 => PCIE_TXDETRX_PR2TLB_3, - SCIADDR0 => SCIADDR0, - SCIADDR1 => SCIADDR1, - SCIADDR2 => SCIADDR2, - SCIADDR3 => SCIADDR3, - SCIADDR4 => SCIADDR4, - SCIADDR5 => SCIADDR5, - SCIENAUX => SCIENAUX, - SCIENCH0 => SCIENCH0, - SCIENCH1 => SCIENCH1, - SCIENCH2 => SCIENCH2, - SCIENCH3 => SCIENCH3, - SCIRD => SCIRD, - SCISELAUX => SCISELAUX, - SCISELCH0 => SCISELCH0, - SCISELCH1 => SCISELCH1, - SCISELCH2 => SCISELCH2, - SCISELCH3 => SCISELCH3, - SCIWDATA0 => SCIWDATA0, - SCIWDATA1 => SCIWDATA1, - SCIWDATA2 => SCIWDATA2, - SCIWDATA3 => SCIWDATA3, - SCIWDATA4 => SCIWDATA4, - SCIWDATA5 => SCIWDATA5, - SCIWDATA6 => SCIWDATA6, - SCIWDATA7 => SCIWDATA7, - SCIWSTN => SCIWSTN, - HDOUTN0 => HDOUTN0, - HDOUTN1 => HDOUTN1, - HDOUTN2 => HDOUTN2, - HDOUTN3 => HDOUTN3, - HDOUTP0 => HDOUTP0, - HDOUTP1 => HDOUTP1, - HDOUTP2 => HDOUTP2, - HDOUTP3 => HDOUTP3, - COUT19 => COUT19, - COUT18 => COUT18, - COUT17 => COUT17, - COUT16 => COUT16, - COUT15 => COUT15, - COUT14 => COUT14, - COUT13 => COUT13, - COUT12 => COUT12, - COUT11 => COUT11, - COUT10 => COUT10, - COUT9 => COUT9, - COUT8 => COUT8, - COUT7 => COUT7, - COUT6 => COUT6, - COUT5 => COUT5, - COUT4 => COUT4, - COUT3 => COUT3, - COUT2 => COUT2, - COUT1 => COUT1, - COUT0 => COUT0, - FF_RX_D_0_0 => FF_RX_D_0_0, - FF_RX_D_0_1 => FF_RX_D_0_1, - FF_RX_D_0_2 => FF_RX_D_0_2, - FF_RX_D_0_3 => FF_RX_D_0_3, - FF_RX_D_0_4 => FF_RX_D_0_4, - FF_RX_D_0_5 => FF_RX_D_0_5, - FF_RX_D_0_6 => FF_RX_D_0_6, - FF_RX_D_0_7 => FF_RX_D_0_7, - FF_RX_D_0_8 => FF_RX_D_0_8, - FF_RX_D_0_9 => FF_RX_D_0_9, - FF_RX_D_0_10 => FF_RX_D_0_10, - FF_RX_D_0_11 => FF_RX_D_0_11, - FF_RX_D_0_12 => FF_RX_D_0_12, - FF_RX_D_0_13 => FF_RX_D_0_13, - FF_RX_D_0_14 => FF_RX_D_0_14, - FF_RX_D_0_15 => FF_RX_D_0_15, - FF_RX_D_0_16 => FF_RX_D_0_16, - FF_RX_D_0_17 => FF_RX_D_0_17, - FF_RX_D_0_18 => FF_RX_D_0_18, - FF_RX_D_0_19 => FF_RX_D_0_19, - FF_RX_D_0_20 => FF_RX_D_0_20, - FF_RX_D_0_21 => FF_RX_D_0_21, - FF_RX_D_0_22 => FF_RX_D_0_22, - FF_RX_D_0_23 => FF_RX_D_0_23, - FF_RX_D_1_0 => FF_RX_D_1_0, - FF_RX_D_1_1 => FF_RX_D_1_1, - FF_RX_D_1_2 => FF_RX_D_1_2, - FF_RX_D_1_3 => FF_RX_D_1_3, - FF_RX_D_1_4 => FF_RX_D_1_4, - FF_RX_D_1_5 => FF_RX_D_1_5, - FF_RX_D_1_6 => FF_RX_D_1_6, - FF_RX_D_1_7 => FF_RX_D_1_7, - FF_RX_D_1_8 => FF_RX_D_1_8, - FF_RX_D_1_9 => FF_RX_D_1_9, - FF_RX_D_1_10 => FF_RX_D_1_10, - FF_RX_D_1_11 => FF_RX_D_1_11, - FF_RX_D_1_12 => FF_RX_D_1_12, - FF_RX_D_1_13 => FF_RX_D_1_13, - FF_RX_D_1_14 => FF_RX_D_1_14, - FF_RX_D_1_15 => FF_RX_D_1_15, - FF_RX_D_1_16 => FF_RX_D_1_16, - FF_RX_D_1_17 => FF_RX_D_1_17, - FF_RX_D_1_18 => FF_RX_D_1_18, - FF_RX_D_1_19 => FF_RX_D_1_19, - FF_RX_D_1_20 => FF_RX_D_1_20, - FF_RX_D_1_21 => FF_RX_D_1_21, - FF_RX_D_1_22 => FF_RX_D_1_22, - FF_RX_D_1_23 => FF_RX_D_1_23, - FF_RX_D_2_0 => FF_RX_D_2_0, - FF_RX_D_2_1 => FF_RX_D_2_1, - FF_RX_D_2_2 => FF_RX_D_2_2, - FF_RX_D_2_3 => FF_RX_D_2_3, - FF_RX_D_2_4 => FF_RX_D_2_4, - FF_RX_D_2_5 => FF_RX_D_2_5, - FF_RX_D_2_6 => FF_RX_D_2_6, - FF_RX_D_2_7 => FF_RX_D_2_7, - FF_RX_D_2_8 => FF_RX_D_2_8, - FF_RX_D_2_9 => FF_RX_D_2_9, - FF_RX_D_2_10 => FF_RX_D_2_10, - FF_RX_D_2_11 => FF_RX_D_2_11, - FF_RX_D_2_12 => FF_RX_D_2_12, - FF_RX_D_2_13 => FF_RX_D_2_13, - FF_RX_D_2_14 => FF_RX_D_2_14, - FF_RX_D_2_15 => FF_RX_D_2_15, - FF_RX_D_2_16 => FF_RX_D_2_16, - FF_RX_D_2_17 => FF_RX_D_2_17, - FF_RX_D_2_18 => FF_RX_D_2_18, - FF_RX_D_2_19 => FF_RX_D_2_19, - FF_RX_D_2_20 => FF_RX_D_2_20, - FF_RX_D_2_21 => FF_RX_D_2_21, - FF_RX_D_2_22 => FF_RX_D_2_22, - FF_RX_D_2_23 => FF_RX_D_2_23, - FF_RX_D_3_0 => FF_RX_D_3_0, - FF_RX_D_3_1 => FF_RX_D_3_1, - FF_RX_D_3_2 => FF_RX_D_3_2, - FF_RX_D_3_3 => FF_RX_D_3_3, - FF_RX_D_3_4 => FF_RX_D_3_4, - FF_RX_D_3_5 => FF_RX_D_3_5, - FF_RX_D_3_6 => FF_RX_D_3_6, - FF_RX_D_3_7 => FF_RX_D_3_7, - FF_RX_D_3_8 => FF_RX_D_3_8, - FF_RX_D_3_9 => FF_RX_D_3_9, - FF_RX_D_3_10 => FF_RX_D_3_10, - FF_RX_D_3_11 => FF_RX_D_3_11, - FF_RX_D_3_12 => FF_RX_D_3_12, - FF_RX_D_3_13 => FF_RX_D_3_13, - FF_RX_D_3_14 => FF_RX_D_3_14, - FF_RX_D_3_15 => FF_RX_D_3_15, - FF_RX_D_3_16 => FF_RX_D_3_16, - FF_RX_D_3_17 => FF_RX_D_3_17, - FF_RX_D_3_18 => FF_RX_D_3_18, - FF_RX_D_3_19 => FF_RX_D_3_19, - FF_RX_D_3_20 => FF_RX_D_3_20, - FF_RX_D_3_21 => FF_RX_D_3_21, - FF_RX_D_3_22 => FF_RX_D_3_22, - FF_RX_D_3_23 => FF_RX_D_3_23, - FF_RX_F_CLK_0 => FF_RX_F_CLK_0, - FF_RX_F_CLK_1 => FF_RX_F_CLK_1, - FF_RX_F_CLK_2 => FF_RX_F_CLK_2, - FF_RX_F_CLK_3 => FF_RX_F_CLK_3, - FF_RX_H_CLK_0 => FF_RX_H_CLK_0, - FF_RX_H_CLK_1 => FF_RX_H_CLK_1, - FF_RX_H_CLK_2 => FF_RX_H_CLK_2, - FF_RX_H_CLK_3 => FF_RX_H_CLK_3, - FF_TX_F_CLK_0 => FF_TX_F_CLK_0, - FF_TX_F_CLK_1 => FF_TX_F_CLK_1, - FF_TX_F_CLK_2 => FF_TX_F_CLK_2, - FF_TX_F_CLK_3 => FF_TX_F_CLK_3, - FF_TX_H_CLK_0 => FF_TX_H_CLK_0, - FF_TX_H_CLK_1 => FF_TX_H_CLK_1, - FF_TX_H_CLK_2 => FF_TX_H_CLK_2, - FF_TX_H_CLK_3 => FF_TX_H_CLK_3, - FFS_CC_OVERRUN_0 => FFS_CC_OVERRUN_0, - FFS_CC_OVERRUN_1 => FFS_CC_OVERRUN_1, - FFS_CC_OVERRUN_2 => FFS_CC_OVERRUN_2, - FFS_CC_OVERRUN_3 => FFS_CC_OVERRUN_3, - FFS_CC_UNDERRUN_0 => FFS_CC_UNDERRUN_0, - FFS_CC_UNDERRUN_1 => FFS_CC_UNDERRUN_1, - FFS_CC_UNDERRUN_2 => FFS_CC_UNDERRUN_2, - FFS_CC_UNDERRUN_3 => FFS_CC_UNDERRUN_3, - FFS_LS_SYNC_STATUS_0 => FFS_LS_SYNC_STATUS_0, - FFS_LS_SYNC_STATUS_1 => FFS_LS_SYNC_STATUS_1, - FFS_LS_SYNC_STATUS_2 => FFS_LS_SYNC_STATUS_2, - FFS_LS_SYNC_STATUS_3 => FFS_LS_SYNC_STATUS_3, - FFS_CDR_TRAIN_DONE_0 => FFS_CDR_TRAIN_DONE_0, - FFS_CDR_TRAIN_DONE_1 => FFS_CDR_TRAIN_DONE_1, - FFS_CDR_TRAIN_DONE_2 => FFS_CDR_TRAIN_DONE_2, - FFS_CDR_TRAIN_DONE_3 => FFS_CDR_TRAIN_DONE_3, - FFS_PCIE_CON_0 => FFS_PCIE_CON_0, - FFS_PCIE_CON_1 => FFS_PCIE_CON_1, - FFS_PCIE_CON_2 => FFS_PCIE_CON_2, - FFS_PCIE_CON_3 => FFS_PCIE_CON_3, - FFS_PCIE_DONE_0 => FFS_PCIE_DONE_0, - FFS_PCIE_DONE_1 => FFS_PCIE_DONE_1, - FFS_PCIE_DONE_2 => FFS_PCIE_DONE_2, - FFS_PCIE_DONE_3 => FFS_PCIE_DONE_3, - FFS_PLOL => FFS_PLOL, - FFS_RLOL_0 => FFS_RLOL_0, - FFS_RLOL_1 => FFS_RLOL_1, - FFS_RLOL_2 => FFS_RLOL_2, - FFS_RLOL_3 => FFS_RLOL_3, - FFS_RLOS_HI_0 => FFS_RLOS_HI_0, - FFS_RLOS_HI_1 => FFS_RLOS_HI_1, - FFS_RLOS_HI_2 => FFS_RLOS_HI_2, - FFS_RLOS_HI_3 => FFS_RLOS_HI_3, - FFS_RLOS_LO_0 => FFS_RLOS_LO_0, - FFS_RLOS_LO_1 => FFS_RLOS_LO_1, - FFS_RLOS_LO_2 => FFS_RLOS_LO_2, - FFS_RLOS_LO_3 => FFS_RLOS_LO_3, - FFS_RXFBFIFO_ERROR_0 => FFS_RXFBFIFO_ERROR_0, - FFS_RXFBFIFO_ERROR_1 => FFS_RXFBFIFO_ERROR_1, - FFS_RXFBFIFO_ERROR_2 => FFS_RXFBFIFO_ERROR_2, - FFS_RXFBFIFO_ERROR_3 => FFS_RXFBFIFO_ERROR_3, - FFS_TXFBFIFO_ERROR_0 => FFS_TXFBFIFO_ERROR_0, - FFS_TXFBFIFO_ERROR_1 => FFS_TXFBFIFO_ERROR_1, - FFS_TXFBFIFO_ERROR_2 => FFS_TXFBFIFO_ERROR_2, - FFS_TXFBFIFO_ERROR_3 => FFS_TXFBFIFO_ERROR_3, - PCIE_PHYSTATUS_0 => PCIE_PHYSTATUS_0, - PCIE_PHYSTATUS_1 => PCIE_PHYSTATUS_1, - PCIE_PHYSTATUS_2 => PCIE_PHYSTATUS_2, - PCIE_PHYSTATUS_3 => PCIE_PHYSTATUS_3, - PCIE_RXVALID_0 => PCIE_RXVALID_0, - PCIE_RXVALID_1 => PCIE_RXVALID_1, - PCIE_RXVALID_2 => PCIE_RXVALID_2, - PCIE_RXVALID_3 => PCIE_RXVALID_3, - FFS_SKP_ADDED_0 => FFS_SKP_ADDED_0, - FFS_SKP_ADDED_1 => FFS_SKP_ADDED_1, - FFS_SKP_ADDED_2 => FFS_SKP_ADDED_2, - FFS_SKP_ADDED_3 => FFS_SKP_ADDED_3, - FFS_SKP_DELETED_0 => FFS_SKP_DELETED_0, - FFS_SKP_DELETED_1 => FFS_SKP_DELETED_1, - FFS_SKP_DELETED_2 => FFS_SKP_DELETED_2, - FFS_SKP_DELETED_3 => FFS_SKP_DELETED_3, - LDR_RX2CORE_0 => LDR_RX2CORE_0, - LDR_RX2CORE_1 => LDR_RX2CORE_1, - LDR_RX2CORE_2 => LDR_RX2CORE_2, - LDR_RX2CORE_3 => LDR_RX2CORE_3, - REFCK2CORE => REFCK2CORE, - SCIINT => SCIINT, - SCIRDATA0 => SCIRDATA0, - SCIRDATA1 => SCIRDATA1, - SCIRDATA2 => SCIRDATA2, - SCIRDATA3 => SCIRDATA3, - SCIRDATA4 => SCIRDATA4, - SCIRDATA5 => SCIRDATA5, - SCIRDATA6 => SCIRDATA6, - SCIRDATA7 => SCIRDATA7, - REFCLK_FROM_NQ => REFCLK_FROM_NQ, - REFCLK_TO_NQ => REFCLK_TO_NQ - ); - -end PCSD_arch; - ---synopsys translate_on - - - - ---synopsys translate_off -library ECP3; -use ECP3.components.all; ---synopsys translate_on - - -library IEEE, STD; -use IEEE.std_logic_1164.all; -use STD.TEXTIO.all; - -entity serdes_sync_hub_upstream is - GENERIC (USER_CONFIG_FILE : String := "serdes_sync_hub_upstream.txt"); - port ( ------------------- --- CH0 -- --- CH1 -- --- CH2 -- --- CH3 -- - hdinp_ch3, hdinn_ch3 : in std_logic; - hdoutp_ch3, hdoutn_ch3 : out std_logic; - sci_sel_ch3 : in std_logic; - txiclk_ch3 : in std_logic; - rx_full_clk_ch3 : out std_logic; - rx_half_clk_ch3 : out std_logic; - tx_full_clk_ch3 : out std_logic; - tx_half_clk_ch3 : out std_logic; - fpga_rxrefclk_ch3 : in std_logic; - txdata_ch3 : in std_logic_vector (7 downto 0); - tx_k_ch3 : in std_logic; - tx_force_disp_ch3 : in std_logic; - tx_disp_sel_ch3 : in std_logic; - rxdata_ch3 : out std_logic_vector (7 downto 0); - rx_k_ch3 : out std_logic; - rx_disp_err_ch3 : out std_logic; - rx_cv_err_ch3 : out std_logic; - rx_serdes_rst_ch3_c : in std_logic; - sb_felb_ch3_c : in std_logic; - sb_felb_rst_ch3_c : in std_logic; - tx_pcs_rst_ch3_c : in std_logic; - tx_pwrup_ch3_c : in std_logic; - rx_pcs_rst_ch3_c : in std_logic; - rx_pwrup_ch3_c : in std_logic; - rx_los_low_ch3_s : out std_logic; - lsm_status_ch3_s : out std_logic; - rx_cdr_lol_ch3_s : out std_logic; - tx_div2_mode_ch3_c : in std_logic; - rx_div2_mode_ch3_c : in std_logic; ----- Miscillaneous ports - sci_wrdata : in std_logic_vector (7 downto 0); - sci_addr : in std_logic_vector (5 downto 0); - sci_rddata : out std_logic_vector (7 downto 0); - sci_sel_quad : in std_logic; - sci_rd : in std_logic; - sci_wrn : in std_logic; - fpga_txrefclk : in std_logic; - tx_serdes_rst_c : in std_logic; - tx_pll_lol_qd_s : out std_logic; - rst_qd_c : in std_logic; - refclk2fpga : out std_logic; - serdes_rst_qd_c : in std_logic); - -end serdes_sync_hub_upstream; - - -architecture serdes_sync_hub_upstream_arch of serdes_sync_hub_upstream is - -component VLO -port ( - Z : out std_logic); -end component; - -component VHI -port ( - Z : out std_logic); -end component; - - - -component PCSD ---synopsys translate_off -GENERIC( - CONFIG_FILE : String; - QUAD_MODE : String; - CH0_CDR_SRC : String := "REFCLK_EXT"; - CH1_CDR_SRC : String := "REFCLK_EXT"; - CH2_CDR_SRC : String := "REFCLK_EXT"; - CH3_CDR_SRC : String := "REFCLK_EXT"; - PLL_SRC : String - ); ---synopsys translate_on -port ( - HDINN0 : in std_logic; - HDINN1 : in std_logic; - HDINN2 : in std_logic; - HDINN3 : in std_logic; - HDINP0 : in std_logic; - HDINP1 : in std_logic; - HDINP2 : in std_logic; - HDINP3 : in std_logic; - REFCLKN : in std_logic; - REFCLKP : in std_logic; - CIN0 : in std_logic; - CIN1 : in std_logic; - CIN2 : in std_logic; - CIN3 : in std_logic; - CIN4 : in std_logic; - CIN5 : in std_logic; - CIN6 : in std_logic; - CIN7 : in std_logic; - CIN8 : in std_logic; - CIN9 : in std_logic; - CIN10 : in std_logic; - CIN11 : in std_logic; - CYAWSTN : in std_logic; - FF_EBRD_CLK_0 : in std_logic; - FF_EBRD_CLK_1 : in std_logic; - FF_EBRD_CLK_2 : in std_logic; - FF_EBRD_CLK_3 : in std_logic; - FF_RXI_CLK_0 : in std_logic; - FF_RXI_CLK_1 : in std_logic; - FF_RXI_CLK_2 : in std_logic; - FF_RXI_CLK_3 : in std_logic; - FF_TX_D_0_0 : in std_logic; - FF_TX_D_0_1 : in std_logic; - FF_TX_D_0_2 : in std_logic; - FF_TX_D_0_3 : in std_logic; - FF_TX_D_0_4 : in std_logic; - FF_TX_D_0_5 : in std_logic; - FF_TX_D_0_6 : in std_logic; - FF_TX_D_0_7 : in std_logic; - FF_TX_D_0_8 : in std_logic; - FF_TX_D_0_9 : in std_logic; - FF_TX_D_0_10 : in std_logic; - FF_TX_D_0_11 : in std_logic; - FF_TX_D_0_12 : in std_logic; - FF_TX_D_0_13 : in std_logic; - FF_TX_D_0_14 : in std_logic; - FF_TX_D_0_15 : in std_logic; - FF_TX_D_0_16 : in std_logic; - FF_TX_D_0_17 : in std_logic; - FF_TX_D_0_18 : in std_logic; - FF_TX_D_0_19 : in std_logic; - FF_TX_D_0_20 : in std_logic; - FF_TX_D_0_21 : in std_logic; - FF_TX_D_0_22 : in std_logic; - FF_TX_D_0_23 : in std_logic; - FF_TX_D_1_0 : in std_logic; - FF_TX_D_1_1 : in std_logic; - FF_TX_D_1_2 : in std_logic; - FF_TX_D_1_3 : in std_logic; - FF_TX_D_1_4 : in std_logic; - FF_TX_D_1_5 : in std_logic; - FF_TX_D_1_6 : in std_logic; - FF_TX_D_1_7 : in std_logic; - FF_TX_D_1_8 : in std_logic; - FF_TX_D_1_9 : in std_logic; - FF_TX_D_1_10 : in std_logic; - FF_TX_D_1_11 : in std_logic; - FF_TX_D_1_12 : in std_logic; - FF_TX_D_1_13 : in std_logic; - FF_TX_D_1_14 : in std_logic; - FF_TX_D_1_15 : in std_logic; - FF_TX_D_1_16 : in std_logic; - FF_TX_D_1_17 : in std_logic; - FF_TX_D_1_18 : in std_logic; - FF_TX_D_1_19 : in std_logic; - FF_TX_D_1_20 : in std_logic; - FF_TX_D_1_21 : in std_logic; - FF_TX_D_1_22 : in std_logic; - FF_TX_D_1_23 : in std_logic; - FF_TX_D_2_0 : in std_logic; - FF_TX_D_2_1 : in std_logic; - FF_TX_D_2_2 : in std_logic; - FF_TX_D_2_3 : in std_logic; - FF_TX_D_2_4 : in std_logic; - FF_TX_D_2_5 : in std_logic; - FF_TX_D_2_6 : in std_logic; - FF_TX_D_2_7 : in std_logic; - FF_TX_D_2_8 : in std_logic; - FF_TX_D_2_9 : in std_logic; - FF_TX_D_2_10 : in std_logic; - FF_TX_D_2_11 : in std_logic; - FF_TX_D_2_12 : in std_logic; - FF_TX_D_2_13 : in std_logic; - FF_TX_D_2_14 : in std_logic; - FF_TX_D_2_15 : in std_logic; - FF_TX_D_2_16 : in std_logic; - FF_TX_D_2_17 : in std_logic; - FF_TX_D_2_18 : in std_logic; - FF_TX_D_2_19 : in std_logic; - FF_TX_D_2_20 : in std_logic; - FF_TX_D_2_21 : in std_logic; - FF_TX_D_2_22 : in std_logic; - FF_TX_D_2_23 : in std_logic; - FF_TX_D_3_0 : in std_logic; - FF_TX_D_3_1 : in std_logic; - FF_TX_D_3_2 : in std_logic; - FF_TX_D_3_3 : in std_logic; - FF_TX_D_3_4 : in std_logic; - FF_TX_D_3_5 : in std_logic; - FF_TX_D_3_6 : in std_logic; - FF_TX_D_3_7 : in std_logic; - FF_TX_D_3_8 : in std_logic; - FF_TX_D_3_9 : in std_logic; - FF_TX_D_3_10 : in std_logic; - FF_TX_D_3_11 : in std_logic; - FF_TX_D_3_12 : in std_logic; - FF_TX_D_3_13 : in std_logic; - FF_TX_D_3_14 : in std_logic; - FF_TX_D_3_15 : in std_logic; - FF_TX_D_3_16 : in std_logic; - FF_TX_D_3_17 : in std_logic; - FF_TX_D_3_18 : in std_logic; - FF_TX_D_3_19 : in std_logic; - FF_TX_D_3_20 : in std_logic; - FF_TX_D_3_21 : in std_logic; - FF_TX_D_3_22 : in std_logic; - FF_TX_D_3_23 : in std_logic; - FF_TXI_CLK_0 : in std_logic; - FF_TXI_CLK_1 : in std_logic; - FF_TXI_CLK_2 : in std_logic; - FF_TXI_CLK_3 : in std_logic; - FFC_CK_CORE_RX_0 : in std_logic; - FFC_CK_CORE_RX_1 : in std_logic; - FFC_CK_CORE_RX_2 : in std_logic; - FFC_CK_CORE_RX_3 : in std_logic; - FFC_CK_CORE_TX : in std_logic; - FFC_EI_EN_0 : in std_logic; - FFC_EI_EN_1 : in std_logic; - FFC_EI_EN_2 : in std_logic; - FFC_EI_EN_3 : in std_logic; - FFC_ENABLE_CGALIGN_0 : in std_logic; - FFC_ENABLE_CGALIGN_1 : in std_logic; - FFC_ENABLE_CGALIGN_2 : in std_logic; - FFC_ENABLE_CGALIGN_3 : in std_logic; - FFC_FB_LOOPBACK_0 : in std_logic; - FFC_FB_LOOPBACK_1 : in std_logic; - FFC_FB_LOOPBACK_2 : in std_logic; - FFC_FB_LOOPBACK_3 : in std_logic; - FFC_LANE_RX_RST_0 : in std_logic; - FFC_LANE_RX_RST_1 : in std_logic; - FFC_LANE_RX_RST_2 : in std_logic; - FFC_LANE_RX_RST_3 : in std_logic; - FFC_LANE_TX_RST_0 : in std_logic; - FFC_LANE_TX_RST_1 : in std_logic; - FFC_LANE_TX_RST_2 : in std_logic; - FFC_LANE_TX_RST_3 : in std_logic; - FFC_MACRO_RST : in std_logic; - FFC_PCI_DET_EN_0 : in std_logic; - FFC_PCI_DET_EN_1 : in std_logic; - FFC_PCI_DET_EN_2 : in std_logic; - FFC_PCI_DET_EN_3 : in std_logic; - FFC_PCIE_CT_0 : in std_logic; - FFC_PCIE_CT_1 : in std_logic; - FFC_PCIE_CT_2 : in std_logic; - FFC_PCIE_CT_3 : in std_logic; - FFC_PFIFO_CLR_0 : in std_logic; - FFC_PFIFO_CLR_1 : in std_logic; - FFC_PFIFO_CLR_2 : in std_logic; - FFC_PFIFO_CLR_3 : in std_logic; - FFC_QUAD_RST : in std_logic; - FFC_RRST_0 : in std_logic; - FFC_RRST_1 : in std_logic; - FFC_RRST_2 : in std_logic; - FFC_RRST_3 : in std_logic; - FFC_RXPWDNB_0 : in std_logic; - FFC_RXPWDNB_1 : in std_logic; - FFC_RXPWDNB_2 : in std_logic; - FFC_RXPWDNB_3 : in std_logic; - FFC_SB_INV_RX_0 : in std_logic; - FFC_SB_INV_RX_1 : in std_logic; - FFC_SB_INV_RX_2 : in std_logic; - FFC_SB_INV_RX_3 : in std_logic; - FFC_SB_PFIFO_LP_0 : in std_logic; - FFC_SB_PFIFO_LP_1 : in std_logic; - FFC_SB_PFIFO_LP_2 : in std_logic; - FFC_SB_PFIFO_LP_3 : in std_logic; - FFC_SIGNAL_DETECT_0 : in std_logic; - FFC_SIGNAL_DETECT_1 : in std_logic; - FFC_SIGNAL_DETECT_2 : in std_logic; - FFC_SIGNAL_DETECT_3 : in std_logic; - FFC_SYNC_TOGGLE : in std_logic; - FFC_TRST : in std_logic; - FFC_TXPWDNB_0 : in std_logic; - FFC_TXPWDNB_1 : in std_logic; - FFC_TXPWDNB_2 : in std_logic; - FFC_TXPWDNB_3 : in std_logic; - FFC_RATE_MODE_RX_0 : in std_logic; - FFC_RATE_MODE_RX_1 : in std_logic; - FFC_RATE_MODE_RX_2 : in std_logic; - FFC_RATE_MODE_RX_3 : in std_logic; - FFC_RATE_MODE_TX_0 : in std_logic; - FFC_RATE_MODE_TX_1 : in std_logic; - FFC_RATE_MODE_TX_2 : in std_logic; - FFC_RATE_MODE_TX_3 : in std_logic; - FFC_DIV11_MODE_RX_0 : in std_logic; - FFC_DIV11_MODE_RX_1 : in std_logic; - FFC_DIV11_MODE_RX_2 : in std_logic; - FFC_DIV11_MODE_RX_3 : in std_logic; - FFC_DIV11_MODE_TX_0 : in std_logic; - FFC_DIV11_MODE_TX_1 : in std_logic; - FFC_DIV11_MODE_TX_2 : in std_logic; - FFC_DIV11_MODE_TX_3 : in std_logic; - LDR_CORE2TX_0 : in std_logic; - LDR_CORE2TX_1 : in std_logic; - LDR_CORE2TX_2 : in std_logic; - LDR_CORE2TX_3 : in std_logic; - FFC_LDR_CORE2TX_EN_0 : in std_logic; - FFC_LDR_CORE2TX_EN_1 : in std_logic; - FFC_LDR_CORE2TX_EN_2 : in std_logic; - FFC_LDR_CORE2TX_EN_3 : in std_logic; - PCIE_POWERDOWN_0_0 : in std_logic; - PCIE_POWERDOWN_0_1 : in std_logic; - PCIE_POWERDOWN_1_0 : in std_logic; - PCIE_POWERDOWN_1_1 : in std_logic; - PCIE_POWERDOWN_2_0 : in std_logic; - PCIE_POWERDOWN_2_1 : in std_logic; - PCIE_POWERDOWN_3_0 : in std_logic; - PCIE_POWERDOWN_3_1 : in std_logic; - PCIE_RXPOLARITY_0 : in std_logic; - PCIE_RXPOLARITY_1 : in std_logic; - PCIE_RXPOLARITY_2 : in std_logic; - PCIE_RXPOLARITY_3 : in std_logic; - PCIE_TXCOMPLIANCE_0 : in std_logic; - PCIE_TXCOMPLIANCE_1 : in std_logic; - PCIE_TXCOMPLIANCE_2 : in std_logic; - PCIE_TXCOMPLIANCE_3 : in std_logic; - PCIE_TXDETRX_PR2TLB_0 : in std_logic; - PCIE_TXDETRX_PR2TLB_1 : in std_logic; - PCIE_TXDETRX_PR2TLB_2 : in std_logic; - PCIE_TXDETRX_PR2TLB_3 : in std_logic; - SCIADDR0 : in std_logic; - SCIADDR1 : in std_logic; - SCIADDR2 : in std_logic; - SCIADDR3 : in std_logic; - SCIADDR4 : in std_logic; - SCIADDR5 : in std_logic; - SCIENAUX : in std_logic; - SCIENCH0 : in std_logic; - SCIENCH1 : in std_logic; - SCIENCH2 : in std_logic; - SCIENCH3 : in std_logic; - SCIRD : in std_logic; - SCISELAUX : in std_logic; - SCISELCH0 : in std_logic; - SCISELCH1 : in std_logic; - SCISELCH2 : in std_logic; - SCISELCH3 : in std_logic; - SCIWDATA0 : in std_logic; - SCIWDATA1 : in std_logic; - SCIWDATA2 : in std_logic; - SCIWDATA3 : in std_logic; - SCIWDATA4 : in std_logic; - SCIWDATA5 : in std_logic; - SCIWDATA6 : in std_logic; - SCIWDATA7 : in std_logic; - SCIWSTN : in std_logic; - REFCLK_FROM_NQ : in std_logic; - HDOUTN0 : out std_logic; - HDOUTN1 : out std_logic; - HDOUTN2 : out std_logic; - HDOUTN3 : out std_logic; - HDOUTP0 : out std_logic; - HDOUTP1 : out std_logic; - HDOUTP2 : out std_logic; - HDOUTP3 : out std_logic; - COUT0 : out std_logic; - COUT1 : out std_logic; - COUT2 : out std_logic; - COUT3 : out std_logic; - COUT4 : out std_logic; - COUT5 : out std_logic; - COUT6 : out std_logic; - COUT7 : out std_logic; - COUT8 : out std_logic; - COUT9 : out std_logic; - COUT10 : out std_logic; - COUT11 : out std_logic; - COUT12 : out std_logic; - COUT13 : out std_logic; - COUT14 : out std_logic; - COUT15 : out std_logic; - COUT16 : out std_logic; - COUT17 : out std_logic; - COUT18 : out std_logic; - COUT19 : out std_logic; - FF_RX_D_0_0 : out std_logic; - FF_RX_D_0_1 : out std_logic; - FF_RX_D_0_2 : out std_logic; - FF_RX_D_0_3 : out std_logic; - FF_RX_D_0_4 : out std_logic; - FF_RX_D_0_5 : out std_logic; - FF_RX_D_0_6 : out std_logic; - FF_RX_D_0_7 : out std_logic; - FF_RX_D_0_8 : out std_logic; - FF_RX_D_0_9 : out std_logic; - FF_RX_D_0_10 : out std_logic; - FF_RX_D_0_11 : out std_logic; - FF_RX_D_0_12 : out std_logic; - FF_RX_D_0_13 : out std_logic; - FF_RX_D_0_14 : out std_logic; - FF_RX_D_0_15 : out std_logic; - FF_RX_D_0_16 : out std_logic; - FF_RX_D_0_17 : out std_logic; - FF_RX_D_0_18 : out std_logic; - FF_RX_D_0_19 : out std_logic; - FF_RX_D_0_20 : out std_logic; - FF_RX_D_0_21 : out std_logic; - FF_RX_D_0_22 : out std_logic; - FF_RX_D_0_23 : out std_logic; - FF_RX_D_1_0 : out std_logic; - FF_RX_D_1_1 : out std_logic; - FF_RX_D_1_2 : out std_logic; - FF_RX_D_1_3 : out std_logic; - FF_RX_D_1_4 : out std_logic; - FF_RX_D_1_5 : out std_logic; - FF_RX_D_1_6 : out std_logic; - FF_RX_D_1_7 : out std_logic; - FF_RX_D_1_8 : out std_logic; - FF_RX_D_1_9 : out std_logic; - FF_RX_D_1_10 : out std_logic; - FF_RX_D_1_11 : out std_logic; - FF_RX_D_1_12 : out std_logic; - FF_RX_D_1_13 : out std_logic; - FF_RX_D_1_14 : out std_logic; - FF_RX_D_1_15 : out std_logic; - FF_RX_D_1_16 : out std_logic; - FF_RX_D_1_17 : out std_logic; - FF_RX_D_1_18 : out std_logic; - FF_RX_D_1_19 : out std_logic; - FF_RX_D_1_20 : out std_logic; - FF_RX_D_1_21 : out std_logic; - FF_RX_D_1_22 : out std_logic; - FF_RX_D_1_23 : out std_logic; - FF_RX_D_2_0 : out std_logic; - FF_RX_D_2_1 : out std_logic; - FF_RX_D_2_2 : out std_logic; - FF_RX_D_2_3 : out std_logic; - FF_RX_D_2_4 : out std_logic; - FF_RX_D_2_5 : out std_logic; - FF_RX_D_2_6 : out std_logic; - FF_RX_D_2_7 : out std_logic; - FF_RX_D_2_8 : out std_logic; - FF_RX_D_2_9 : out std_logic; - FF_RX_D_2_10 : out std_logic; - FF_RX_D_2_11 : out std_logic; - FF_RX_D_2_12 : out std_logic; - FF_RX_D_2_13 : out std_logic; - FF_RX_D_2_14 : out std_logic; - FF_RX_D_2_15 : out std_logic; - FF_RX_D_2_16 : out std_logic; - FF_RX_D_2_17 : out std_logic; - FF_RX_D_2_18 : out std_logic; - FF_RX_D_2_19 : out std_logic; - FF_RX_D_2_20 : out std_logic; - FF_RX_D_2_21 : out std_logic; - FF_RX_D_2_22 : out std_logic; - FF_RX_D_2_23 : out std_logic; - FF_RX_D_3_0 : out std_logic; - FF_RX_D_3_1 : out std_logic; - FF_RX_D_3_2 : out std_logic; - FF_RX_D_3_3 : out std_logic; - FF_RX_D_3_4 : out std_logic; - FF_RX_D_3_5 : out std_logic; - FF_RX_D_3_6 : out std_logic; - FF_RX_D_3_7 : out std_logic; - FF_RX_D_3_8 : out std_logic; - FF_RX_D_3_9 : out std_logic; - FF_RX_D_3_10 : out std_logic; - FF_RX_D_3_11 : out std_logic; - FF_RX_D_3_12 : out std_logic; - FF_RX_D_3_13 : out std_logic; - FF_RX_D_3_14 : out std_logic; - FF_RX_D_3_15 : out std_logic; - FF_RX_D_3_16 : out std_logic; - FF_RX_D_3_17 : out std_logic; - FF_RX_D_3_18 : out std_logic; - FF_RX_D_3_19 : out std_logic; - FF_RX_D_3_20 : out std_logic; - FF_RX_D_3_21 : out std_logic; - FF_RX_D_3_22 : out std_logic; - FF_RX_D_3_23 : out std_logic; - FF_RX_F_CLK_0 : out std_logic; - FF_RX_F_CLK_1 : out std_logic; - FF_RX_F_CLK_2 : out std_logic; - FF_RX_F_CLK_3 : out std_logic; - FF_RX_H_CLK_0 : out std_logic; - FF_RX_H_CLK_1 : out std_logic; - FF_RX_H_CLK_2 : out std_logic; - FF_RX_H_CLK_3 : out std_logic; - FF_TX_F_CLK_0 : out std_logic; - FF_TX_F_CLK_1 : out std_logic; - FF_TX_F_CLK_2 : out std_logic; - FF_TX_F_CLK_3 : out std_logic; - FF_TX_H_CLK_0 : out std_logic; - FF_TX_H_CLK_1 : out std_logic; - FF_TX_H_CLK_2 : out std_logic; - FF_TX_H_CLK_3 : out std_logic; - FFS_CC_OVERRUN_0 : out std_logic; - FFS_CC_OVERRUN_1 : out std_logic; - FFS_CC_OVERRUN_2 : out std_logic; - FFS_CC_OVERRUN_3 : out std_logic; - FFS_CC_UNDERRUN_0 : out std_logic; - FFS_CC_UNDERRUN_1 : out std_logic; - FFS_CC_UNDERRUN_2 : out std_logic; - FFS_CC_UNDERRUN_3 : out std_logic; - FFS_LS_SYNC_STATUS_0 : out std_logic; - FFS_LS_SYNC_STATUS_1 : out std_logic; - FFS_LS_SYNC_STATUS_2 : out std_logic; - FFS_LS_SYNC_STATUS_3 : out std_logic; - FFS_CDR_TRAIN_DONE_0 : out std_logic; - FFS_CDR_TRAIN_DONE_1 : out std_logic; - FFS_CDR_TRAIN_DONE_2 : out std_logic; - FFS_CDR_TRAIN_DONE_3 : out std_logic; - FFS_PCIE_CON_0 : out std_logic; - FFS_PCIE_CON_1 : out std_logic; - FFS_PCIE_CON_2 : out std_logic; - FFS_PCIE_CON_3 : out std_logic; - FFS_PCIE_DONE_0 : out std_logic; - FFS_PCIE_DONE_1 : out std_logic; - FFS_PCIE_DONE_2 : out std_logic; - FFS_PCIE_DONE_3 : out std_logic; - FFS_PLOL : out std_logic; - FFS_RLOL_0 : out std_logic; - FFS_RLOL_1 : out std_logic; - FFS_RLOL_2 : out std_logic; - FFS_RLOL_3 : out std_logic; - FFS_RLOS_HI_0 : out std_logic; - FFS_RLOS_HI_1 : out std_logic; - FFS_RLOS_HI_2 : out std_logic; - FFS_RLOS_HI_3 : out std_logic; - FFS_RLOS_LO_0 : out std_logic; - FFS_RLOS_LO_1 : out std_logic; - FFS_RLOS_LO_2 : out std_logic; - FFS_RLOS_LO_3 : out std_logic; - FFS_RXFBFIFO_ERROR_0 : out std_logic; - FFS_RXFBFIFO_ERROR_1 : out std_logic; - FFS_RXFBFIFO_ERROR_2 : out std_logic; - FFS_RXFBFIFO_ERROR_3 : out std_logic; - FFS_TXFBFIFO_ERROR_0 : out std_logic; - FFS_TXFBFIFO_ERROR_1 : out std_logic; - FFS_TXFBFIFO_ERROR_2 : out std_logic; - FFS_TXFBFIFO_ERROR_3 : out std_logic; - PCIE_PHYSTATUS_0 : out std_logic; - PCIE_PHYSTATUS_1 : out std_logic; - PCIE_PHYSTATUS_2 : out std_logic; - PCIE_PHYSTATUS_3 : out std_logic; - PCIE_RXVALID_0 : out std_logic; - PCIE_RXVALID_1 : out std_logic; - PCIE_RXVALID_2 : out std_logic; - PCIE_RXVALID_3 : out std_logic; - FFS_SKP_ADDED_0 : out std_logic; - FFS_SKP_ADDED_1 : out std_logic; - FFS_SKP_ADDED_2 : out std_logic; - FFS_SKP_ADDED_3 : out std_logic; - FFS_SKP_DELETED_0 : out std_logic; - FFS_SKP_DELETED_1 : out std_logic; - FFS_SKP_DELETED_2 : out std_logic; - FFS_SKP_DELETED_3 : out std_logic; - LDR_RX2CORE_0 : out std_logic; - LDR_RX2CORE_1 : out std_logic; - LDR_RX2CORE_2 : out std_logic; - LDR_RX2CORE_3 : out std_logic; - REFCK2CORE : out std_logic; - SCIINT : out std_logic; - SCIRDATA0 : out std_logic; - SCIRDATA1 : out std_logic; - SCIRDATA2 : out std_logic; - SCIRDATA3 : out std_logic; - SCIRDATA4 : out std_logic; - SCIRDATA5 : out std_logic; - SCIRDATA6 : out std_logic; - SCIRDATA7 : out std_logic; - REFCLK_TO_NQ : out std_logic -); -end component; - attribute CONFIG_FILE: string; - attribute CONFIG_FILE of PCSD_INST : label is USER_CONFIG_FILE; - attribute QUAD_MODE: string; - attribute QUAD_MODE of PCSD_INST : label is "SINGLE"; - attribute PLL_SRC: string; - attribute PLL_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute CH3_CDR_SRC: string; - attribute CH3_CDR_SRC of PCSD_INST : label is "REFCLK_CORE"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_0 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_1 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_2 of PCSD_INST : label is "250.000"; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_F_CLK_3 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_0 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_1 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_2 of PCSD_INST : label is "125.000"; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_RX_H_CLK_3 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_0 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_1 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_2 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_F_CLK_3 of PCSD_INST : label is "200"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_0 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_1 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_2 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3: string; - attribute FREQUENCY_PIN_FF_TX_H_CLK_3 of PCSD_INST : label is "100"; - attribute FREQUENCY_PIN_REFCK2CORE: string; - attribute FREQUENCY_PIN_REFCK2CORE of PCSD_INST : label is "200"; - attribute black_box_pad_pin: string; - attribute black_box_pad_pin of PCSD : component is "HDINP0, HDINN0, HDINP1, HDINN1, HDINP2, HDINN2, HDINP3, HDINN3, HDOUTP0, HDOUTN0, HDOUTP1, HDOUTN1, HDOUTP2, HDOUTN2, HDOUTP3, HDOUTN3, REFCLKP, REFCLKN"; - -signal refclk_from_nq : std_logic := '0'; -signal fpsc_vlo : std_logic := '0'; -signal fpsc_vhi : std_logic := '1'; -signal cin : std_logic_vector (11 downto 0) := "000000000000"; -signal cout : std_logic_vector (19 downto 0); -signal tx_full_clk_ch3_sig : std_logic; - -signal refclk2fpga_sig : std_logic; -signal tx_pll_lol_qd_sig : std_logic; -signal rx_los_low_ch0_sig : std_logic; -signal rx_los_low_ch1_sig : std_logic; -signal rx_los_low_ch2_sig : std_logic; -signal rx_los_low_ch3_sig : std_logic; -signal rx_cdr_lol_ch0_sig : std_logic; -signal rx_cdr_lol_ch1_sig : std_logic; -signal rx_cdr_lol_ch2_sig : std_logic; -signal rx_cdr_lol_ch3_sig : std_logic; - - - - - -begin - -vlo_inst : VLO port map(Z => fpsc_vlo); -vhi_inst : VHI port map(Z => fpsc_vhi); - - refclk2fpga <= refclk2fpga_sig; - rx_los_low_ch3_s <= rx_los_low_ch3_sig; - rx_cdr_lol_ch3_s <= rx_cdr_lol_ch3_sig; - tx_pll_lol_qd_s <= tx_pll_lol_qd_sig; - tx_full_clk_ch3 <= tx_full_clk_ch3_sig; - --- pcs_quad instance -PCSD_INST : PCSD ---synopsys translate_off - generic map (CONFIG_FILE => USER_CONFIG_FILE, - QUAD_MODE => "SINGLE", - CH3_CDR_SRC => "REFCLK_CORE", - PLL_SRC => "REFCLK_CORE" - ) ---synopsys translate_on -port map ( - REFCLKP => fpsc_vlo, - REFCLKN => fpsc_vlo, - ------ CH0 ----- - HDOUTP0 => open, - HDOUTN0 => open, - HDINP0 => fpsc_vlo, - HDINN0 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_0 => fpsc_vlo, - PCIE_TXCOMPLIANCE_0 => fpsc_vlo, - PCIE_RXPOLARITY_0 => fpsc_vlo, - PCIE_POWERDOWN_0_0 => fpsc_vlo, - PCIE_POWERDOWN_0_1 => fpsc_vlo, - PCIE_RXVALID_0 => open, - PCIE_PHYSTATUS_0 => open, - SCISELCH0 => fpsc_vlo, - SCIENCH0 => fpsc_vlo, - FF_RXI_CLK_0 => fpsc_vlo, - FF_TXI_CLK_0 => fpsc_vlo, - FF_EBRD_CLK_0 => fpsc_vlo, - FF_RX_F_CLK_0 => open, - FF_RX_H_CLK_0 => open, - FF_TX_F_CLK_0 => open, - FF_TX_H_CLK_0 => open, - FFC_CK_CORE_RX_0 => fpsc_vlo, - FF_TX_D_0_0 => fpsc_vlo, - FF_TX_D_0_1 => fpsc_vlo, - FF_TX_D_0_2 => fpsc_vlo, - FF_TX_D_0_3 => fpsc_vlo, - FF_TX_D_0_4 => fpsc_vlo, - FF_TX_D_0_5 => fpsc_vlo, - FF_TX_D_0_6 => fpsc_vlo, - FF_TX_D_0_7 => fpsc_vlo, - FF_TX_D_0_8 => fpsc_vlo, - FF_TX_D_0_9 => fpsc_vlo, - FF_TX_D_0_10 => fpsc_vlo, - FF_TX_D_0_11 => fpsc_vlo, - FF_TX_D_0_12 => fpsc_vlo, - FF_TX_D_0_13 => fpsc_vlo, - FF_TX_D_0_14 => fpsc_vlo, - FF_TX_D_0_15 => fpsc_vlo, - FF_TX_D_0_16 => fpsc_vlo, - FF_TX_D_0_17 => fpsc_vlo, - FF_TX_D_0_18 => fpsc_vlo, - FF_TX_D_0_19 => fpsc_vlo, - FF_TX_D_0_20 => fpsc_vlo, - FF_TX_D_0_21 => fpsc_vlo, - FF_TX_D_0_22 => fpsc_vlo, - FF_TX_D_0_23 => fpsc_vlo, - FF_RX_D_0_0 => open, - FF_RX_D_0_1 => open, - FF_RX_D_0_2 => open, - FF_RX_D_0_3 => open, - FF_RX_D_0_4 => open, - FF_RX_D_0_5 => open, - FF_RX_D_0_6 => open, - FF_RX_D_0_7 => open, - FF_RX_D_0_8 => open, - FF_RX_D_0_9 => open, - FF_RX_D_0_10 => open, - FF_RX_D_0_11 => open, - FF_RX_D_0_12 => open, - FF_RX_D_0_13 => open, - FF_RX_D_0_14 => open, - FF_RX_D_0_15 => open, - FF_RX_D_0_16 => open, - FF_RX_D_0_17 => open, - FF_RX_D_0_18 => open, - FF_RX_D_0_19 => open, - FF_RX_D_0_20 => open, - FF_RX_D_0_21 => open, - FF_RX_D_0_22 => open, - FF_RX_D_0_23 => open, - - FFC_RRST_0 => fpsc_vlo, - FFC_SIGNAL_DETECT_0 => fpsc_vlo, - FFC_SB_PFIFO_LP_0 => fpsc_vlo, - FFC_PFIFO_CLR_0 => fpsc_vlo, - FFC_SB_INV_RX_0 => fpsc_vlo, - FFC_PCIE_CT_0 => fpsc_vlo, - FFC_PCI_DET_EN_0 => fpsc_vlo, - FFC_FB_LOOPBACK_0 => fpsc_vlo, - FFC_ENABLE_CGALIGN_0 => fpsc_vlo, - FFC_EI_EN_0 => fpsc_vlo, - FFC_LANE_TX_RST_0 => fpsc_vlo, - FFC_TXPWDNB_0 => fpsc_vlo, - FFC_LANE_RX_RST_0 => fpsc_vlo, - FFC_RXPWDNB_0 => fpsc_vlo, - FFS_RLOS_LO_0 => open, - FFS_RLOS_HI_0 => open, - FFS_PCIE_CON_0 => open, - FFS_PCIE_DONE_0 => open, - FFS_LS_SYNC_STATUS_0 => open, - FFS_CC_OVERRUN_0 => open, - FFS_CC_UNDERRUN_0 => open, - FFS_SKP_ADDED_0 => open, - FFS_SKP_DELETED_0 => open, - FFS_RLOL_0 => open, - FFS_RXFBFIFO_ERROR_0 => open, - FFS_TXFBFIFO_ERROR_0 => open, - LDR_CORE2TX_0 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_0 => fpsc_vlo, - LDR_RX2CORE_0 => open, - FFS_CDR_TRAIN_DONE_0 => open, - FFC_DIV11_MODE_TX_0 => fpsc_vlo, - FFC_RATE_MODE_TX_0 => fpsc_vlo, - FFC_DIV11_MODE_RX_0 => fpsc_vlo, - FFC_RATE_MODE_RX_0 => fpsc_vlo, - ------ CH1 ----- - HDOUTP1 => open, - HDOUTN1 => open, - HDINP1 => fpsc_vlo, - HDINN1 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_1 => fpsc_vlo, - PCIE_TXCOMPLIANCE_1 => fpsc_vlo, - PCIE_RXPOLARITY_1 => fpsc_vlo, - PCIE_POWERDOWN_1_0 => fpsc_vlo, - PCIE_POWERDOWN_1_1 => fpsc_vlo, - PCIE_RXVALID_1 => open, - PCIE_PHYSTATUS_1 => open, - SCISELCH1 => fpsc_vlo, - SCIENCH1 => fpsc_vlo, - FF_RXI_CLK_1 => fpsc_vlo, - FF_TXI_CLK_1 => fpsc_vlo, - FF_EBRD_CLK_1 => fpsc_vlo, - FF_RX_F_CLK_1 => open, - FF_RX_H_CLK_1 => open, - FF_TX_F_CLK_1 => open, - FF_TX_H_CLK_1 => open, - FFC_CK_CORE_RX_1 => fpsc_vlo, - FF_TX_D_1_0 => fpsc_vlo, - FF_TX_D_1_1 => fpsc_vlo, - FF_TX_D_1_2 => fpsc_vlo, - FF_TX_D_1_3 => fpsc_vlo, - FF_TX_D_1_4 => fpsc_vlo, - FF_TX_D_1_5 => fpsc_vlo, - FF_TX_D_1_6 => fpsc_vlo, - FF_TX_D_1_7 => fpsc_vlo, - FF_TX_D_1_8 => fpsc_vlo, - FF_TX_D_1_9 => fpsc_vlo, - FF_TX_D_1_10 => fpsc_vlo, - FF_TX_D_1_11 => fpsc_vlo, - FF_TX_D_1_12 => fpsc_vlo, - FF_TX_D_1_13 => fpsc_vlo, - FF_TX_D_1_14 => fpsc_vlo, - FF_TX_D_1_15 => fpsc_vlo, - FF_TX_D_1_16 => fpsc_vlo, - FF_TX_D_1_17 => fpsc_vlo, - FF_TX_D_1_18 => fpsc_vlo, - FF_TX_D_1_19 => fpsc_vlo, - FF_TX_D_1_20 => fpsc_vlo, - FF_TX_D_1_21 => fpsc_vlo, - FF_TX_D_1_22 => fpsc_vlo, - FF_TX_D_1_23 => fpsc_vlo, - FF_RX_D_1_0 => open, - FF_RX_D_1_1 => open, - FF_RX_D_1_2 => open, - FF_RX_D_1_3 => open, - FF_RX_D_1_4 => open, - FF_RX_D_1_5 => open, - FF_RX_D_1_6 => open, - FF_RX_D_1_7 => open, - FF_RX_D_1_8 => open, - FF_RX_D_1_9 => open, - FF_RX_D_1_10 => open, - FF_RX_D_1_11 => open, - FF_RX_D_1_12 => open, - FF_RX_D_1_13 => open, - FF_RX_D_1_14 => open, - FF_RX_D_1_15 => open, - FF_RX_D_1_16 => open, - FF_RX_D_1_17 => open, - FF_RX_D_1_18 => open, - FF_RX_D_1_19 => open, - FF_RX_D_1_20 => open, - FF_RX_D_1_21 => open, - FF_RX_D_1_22 => open, - FF_RX_D_1_23 => open, - - FFC_RRST_1 => fpsc_vlo, - FFC_SIGNAL_DETECT_1 => fpsc_vlo, - FFC_SB_PFIFO_LP_1 => fpsc_vlo, - FFC_PFIFO_CLR_1 => fpsc_vlo, - FFC_SB_INV_RX_1 => fpsc_vlo, - FFC_PCIE_CT_1 => fpsc_vlo, - FFC_PCI_DET_EN_1 => fpsc_vlo, - FFC_FB_LOOPBACK_1 => fpsc_vlo, - FFC_ENABLE_CGALIGN_1 => fpsc_vlo, - FFC_EI_EN_1 => fpsc_vlo, - FFC_LANE_TX_RST_1 => fpsc_vlo, - FFC_TXPWDNB_1 => fpsc_vlo, - FFC_LANE_RX_RST_1 => fpsc_vlo, - FFC_RXPWDNB_1 => fpsc_vlo, - FFS_RLOS_LO_1 => open, - FFS_RLOS_HI_1 => open, - FFS_PCIE_CON_1 => open, - FFS_PCIE_DONE_1 => open, - FFS_LS_SYNC_STATUS_1 => open, - FFS_CC_OVERRUN_1 => open, - FFS_CC_UNDERRUN_1 => open, - FFS_SKP_ADDED_1 => open, - FFS_SKP_DELETED_1 => open, - FFS_RLOL_1 => open, - FFS_RXFBFIFO_ERROR_1 => open, - FFS_TXFBFIFO_ERROR_1 => open, - LDR_CORE2TX_1 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_1 => fpsc_vlo, - LDR_RX2CORE_1 => open, - FFS_CDR_TRAIN_DONE_1 => open, - FFC_DIV11_MODE_TX_1 => fpsc_vlo, - FFC_RATE_MODE_TX_1 => fpsc_vlo, - FFC_DIV11_MODE_RX_1 => fpsc_vlo, - FFC_RATE_MODE_RX_1 => fpsc_vlo, - ------ CH2 ----- - HDOUTP2 => open, - HDOUTN2 => open, - HDINP2 => fpsc_vlo, - HDINN2 => fpsc_vlo, - PCIE_TXDETRX_PR2TLB_2 => fpsc_vlo, - PCIE_TXCOMPLIANCE_2 => fpsc_vlo, - PCIE_RXPOLARITY_2 => fpsc_vlo, - PCIE_POWERDOWN_2_0 => fpsc_vlo, - PCIE_POWERDOWN_2_1 => fpsc_vlo, - PCIE_RXVALID_2 => open, - PCIE_PHYSTATUS_2 => open, - SCISELCH2 => fpsc_vlo, - SCIENCH2 => fpsc_vlo, - FF_RXI_CLK_2 => fpsc_vlo, - FF_TXI_CLK_2 => fpsc_vlo, - FF_EBRD_CLK_2 => fpsc_vlo, - FF_RX_F_CLK_2 => open, - FF_RX_H_CLK_2 => open, - FF_TX_F_CLK_2 => open, - FF_TX_H_CLK_2 => open, - FFC_CK_CORE_RX_2 => fpsc_vlo, - FF_TX_D_2_0 => fpsc_vlo, - FF_TX_D_2_1 => fpsc_vlo, - FF_TX_D_2_2 => fpsc_vlo, - FF_TX_D_2_3 => fpsc_vlo, - FF_TX_D_2_4 => fpsc_vlo, - FF_TX_D_2_5 => fpsc_vlo, - FF_TX_D_2_6 => fpsc_vlo, - FF_TX_D_2_7 => fpsc_vlo, - FF_TX_D_2_8 => fpsc_vlo, - FF_TX_D_2_9 => fpsc_vlo, - FF_TX_D_2_10 => fpsc_vlo, - FF_TX_D_2_11 => fpsc_vlo, - FF_TX_D_2_12 => fpsc_vlo, - FF_TX_D_2_13 => fpsc_vlo, - FF_TX_D_2_14 => fpsc_vlo, - FF_TX_D_2_15 => fpsc_vlo, - FF_TX_D_2_16 => fpsc_vlo, - FF_TX_D_2_17 => fpsc_vlo, - FF_TX_D_2_18 => fpsc_vlo, - FF_TX_D_2_19 => fpsc_vlo, - FF_TX_D_2_20 => fpsc_vlo, - FF_TX_D_2_21 => fpsc_vlo, - FF_TX_D_2_22 => fpsc_vlo, - FF_TX_D_2_23 => fpsc_vlo, - FF_RX_D_2_0 => open, - FF_RX_D_2_1 => open, - FF_RX_D_2_2 => open, - FF_RX_D_2_3 => open, - FF_RX_D_2_4 => open, - FF_RX_D_2_5 => open, - FF_RX_D_2_6 => open, - FF_RX_D_2_7 => open, - FF_RX_D_2_8 => open, - FF_RX_D_2_9 => open, - FF_RX_D_2_10 => open, - FF_RX_D_2_11 => open, - FF_RX_D_2_12 => open, - FF_RX_D_2_13 => open, - FF_RX_D_2_14 => open, - FF_RX_D_2_15 => open, - FF_RX_D_2_16 => open, - FF_RX_D_2_17 => open, - FF_RX_D_2_18 => open, - FF_RX_D_2_19 => open, - FF_RX_D_2_20 => open, - FF_RX_D_2_21 => open, - FF_RX_D_2_22 => open, - FF_RX_D_2_23 => open, - - FFC_RRST_2 => fpsc_vlo, - FFC_SIGNAL_DETECT_2 => fpsc_vlo, - FFC_SB_PFIFO_LP_2 => fpsc_vlo, - FFC_PFIFO_CLR_2 => fpsc_vlo, - FFC_SB_INV_RX_2 => fpsc_vlo, - FFC_PCIE_CT_2 => fpsc_vlo, - FFC_PCI_DET_EN_2 => fpsc_vlo, - FFC_FB_LOOPBACK_2 => fpsc_vlo, - FFC_ENABLE_CGALIGN_2 => fpsc_vlo, - FFC_EI_EN_2 => fpsc_vlo, - FFC_LANE_TX_RST_2 => fpsc_vlo, - FFC_TXPWDNB_2 => fpsc_vlo, - FFC_LANE_RX_RST_2 => fpsc_vlo, - FFC_RXPWDNB_2 => fpsc_vlo, - FFS_RLOS_LO_2 => open, - FFS_RLOS_HI_2 => open, - FFS_PCIE_CON_2 => open, - FFS_PCIE_DONE_2 => open, - FFS_LS_SYNC_STATUS_2 => open, - FFS_CC_OVERRUN_2 => open, - FFS_CC_UNDERRUN_2 => open, - FFS_SKP_ADDED_2 => open, - FFS_SKP_DELETED_2 => open, - FFS_RLOL_2 => open, - FFS_RXFBFIFO_ERROR_2 => open, - FFS_TXFBFIFO_ERROR_2 => open, - LDR_CORE2TX_2 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_2 => fpsc_vlo, - LDR_RX2CORE_2 => open, - FFS_CDR_TRAIN_DONE_2 => open, - FFC_DIV11_MODE_TX_2 => fpsc_vlo, - FFC_RATE_MODE_TX_2 => fpsc_vlo, - FFC_DIV11_MODE_RX_2 => fpsc_vlo, - FFC_RATE_MODE_RX_2 => fpsc_vlo, - ------ CH3 ----- - HDOUTP3 => hdoutp_ch3, - HDOUTN3 => hdoutn_ch3, - HDINP3 => hdinp_ch3, - HDINN3 => hdinn_ch3, - PCIE_TXDETRX_PR2TLB_3 => fpsc_vlo, - PCIE_TXCOMPLIANCE_3 => fpsc_vlo, - PCIE_RXPOLARITY_3 => fpsc_vlo, - PCIE_POWERDOWN_3_0 => fpsc_vlo, - PCIE_POWERDOWN_3_1 => fpsc_vlo, - PCIE_RXVALID_3 => open, - PCIE_PHYSTATUS_3 => open, - SCISELCH3 => sci_sel_ch3, - SCIENCH3 => fpsc_vhi, - FF_RXI_CLK_3 => fpsc_vlo, - FF_TXI_CLK_3 => txiclk_ch3, - FF_EBRD_CLK_3 => fpsc_vlo, - FF_RX_F_CLK_3 => rx_full_clk_ch3, - FF_RX_H_CLK_3 => rx_half_clk_ch3, - FF_TX_F_CLK_3 => tx_full_clk_ch3_sig, - FF_TX_H_CLK_3 => tx_half_clk_ch3, - FFC_CK_CORE_RX_3 => fpga_rxrefclk_ch3, - FF_TX_D_3_0 => txdata_ch3(0), - FF_TX_D_3_1 => txdata_ch3(1), - FF_TX_D_3_2 => txdata_ch3(2), - FF_TX_D_3_3 => txdata_ch3(3), - FF_TX_D_3_4 => txdata_ch3(4), - FF_TX_D_3_5 => txdata_ch3(5), - FF_TX_D_3_6 => txdata_ch3(6), - FF_TX_D_3_7 => txdata_ch3(7), - FF_TX_D_3_8 => tx_k_ch3, - FF_TX_D_3_9 => tx_force_disp_ch3, - FF_TX_D_3_10 => tx_disp_sel_ch3, - FF_TX_D_3_11 => fpsc_vlo, - FF_TX_D_3_12 => fpsc_vlo, - FF_TX_D_3_13 => fpsc_vlo, - FF_TX_D_3_14 => fpsc_vlo, - FF_TX_D_3_15 => fpsc_vlo, - FF_TX_D_3_16 => fpsc_vlo, - FF_TX_D_3_17 => fpsc_vlo, - FF_TX_D_3_18 => fpsc_vlo, - FF_TX_D_3_19 => fpsc_vlo, - FF_TX_D_3_20 => fpsc_vlo, - FF_TX_D_3_21 => fpsc_vlo, - FF_TX_D_3_22 => fpsc_vlo, - FF_TX_D_3_23 => fpsc_vlo, - FF_RX_D_3_0 => rxdata_ch3(0), - FF_RX_D_3_1 => rxdata_ch3(1), - FF_RX_D_3_2 => rxdata_ch3(2), - FF_RX_D_3_3 => rxdata_ch3(3), - FF_RX_D_3_4 => rxdata_ch3(4), - FF_RX_D_3_5 => rxdata_ch3(5), - FF_RX_D_3_6 => rxdata_ch3(6), - FF_RX_D_3_7 => rxdata_ch3(7), - FF_RX_D_3_8 => rx_k_ch3, - FF_RX_D_3_9 => rx_disp_err_ch3, - FF_RX_D_3_10 => rx_cv_err_ch3, - FF_RX_D_3_11 => open, - FF_RX_D_3_12 => open, - FF_RX_D_3_13 => open, - FF_RX_D_3_14 => open, - FF_RX_D_3_15 => open, - FF_RX_D_3_16 => open, - FF_RX_D_3_17 => open, - FF_RX_D_3_18 => open, - FF_RX_D_3_19 => open, - FF_RX_D_3_20 => open, - FF_RX_D_3_21 => open, - FF_RX_D_3_22 => open, - FF_RX_D_3_23 => open, - - FFC_RRST_3 => rx_serdes_rst_ch3_c, - FFC_SIGNAL_DETECT_3 => fpsc_vlo, - FFC_SB_PFIFO_LP_3 => sb_felb_ch3_c, - FFC_PFIFO_CLR_3 => sb_felb_rst_ch3_c, - FFC_SB_INV_RX_3 => fpsc_vlo, - FFC_PCIE_CT_3 => fpsc_vlo, - FFC_PCI_DET_EN_3 => fpsc_vlo, - FFC_FB_LOOPBACK_3 => fpsc_vlo, - FFC_ENABLE_CGALIGN_3 => fpsc_vlo, - FFC_EI_EN_3 => fpsc_vlo, - FFC_LANE_TX_RST_3 => tx_pcs_rst_ch3_c, - FFC_TXPWDNB_3 => tx_pwrup_ch3_c, - FFC_LANE_RX_RST_3 => rx_pcs_rst_ch3_c, - FFC_RXPWDNB_3 => rx_pwrup_ch3_c, - FFS_RLOS_LO_3 => rx_los_low_ch3_sig, - FFS_RLOS_HI_3 => open, - FFS_PCIE_CON_3 => open, - FFS_PCIE_DONE_3 => open, - FFS_LS_SYNC_STATUS_3 => lsm_status_ch3_s, - FFS_CC_OVERRUN_3 => open, - FFS_CC_UNDERRUN_3 => open, - FFS_SKP_ADDED_3 => open, - FFS_SKP_DELETED_3 => open, - FFS_RLOL_3 => rx_cdr_lol_ch3_sig, - FFS_RXFBFIFO_ERROR_3 => open, - FFS_TXFBFIFO_ERROR_3 => open, - LDR_CORE2TX_3 => fpsc_vlo, - FFC_LDR_CORE2TX_EN_3 => fpsc_vlo, - LDR_RX2CORE_3 => open, - FFS_CDR_TRAIN_DONE_3 => open, - FFC_DIV11_MODE_TX_3 => fpsc_vlo, - FFC_RATE_MODE_TX_3 => tx_div2_mode_ch3_c, - FFC_DIV11_MODE_RX_3 => fpsc_vlo, - FFC_RATE_MODE_RX_3 => rx_div2_mode_ch3_c, - ------ Auxilliary ---- - SCIWDATA7 => sci_wrdata(7), - SCIWDATA6 => sci_wrdata(6), - SCIWDATA5 => sci_wrdata(5), - SCIWDATA4 => sci_wrdata(4), - SCIWDATA3 => sci_wrdata(3), - SCIWDATA2 => sci_wrdata(2), - SCIWDATA1 => sci_wrdata(1), - SCIWDATA0 => sci_wrdata(0), - SCIADDR5 => sci_addr(5), - SCIADDR4 => sci_addr(4), - SCIADDR3 => sci_addr(3), - SCIADDR2 => sci_addr(2), - SCIADDR1 => sci_addr(1), - SCIADDR0 => sci_addr(0), - SCIRDATA7 => sci_rddata(7), - SCIRDATA6 => sci_rddata(6), - SCIRDATA5 => sci_rddata(5), - SCIRDATA4 => sci_rddata(4), - SCIRDATA3 => sci_rddata(3), - SCIRDATA2 => sci_rddata(2), - SCIRDATA1 => sci_rddata(1), - SCIRDATA0 => sci_rddata(0), - SCIENAUX => fpsc_vhi, - SCISELAUX => sci_sel_quad, - SCIRD => sci_rd, - SCIWSTN => sci_wrn, - CYAWSTN => fpsc_vlo, - SCIINT => open, - FFC_CK_CORE_TX => fpga_txrefclk, - FFC_MACRO_RST => serdes_rst_qd_c, - FFC_QUAD_RST => rst_qd_c, - FFC_TRST => tx_serdes_rst_c, - FFS_PLOL => tx_pll_lol_qd_sig, - FFC_SYNC_TOGGLE => fpsc_vlo, - REFCK2CORE => refclk2fpga_sig, - CIN0 => fpsc_vlo, - CIN1 => fpsc_vlo, - CIN2 => fpsc_vlo, - CIN3 => fpsc_vlo, - CIN4 => fpsc_vlo, - CIN5 => fpsc_vlo, - CIN6 => fpsc_vlo, - CIN7 => fpsc_vlo, - CIN8 => fpsc_vlo, - CIN9 => fpsc_vlo, - CIN10 => fpsc_vlo, - CIN11 => fpsc_vlo, - COUT0 => open, - COUT1 => open, - COUT2 => open, - COUT3 => open, - COUT4 => open, - COUT5 => open, - COUT6 => open, - COUT7 => open, - COUT8 => open, - COUT9 => open, - COUT10 => open, - COUT11 => open, - COUT12 => open, - COUT13 => open, - COUT14 => open, - COUT15 => open, - COUT16 => open, - COUT17 => open, - COUT18 => open, - COUT19 => open, - REFCLK_FROM_NQ => refclk_from_nq, - REFCLK_TO_NQ => open); - - - - ---synopsys translate_off -file_read : PROCESS -VARIABLE open_status : file_open_status; -FILE config : text; -BEGIN - file_open (open_status, config, USER_CONFIG_FILE, read_mode); - IF (open_status = name_error) THEN - report "Auto configuration file for PCS module not found. PCS internal configuration registers will not be initialized correctly during simulation!" - severity ERROR; - END IF; - wait; -END PROCESS; ---synopsys translate_on -end serdes_sync_hub_upstream_arch ; diff --git a/code/ip/serdes_sync_source_downstream.txt b/code/ip/serdes_sync_source_downstream.txt deleted file mode 100644 index 400122b..0000000 --- a/code/ip/serdes_sync_source_downstream.txt +++ /dev/null @@ -1,58 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH0_PROTOCOL "G8B10B" -CH0_MODE "RXTX" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "DISABLED" -CH0_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH0_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200 -CH0_RX_DATA_RATE "FULL" -CH0_TX_DATA_RATE "FULL" -CH0_TX_DATA_WIDTH "8" -CH0_RX_DATA_WIDTH "8" -CH0_TX_FIFO "DISABLED" -CH0_RX_FIFO "ENABLED" -CH0_TDRV "0" -#CH0_TX_FICLK_RATE 200 -#CH0_RXREFCLK_RATE "200" -#CH0_RX_FICLK_RATE 200 -CH0_TX_PRE "DISABLED" -CH0_RTERM_TX "50" -CH0_RX_EQ "DISABLED" -CH0_RTERM_RX "50" -CH0_RX_DCC "DC" -CH0_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH0_TX_SB "DISABLED" -CH0_RX_SB "DISABLED" -CH0_TX_8B10B "ENABLED" -CH0_RX_8B10B "ENABLED" -CH0_COMMA_A "1100000101" -CH0_COMMA_B "0011111010" -CH0_COMMA_M "1111111100" -CH0_RXWA "ENABLED" -CH0_ILSM "ENABLED" -CH0_CTC "DISABLED" -CH0_CC_MATCH4 "0000011100" -CH0_CC_MATCH_MODE "1" -CH0_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH0_SSLB "DISABLED" -CH0_SPLBPORTS "DISABLED" -CH0_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/code/ip/serdes_sync_upstream.ipx b/code/ip/serdes_sync_upstream.ipx index be6e918..c75996b 100644 --- a/code/ip/serdes_sync_upstream.ipx +++ b/code/ip/serdes_sync_upstream.ipx @@ -1,11 +1,11 @@ - + - - - - - - + + + + + + diff --git a/code/ip/serdes_sync_upstream.lpc b/code/ip/serdes_sync_upstream.lpc index 7cbc9d4..832cc40 100644 --- a/code/ip/serdes_sync_upstream.lpc +++ b/code/ip/serdes_sync_upstream.lpc @@ -16,8 +16,8 @@ CoreRevision=8.1 ModuleName=serdes_sync_upstream SourceFormat=VHDL ParameterFileVersion=1.0 -Date=05/06/2014 -Time=11:35:18 +Date=07/08/2014 +Time=16:04:19 [Parameters] Verilog=0 diff --git a/code/ip/serdes_sync_upstream.txt b/code/ip/serdes_sync_upstream.txt deleted file mode 100644 index a057cb3..0000000 --- a/code/ip/serdes_sync_upstream.txt +++ /dev/null @@ -1,58 +0,0 @@ -# This file is used by the simulation model as well as the ispLEVER bitstream -# generation process to automatically initialize the PCSD quad to the mode -# selected in the IPexpress. This file is expected to be modified by the -# end user to adjust the PCSD quad to the final design requirements. - -DEVICE_NAME "LFE3-150EA" -CH3_PROTOCOL "G8B10B" -CH0_MODE "DISABLED" -CH1_MODE "DISABLED" -CH2_MODE "DISABLED" -CH3_MODE "RXTX" -CH3_CDR_SRC "REFCLK_CORE" -PLL_SRC "REFCLK_CORE" -TX_DATARATE_RANGE "MEDHIGH" -CH3_RX_DATARATE_RANGE "MEDHIGH" -REFCK_MULT "10X" -#REFCLK_RATE 200 -CH3_RX_DATA_RATE "FULL" -CH3_TX_DATA_RATE "FULL" -CH3_TX_DATA_WIDTH "8" -CH3_RX_DATA_WIDTH "8" -CH3_TX_FIFO "DISABLED" -CH3_RX_FIFO "DISABLED" -CH3_TDRV "0" -#CH3_TX_FICLK_RATE 200 -#CH3_RXREFCLK_RATE "200" -#CH3_RX_FICLK_RATE 200 -CH3_TX_PRE "DISABLED" -CH3_RTERM_TX "50" -CH3_RX_EQ "DISABLED" -CH3_RTERM_RX "50" -CH3_RX_DCC "DC" -CH3_LOS_THRESHOLD_LO "2" -PLL_TERM "50" -PLL_DCC "AC" -PLL_LOL_SET "0" -CH3_TX_SB "DISABLED" -CH3_RX_SB "DISABLED" -CH3_TX_8B10B "ENABLED" -CH3_RX_8B10B "ENABLED" -CH3_COMMA_A "1100000101" -CH3_COMMA_B "0011111010" -CH3_COMMA_M "1111111100" -CH3_RXWA "ENABLED" -CH3_ILSM "ENABLED" -CH3_CTC "DISABLED" -CH3_CC_MATCH4 "0100011100" -CH3_CC_MATCH_MODE "1" -CH3_CC_MIN_IPG "3" -CCHMARK "9" -CCLMARK "7" -CH3_SSLB "DISABLED" -CH3_SPLBPORTS "DISABLED" -CH3_PCSLBPORTS "DISABLED" -INT_ALL "DISABLED" -QD_REFCK2CORE "ENABLED" - - diff --git a/code/med_ecp3_sfp_4_sync_down.vhd b/code/med_ecp3_sfp_4_sync_down.vhd index d85ecba..d7fbf0a 100644 --- a/code/med_ecp3_sfp_4_sync_down.vhd +++ b/code/med_ecp3_sfp_4_sync_down.vhd @@ -434,7 +434,7 @@ generated_logic : for i in 0 to 3 generate ------------------------------------------------- THE_TX : soda_tx_control port map( - CLK_200 => tx_full_clk(i), --clk_200_i(i), + CLK_200 => clk_200_txdata, --tx_full_clk(i), --clk_200_i(i), CLK_100 => SYSCLK, RESET_IN => rst(i), --CLEAR, PL! diff --git a/code/med_ecp3_sfp_sync_up.vhd b/code/med_ecp3_sfp_sync_up.vhd index 8644227..353c15f 100644 --- a/code/med_ecp3_sfp_sync_up.vhd +++ b/code/med_ecp3_sfp_sync_up.vhd @@ -31,7 +31,8 @@ entity med_ecp3_sfp_sync_up is RX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz TX_HALF_CLK_OUT : out std_logic := '0'; --received 100 MHz - TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + TX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz + RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014 --Sync operation RX_DLM : out std_logic := '0'; @@ -201,7 +202,8 @@ clk_200_osc <= OSCCLK; RX_HALF_CLK_OUT <= rx_half_clk_ch3; RX_FULL_CLK_OUT <= rx_full_clk_ch3; TX_HALF_CLK_OUT <= tx_half_clk_ch3; -TX_FULL_CLK_OUT <= tx_full_clk_ch3; +TX_FULL_CLK_OUT <= tx_full_clk_ch3; +RX_CDR_LOL_OUT <= rx_cdr_lol; -- !PL14082014 SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready @@ -325,7 +327,7 @@ tx_allow_q <= tx_allow when rising_edge(SYSCLK); PROC_START_TIMER : process(rx_full_clk_ch3) --clk_200_osc) --clk_200_i) begin - if rising_edge(clk_200_osc) then + if rising_edge(rx_full_clk_ch3) then --clk_200_osc) then if got_link_ready_i = '1' then watchdog_timer <= (others => '0'); if start_timer(start_timer'left) = '0' then diff --git a/code/soda_components.vhd b/code/soda_components.vhd index b3dd5d8..c075021 100644 --- a/code/soda_components.vhd +++ b/code/soda_components.vhd @@ -451,6 +451,7 @@ component med_ecp3_sfp_sync_up is RX_FULL_CLK_OUT : out std_logic := '0'; --received 200 MHz TX_HALF_CLK_OUT : out std_logic := '0'; --pll 100 MHz TX_FULL_CLK_OUT : out std_logic := '0'; --pll 200 MHz + RX_CDR_LOL_OUT : out std_logic := '0'; -- CLOCK_DATA RECOVERY LOSS_OF_LOCK !PL14082014 --Sync operation RX_DLM : out std_logic := '0'; RX_DLM_WORD : out std_logic_vector(7 downto 0) := x"00"; diff --git a/code/soda_hub.vhd b/code/soda_hub.vhd index f260850..1b104d0 100644 --- a/code/soda_hub.vhd +++ b/code/soda_hub.vhd @@ -160,10 +160,10 @@ begin --TXsoda_cmd_word_S(i) <= (others => '0'); --TXsuper_burst_nr_S(i) <= (others => '0'); --else - --TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; - --TXstart_of_superburst_S(i) <= start_of_superburst_S; - --TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; - --TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; + TXsoda_cmd_valid_S(i) <= soda_cmd_valid_S; + TXstart_of_superburst_S(i) <= start_of_superburst_S; + TXsoda_cmd_word_S(i) <= '0' & soda_cmd_word_S; + TXsuper_burst_nr_S(i) <= '0' & super_burst_nr_S; --end if; --end if; --end process; diff --git a/code/trb3_periph_sodahub.vhd b/code/trb3_periph_sodahub.vhd index dff97ba..21b88a7 100644 --- a/code/trb3_periph_sodahub.vhd +++ b/code/trb3_periph_sodahub.vhd @@ -93,7 +93,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal GSR_N : std_logic; attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; - signal clk_sys_internal : std_logic; + signal clk_100_osc : std_logic; -- signal clk_raw_internal : std_logic; signal clk_200_osc : std_logic; @@ -101,6 +101,7 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is signal rxup_full_clk : std_logic; signal txup_half_clk : std_logic; signal txup_full_clk : std_logic; + signal rx_cdr_lol_S : std_logic; signal rxdn_half_clk : t_HUB_BIT; signal rxdn_full_clk : t_HUB_BIT; @@ -224,8 +225,8 @@ architecture trb3_periph_sodahub_arch of trb3_periph_sodahub is attribute syn_keep of soda_counter_i : signal is true; -- fix signal names for constraining - attribute syn_preserve of clk_sys_internal : signal is true; - attribute syn_keep of clk_sys_internal : signal is true; + attribute syn_preserve of clk_100_osc : signal is true; + attribute syn_keep of clk_100_osc : signal is true; -- attribute syn_preserve of clk_raw_internal : signal is true; -- attribute syn_keep of clk_raw_internal : signal is true; -- attribute syn_preserve of clk_soda_i : signal is true; @@ -252,6 +253,7 @@ begin LED_LINKOK <= (others => '0'); -- otherwise it is floating GSR_N <= pll_lock; + THE_RESET_HANDLER : trb_net_reset_handler generic map( @@ -261,8 +263,8 @@ begin CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) CLK_IN => clk_200_osc, -- raw master clock, NOT from PLL/DLL! - SYSCLK_IN => clk_sys_internal, -- PLL/DLL remastered clock - PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) + SYSCLK_IN => clk_100_osc, -- PLL/DLL remastered clock + PLL_LOCKED_IN => GSR_N, --pll_lock, -- master PLL lock signal (async) !PL 14082014 RESET_IN => '0', --general_reset_i, -- '0', -- general reset signal (SYSCLK) --peter schakel TRB_RESET_IN => med_stat_op(13), -- TRBnet reset signal (SYSCLK) CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! @@ -270,9 +272,9 @@ begin DEBUG_OUT => open ); --- process(clk_sys_internal) +-- process(clk_100_osc) -- begin --- if rising_edge(clk_sys_internal) then +-- if rising_edge(clk_100_osc) then -- general_reset_i <= not SFP_LOS(1); -- end if; -- end process; @@ -284,14 +286,14 @@ begin THE_MAIN_PLL : pll_in200_out100 port map( CLK => CLK_GPLL_RIGHT, - CLKOP => clk_sys_internal, + CLKOP => clk_100_osc, CLKOK => clk_200_osc, LOCK => pll_lock ); --end generate; --gen_125 : if USE_125_MHZ = c_YES generate --- clk_sys_internal <= CLK_GPLL_LEFT; +-- clk_100_osc <= CLK_GPLL_LEFT; -- clk_raw_internal <= CLK_GPLL_LEFT; --end generate; @@ -314,7 +316,7 @@ begin PORT_ADDR_MASK => (0 => 9, 1 => 9, 2 => 9, 3 => 4, others => 0) ) port map( - CLK => clk_sys_internal, --clk_sys_i, + CLK => rxup_half_clk, --clk_100_osc, --clk_sys_i, RESET => reset_i, DAT_ADDR_IN => regio_addr_out, @@ -395,7 +397,7 @@ begin THE_SPI_RELOAD : spi_flash_and_fpga_reload --.flash_reboot_arch port map( - CLK_IN => clk_sys_internal, --clk_sys_i, + CLK_IN => clk_100_osc, --clk_sys_i, RESET_IN => reset_i, BUS_ADDR_IN => spimem_addr, @@ -430,7 +432,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up ) port map( OSCCLK => clk_200_osc, --clk_200_i, - SYSCLK => clk_sys_internal, --clk_sys_i, + SYSCLK => clk_100_osc, --clk_sys_i, RESET => reset_i, CLEAR => clear_i, --Internal Connection for TrbNet data -> not used a.t.m. @@ -445,7 +447,8 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up RX_HALF_CLK_OUT => rxup_half_clk, RX_FULL_CLK_OUT => rxup_full_clk, TX_HALF_CLK_OUT => txup_half_clk, - TX_FULL_CLK_OUT => txup_full_clk, + TX_FULL_CLK_OUT => txup_full_clk, + RX_CDR_LOL_OUT => rx_cdr_lol_S, -- !PL 14082014 RX_DLM => rxup_dlm_i, RX_DLM_WORD => rxup_dlm_word, @@ -487,7 +490,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up A_SODA_HUB : soda_hub port map( - SYSCLK => clk_sys_internal, --clk_sys_i, + SYSCLK => rxup_half_clk, --clk_100_osc, --clk_sys_i, SODACLK => rxup_full_clk, --clk_soda_i, -- SODA_OUT_CLK => txdn_full_clk, -- This is 4 clocks !! RESET => reset_i, @@ -532,7 +535,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up port map( OSC_CLK => clk_200_osc, TX_DATACLK => rxup_full_clk, --clk_soda_i, --clk_raw_internal, --clk_200_i, - SYSCLK => clk_sys_internal, --clk_sys_i, + SYSCLK => clk_100_osc, --clk_sys_i, RESET => downlink_reset, CLEAR => downlink_clear, --------------------------------------------------------------------------------------------------------------------------------------------------------- @@ -712,7 +715,7 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up CLOCK_FREQUENCY => CLOCK_FREQUENCY ) port map ( - CLK => clk_sys_internal, + CLK => rxup_half_clk, --clk_100_osc, RESET => reset_i, CLK_EN => '1', @@ -772,19 +775,19 @@ THE_HUB_SYNC_UPLINK : med_ecp3_sfp_sync_up --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- - clock_counter_proc : process(clk_sys_internal) - begin - if rising_edge(clk_sys_internal) then - time_counter <= time_counter + 1; - end if; - end process; - - process(rxup_full_clk) --clk_soda_i) - begin - if rising_edge(rxup_full_clk) then - soda_counter_i <= soda_counter_i+1; - end if; - end process; +-- clock_counter_proc : process(rxup_half_clk, --) +-- begin +-- if rising_edge(rxup_half_clk, --) then +-- time_counter <= time_counter + 1; +-- end if; +-- end process; + +-- process(rxup_full_clk) --clk_soda_i) +-- begin +-- if rising_edge(rxup_full_clk) then +-- soda_counter_i <= soda_counter_i+1; +-- end if; +-- end process; end trb3_periph_sodahub_arch; \ No newline at end of file diff --git a/code/trb3_periph_sodasource.vhd b/code/trb3_periph_sodasource.vhd index b86f668..be52ac3 100644 --- a/code/trb3_periph_sodasource.vhd +++ b/code/trb3_periph_sodasource.vhd @@ -616,7 +616,7 @@ THE_SOB_SOURCE : soda_start_of_burst_faker THE_SODA_SOURCE : soda_source port map( SYSCLK => soda_tx_clock_half, --clk_sys_internal, --clk_sys_i, PL! 30062014 - SODACLK => soda_tx_clock_full, --clk_raw_internal, PL! 30062014 + SODACLK => soda_tx_clock_full, --clk_raw_internal, -- PL! 30062014 RESET => reset_i, --Internal Connection SODA_BURST_PULSE_IN => SOB_S, diff --git a/soda_client.lpf b/soda_client.lpf index 1c0a4fb..a74f0fc 100644 --- a/soda_client.lpf +++ b/soda_client.lpf @@ -1,4 +1,4 @@ -rvl_alias "clk_soda_i" "clk_soda_i"; +rvl_alias "rx_full_clk" "rx_full_clk"; RVL_ALIAS "clk_soda_i" "clk_soda_i"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; diff --git a/soda_client_probe.rvl b/soda_client_probe.rvl index 0a27f45..1f76566 100644 --- a/soda_client_probe.rvl +++ b/soda_client_probe.rvl @@ -1,9 +1,9 @@ - + - + - + @@ -63,11 +63,12 @@ - - + + + diff --git a/soda_hub_probe.rvl b/soda_hub_probe.rvl index 1051fb4..9f04a86 100644 --- a/soda_hub_probe.rvl +++ b/soda_hub_probe.rvl @@ -1,342 +1,201 @@ - + - + - - + + - - - - - - + + + + + + - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + - diff --git a/soda_source.lpf b/soda_source.lpf index 6b55810..771f071 100644 --- a/soda_source.lpf +++ b/soda_source.lpf @@ -1,4 +1,4 @@ -rvl_alias "soda_tx_clock_full" "the_sync_link/clk_tx_full_out"; +rvl_alias "clk_raw_internal" "clk_raw_internal"; RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; RVL_ALIAS "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; diff --git a/soda_source_probe.rvl b/soda_source_probe.rvl index 1c38c86..ae036ba 100644 --- a/soda_source_probe.rvl +++ b/soda_source_probe.rvl @@ -1,318 +1,19 @@ - + - + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + @@ -323,7 +24,6 @@ - @@ -334,82 +34,35 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + - - - - - + + + - - diff --git a/trb3_soda_hub.xcf b/trb3_soda_hub.xcf index a8b9531..6798744 100644 --- a/trb3_soda_hub.xcf +++ b/trb3_soda_hub.xcf @@ -45,8 +45,8 @@ 1 0 - /local/lemmens/lattice/soda/trb3_periph_sodahub_20140708.bit - 07/08/14 08:30:03 + /local/lemmens/lattice/soda/trb3_periph_sodahub_20140819.bit + 08/18/14 18:00:31 Fast Program