From: hadeshyp Date: Tue, 20 Jul 2010 11:18:11 +0000 (+0000) Subject: *** empty log message *** X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=65d6907c73db792518e9f4860c744160d58f599e;p=daqdocu.git *** empty log message *** --- diff --git a/cts.tex b/cts.tex index 640c9e7..426dea0 100644 --- a/cts.tex +++ b/cts.tex @@ -11,7 +11,7 @@ The schematics of the new CTS AddOn can be found in \cite{CTS}. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% For all registers described in this subsection refer to the Fig.\ref{cts_logic} To enable trigger box logic which is described in this subsection (Fig.\ref{cts_logic}) -it is necessary to set register A0C5 to 40000000. +it is necessary to set register A0C5 to 40000000. \begin{description} \item [0xA089: Debug] Trigger logic debug out \item [0xA09B -- 0xA0BA: Scaler] Scalers out @@ -41,7 +41,7 @@ it is necessary to set register A0C5 to 40000000. \item[Bit 5] MDC calibration trigger enable \item[Bit 6] Force update Shower pedestals trigger (write ..1..0) \item[Bit 7] Disable Shower pedestals update (generated once during each spill off) - \item[Bit 11 -- 8] Select frequency for internally generated trigger - $781.25kHz/(2^{value})$ + \item[Bit 11 -- 8] Select frequency for internally generated trigger - $781.25kHz/(2^{value})$. \item[Bit 12] Enable Shower calibration trigger \item[Bit 13] Enable trigger from internal generator \item[Bit 28 -- 24] MDC delay trigger. $Delay = Value * 40 ns + 30ns$ @@ -56,7 +56,7 @@ it is necessary to set register A0C5 to 40000000. \subsubsection{CTS Control and Status Registers} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% When Trigger Logic is not used (A0C5 bit 30 = 0 ) the configuration of the used logic is simple (just accepting the input triggers see address A0C5). -In this case when calibration trigger is set (0xA0C7;A0C5 bit 30 = 0) still the reference time/hold signal is send. When Trigger Logic is enabled and register 0xA0DC is used to overwrite trigger code. In this case if calibration trigger is send there is no reference time/hold signal. +In this case when calibration trigger is set (0xA0C7;A0C5 bit 30 = 0) still the reference time/hold signal is send. When Trigger Logic is enabled and register 0xA0DC is used to overwrite trigger code. In this case if calibration trigger is send there is no reference time/hold signal. It is recommended to start system ether with simple or trigger logic and do not switch between them when it is running. \begin{description} \item[0xA091: LVL1 information] Busy flags and current trigger number and type on LVL1 channel @@ -128,15 +128,15 @@ For the time being "old" logic of the CTS is not removed. \item[Bit 4 -- 0] If c7(4)=1 the lvl1 trigger type equals c7(3 downto 0) else type is defined internally or by trigger logic \end{description} -\item[0xA0C7] LVL1 trigger information +\item[0xA0C8] LVL1 trigger information \begin{description} \item[Bit 13 -- 0] LVL1 trigger information 13 downto 0 \end{description} \item[0xA0C9] Selects how many times should be sent data to the EB with current ID (which corresponds to the EB IP number), when 0 does not swith between IDs \item[0xA0CA] Tables of 8 EB IDs (each ID has four bits), the IDs are switched form CA(3 down to 0) to CA(7 down to 4) ... CB(31 down to 28) -\item[0xA0CB] Tables of 8 EB IDs (each ID has four bits) +\item[0xA0CB] Tables of 8 EB IDs (each ID has four bits) -\end{description} +\end{description} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -149,9 +149,9 @@ When there is MDC calibration trigger CTS sends also scalers information. \begin{description} \item[1 Standard hub word] When hub is used, currently without this (readout through etrax) \item[2 First header of the data] the same as for the timing detectors (Start,TOF ...) -\item[3 Second header] +\item[3 Second header] \begin{description} - \item[bit 31 -- 16] Data version + \item[bit 31 -- 16] Data version \item[bit 15 -- 0] Number of extension words \end{description} \item[4 Latches] @@ -167,13 +167,13 @@ When there is MDC calibration trigger CTS sends also scalers information. \item[bit 8] TOF/RPC multiplicity 2 no neigbour \item[bit 9] TOF/RPC multiplicity 3 no neighbour \item[bit 10] TOF/RPC multiplicity 2 opposite sectors - \item[bit 11] Physical trigger (PT) 1 (definition depends on the beam time) - \item[bit 12] PT 2 + \item[bit 11] Physical trigger (PT) 1 (definition depends on the beam time) + \item[bit 12] PT 2 \item[bit 13] PT 3 \item[bit 14] PT 4 \item[bit 31 -- 15] All 0 \end{description} -\item[5 Currently empty] +\item[5 Currently empty] \item[13 -- 6 Start scalers] \item[21 -- 14 Veto scalers] \item[27 -- 22 TOF scalers] @@ -181,11 +181,11 @@ When there is MDC calibration trigger CTS sends also scalers information. \item[37 -- 34 PT scalers] \item[38 Start OR scaler] \item[39 Veto OR scaler] -\item[43 -- 40 PT delayed scalers] +\item[43 -- 40 PT delayed scalers] \item[52 -- 44 Multiplicity scalers] The same order as for latches -\end{description} +\end{description} diff --git a/daqstartup.tex b/daqstartup.tex index 0a39ca9..8821200 100755 --- a/daqstartup.tex +++ b/daqstartup.tex @@ -3,7 +3,7 @@ One of the advantages of the new slow control system is that all subsystems now can be addressed and configured with one common interface. There is no need to log in to several boards and execute system specific commands there. -The startup procedure for each subsystem consists of several files: +The startup procedure for each subsystem consists of several files: \begin{itemize} \item A documentation that shows which steps have to be done in which order @@ -91,7 +91,7 @@ The table with addresses has five columns, besides the address and the serial nu 022 0x5e000001fc535c28 023 0x59000001fc488628 025 0x15000001fc5c5328 -\end{lstlisting} +\end{lstlisting} \lstset { caption ={Example: addresses\_oep.db}} @@ -103,7 +103,7 @@ The table with addresses has five columns, besides the address and the serial nu 0x2002 024 1 12 0 0x2003 023 1 12 0 0x2004 022 1 12 0 -\end{lstlisting} +\end{lstlisting} \subsection{Registers} @@ -120,7 +120,7 @@ The most common operation is to load some settings to registers on the FPGA. In !Value table # OEP # Type # T0 # T1 # T2 # T3 # T4 # T5 # ################################################### - 0x2000 1 0xff 0xff 0xff 0xff + 0x2000 1 0xff 0xff 0xff 0xff 0x2001 2 0xff 0xff 0xff 0xff 0xff 0xff 0x2002 2 0xff 0xff 0xff 0xff 0xff 0xff 0x2003 1 0xff 0xff 0xff 0xff @@ -158,10 +158,11 @@ Since the unpacker should be able to work in a data-driven mode, the version of 8 TRBSlwCtrl 0x4ab38e12 trb2_ctrl_20091030.stp 1 9 MDCAddOnFPGA1 0x12347832 mdcopt_1_20091027.stp 1 10 MDCAddOnFPGA2 0x12347832 mdcopt_2_20091027.stp 1 -\end{lstlisting} +\end{lstlisting} \subsection{Modifiers} +Modifieres written in camel case have to be given to the startup script in all uppercase, modifieres shown in lower case are also lower case on the command line. \subsubsection*{Common Settings} \begin{description} @@ -201,14 +202,19 @@ Since the unpacker should be able to work in a data-driven mode, the version of \end{description} -\subsubsection*{MDC settings} +\subsubsection*{MDC Settings} \begin{description} \item[\textsc{reg0}] Load settings for TDC register 0, overwrite default values in OEP \item[\textsc{reg1}] Load settings for TDC register 1, overwrite default values in OEP \item[\textsc{thresh*}] Load special threshold values for all boards. Values are given in hex: thresh10, thresh20, thresh30, thresh40, thresh50, thresh60, thresh70, thresh80, thresh90, thresha0, threshf0. \item[\textsc{calib}] Temporary: run calibration triggers \item[\textsc{nocms}] Temporary: use internal cms, not external signal + \item[\textsc{Mdcswitchoff}] Runs a script with commands to switch off not correctly connected OEP + \item[\textsc{Mdcreboot}] Reboots OEP with the current design for data taking \end{description} +\subsubsection*{Shower Settings} - +\begin{description} + \item[\textsc{Showerped*}] Loads Shower pedestals. Valid names are Showerpeddef (loads the measured pedestals), Showerped20 (all set to 0x20), Showerped40 (all set to 0x40), Showerpedff (all set to 0xff) +\end{description} diff --git a/lvl1trigger.tex b/lvl1trigger.tex index be51366..0e0413d 100755 --- a/lvl1trigger.tex +++ b/lvl1trigger.tex @@ -3,7 +3,7 @@ \subsection{Trigger Procedure Overview} In the new system each trigger consists of to separated events: First, a timing trigger is received on the dedicated trigger input which delivers accurate timing information and starts the readout cycle. -Some microseconds later (typically 2 - 3 us) the LVL1 trigger packet will be received over TrbNet. The information will be completely decoded internally in the endpoint and given to the user using the interface described in section \ref{LVL1userinterface}. This +Some microseconds later (typically 2 - 3 us) the LVL1 trigger packet will be received over TrbNet. The information will be completely decoded internally in the endpoint and given to the user using the interface described in section \ref{LVL1userinterface}. This packet contains the trigger number, trigger type and additional information. In total, 52 Bits of information can be transported with each trigger packet. Despite the trigger number a second feature is used to identify events: The trigger packet contains a random code that has to be stored with the event data and is checked during readout. This gives a better protection from event mixing than a deterministic counter which can easily be screwed up by an erroneous increase signal. @@ -11,40 +11,107 @@ Despite the trigger number a second feature is used to identify events: The trig As soon as the frontend is able to handle the next timing trigger, the trigger is released (like the busy release in our old system) by setting the corresponding signal on the user interface along with basic error information as described in section \ref{LVL1Errorbits}. \subsection{Trigger-less Triggers} -For calibration triggers the separation into timing trigger and LVL1 trigger packet causes some difficulties: The timing trigger would start the readout process, but some time later the trigger packet arrives stating that there is no normal event but a calibration should be done instead. This then would cause the readout logic to discard the gathered data and start readout again in calibration mode. +For calibration triggers the separation into timing trigger and LVL1 trigger packet causes some difficulties: The timing trigger would start the readout process, but some time later the trigger packet arrives stating that there is no normal event but a calibration should be done instead. This then would cause the readout logic to discard the gathered data and start readout again in calibration mode. Therefore, for calibration and similar triggers there will be no timing trigger but only a LVL1 trigger packet. To distinguish this situation from an error on the timing cable, the distinction is made based on the trigger type. Trigger types 0 to 7 are preceded by a timing trigger, types 8 to F are not. To allow for further checks, also Bit 7 of the trigger information will be set for LVL1 triggers without timing trigger. Additionally the user logic can provide some checks to assure that e.g. a normal trigger must always be preceded by a timing trigger. +\subsection{Trigger Handler} +The LVL1 trigger handler is included in every \filename{endpoint\_hades\_full} and checks for correct timing and order on the LVL1 channel. It monitores the incoming timing trigger signal, rejects spikes and other erroneous triggers, checks timing trigger less triggers for correctness and forwards information to the FEE. + +All actions inside the FPGA and the FEE that are triggered with the external timing signal should rely on the output of this entity only. FEE which need an exact timing (with a resolution higher than the internal clock period) and therefore access to the raw timing trigger signal are the only execption from this rule. Nevertheless, the user has to make sure that the FEE is correctly working in the case that a raw timing trigger is accepted by the FEE but rejected by the LVL1 handler. + +All information generated by the LVL1 handler is available on the user interface: four signals validate or invalidate incoming triggers and trigger information, two ports are used for the feedback from the FEE and several ports give additional status information about the situation on the timing trigger input. + +The checks done in the LVL1 handler include: +\begin{itemize} + \item Check the length of trigger pulse - the length is defined to be more than 100~ns. All pulses below 40~ns are rejected as spikes + \item For each timing trigger there must be a corresponding LVL1 trigger information + \item For each timing trigger less trigger on the LVL1 channel there must be no timing trigger + \item The time between timing trigger and LVL1 trigger must not exceed a certain time limit (currently about 20 us) + \item Trigger signal is checked for right polarity. Otherwise a status bit is set and the trigger polarity can be inverted via slow control +\end{itemize} + +All possible combinations of events on the timing trigger input and the LVL1 data bus can be divided into six basic categories: + +\begin{figure} + \centering + \includegraphics[width=\textwidth]{timingtriggercase1.png} + \caption{Timing Diagram: Timing Trigger and LVL1 channel events - case 1} + \label{fig:timingtriggercase1} +\end{figure} + +\begin{figure} + \centering + \includegraphics[width=\textwidth]{timingtriggercase2.png} + \caption{Timing Diagram: Timing Trigger and LVL1 channel events - case 2} + \label{fig:timingtriggercase2} +\end{figure} + + +\begin{figure} + \centering + \includegraphics[width=\textwidth]{timingtriggercase3.png} + \caption{Timing Diagram: Timing Trigger and LVL1 channel events - case 3} + \label{fig:timingtriggercase3} +\end{figure} + + +\begin{figure} + \centering + \includegraphics[width=\textwidth]{timingtriggercase4.png} + \caption{Timing Diagram: Timing Trigger and LVL1 channel events - case 4} + \label{fig:timingtriggercase4} +\end{figure} + + +\begin{figure} + \centering + \includegraphics[width=\textwidth]{timingtriggercase5.png} + \caption{Timing Diagram: Timing Trigger and LVL1 channel events - case 5} + \label{fig:timingtriggercase5} +\end{figure} + + +\begin{figure} + \centering + \includegraphics[width=\textwidth]{timingtriggercase6.png} + \caption{Timing Diagram: Timing Trigger and LVL1 channel events - case 6} + \label{fig:timingtriggercase6} +\end{figure} + + + + \subsection{User Interface} \label{LVL1userinterface} \begin{figure} \centering \includegraphics[width=0.9\textheight, angle= 90]{triggerinterface.png} - \caption[Timing Diagram: LVL1 Trigger Interface]{LVL1 Trigger Interface timing. Port TrgReceived is now named TrgDataValid.} + \caption[Timing Diagram: LVL1 Trigger Interface]{LVL1 Trigger Interface timing.} \label{fig:triggerinterface} \end{figure} -\begin{description} - - \item [\portname{Lvl1\_\-valid\_\-timing\_\-trg\_\-out}] A timing trigger has been received and the internal state machine marked it as valid. Typically set 2 to 5 clock cycles after \portname{trg\_\-timing\_\-trg\_\-received\_\-in} was high. - \item [\portname{Lvl1\_\-valid\_\-notiming\_\-trg\_\-out}] A valid timing-trigger-less LVL1 trigger has been received. Typically high 1 to 2 clock cycles after the rising edge of \portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out}. - \item [\portname{Lvl1\_\-invalid\_\-trg\_\-out}] A trigger (either timing trigger or LVL1 trigger) has been received which has been marked invalid by the internal state machine. E.g. to timing triggers without a LVL1 trigger or a LVL1 trigger without preceeding timing trigger has been detected. - \item [\portname{Lvl1\_\-trg\_\-type\_\-out}] The trigger type, similar to the old system. - \item [\portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out}] Rising edge marks that a LVL1 trigger information has been received. Falling edge comes after user set \portname{Lvl1\_\-Trg\_\-Release}. While high, all trigger information ports, namely \portname{Lvl1\_\-Trg\_\-Type}, \portname{Lvl1\_\-Trg\_\-Number}, \portname{Lvl1\_\-Trg\_\-Code} and \portname{Lvl1\_\-Trg\_\-In\-for\-ma\-tion} are valid. - \item [\portname{Lvl1\_\-trg\_\-number\_\-out}] (16 bit) Trigger number. - \item [\portname{Lvl1\_\-trg\_\-code\_\-out}] (8 bit) A random code generated by CTS that has to be stored and put to the IPU data stream. - \item [\portname{Lvl1\_\-trg\_\-information\_\-out}] (24 bit) Additional information about trigger as explained in the corresponding section. - \item [\portname{Lvl1\_\-error\_\-pattern\_\-in}] (32 bit) Error and status bits as explained in the corresponding section. Must be valid when \portname{Lvl1\_\-\-Trg\_\-\-Release} is high. - \item [\portname{Lvl1\_\-trg\_\-release\_\-in}] Must be set for at least one clock cycle to release the trigger (comparable to the old ``busy release''). - \item [\portname{Lvl1\_\-int\_\-trg\_\-number\_\-out}] (16 bit) The internal trigger counter counting the received timing triggers. Will be valid 5 clock cycles after a timing trigger has been received until \portname{Lvl1\_\-\-Trg\_\-\-Received} goes down. - \item [\portname{trg\_\-timing\_\-trg\_\-received\_\-in}] Here are pulse for each received timing trigger has to be connected. This allows the endpoint to generate the \portname{Lvl1\_\-Int\_\-Trg\_\-Number\_\-Out}. -\end{description} +% \begin{description} +% +% \item [\portname{Lvl1\_\-valid\_\-timing\_\-trg\_\-out}] A timing trigger has been received and the internal state machine marked it as valid. Typically set 2 to 5 clock cycles after \portname{trg\_\-timing\_\-trg\_\-received\_\-in} was high. +% \item [\portname{Lvl1\_\-valid\_\-notiming\_\-trg\_\-out}] A valid timing-trigger-less LVL1 trigger has been received. Typically high 1 to 2 clock cycles after the rising edge of \portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out}. +% \item [\portname{Lvl1\_\-invalid\_\-trg\_\-out}] A trigger (either timing trigger or LVL1 trigger) has been received which has been marked invalid by the internal state machine. E.g. to timing triggers without a LVL1 trigger or a LVL1 trigger without preceeding timing trigger has been detected. +% \item [\portname{Lvl1\_\-trg\_\-type\_\-out}] The trigger type, similar to the old system. +% \item [\portname{Lvl1\_\-trg\_\-data\_\-valid\_\-out}] Rising edge marks that a LVL1 trigger information has been received. Falling edge comes after user set \portname{Lvl1\_\-Trg\_\-Release}. While high, all trigger information ports, namely \portname{Lvl1\_\-Trg\_\-Type}, \portname{Lvl1\_\-Trg\_\-Number}, \portname{Lvl1\_\-Trg\_\-Code} and \portname{Lvl1\_\-Trg\_\-In\-for\-ma\-tion} are valid. +% \item [\portname{Lvl1\_\-trg\_\-number\_\-out}] (16 bit) Trigger number. +% \item [\portname{Lvl1\_\-trg\_\-code\_\-out}] (8 bit) A random code generated by CTS that has to be stored and put to the IPU data stream. +% \item [\portname{Lvl1\_\-trg\_\-information\_\-out}] (24 bit) Additional information about trigger as explained in the corresponding section. +% \item [\portname{Lvl1\_\-error\_\-pattern\_\-in}] (32 bit) Error and status bits as explained in the corresponding section. Must be valid when \portname{Lvl1\_\-\-Trg\_\-\-Release} is high. +% \item [\portname{Lvl1\_\-trg\_\-release\_\-in}] Must be set for at least one clock cycle to release the trigger (comparable to the old ``busy release''). +% \item [\portname{Lvl1\_\-int\_\-trg\_\-number\_\-out}] (16 bit) The internal trigger counter counting the received timing triggers. Will be valid 5 clock cycles after a timing trigger has been received until \portname{Lvl1\_\-\-Trg\_\-\-Received} goes down. +% \item [\portname{trg\_\-timing\_\-trg\_\-received\_\-in}] Here are pulse for each received timing trigger has to be connected. This allows the endpoint to generate the \portname{Lvl1\_\-Int\_\-Trg\_\-Number\_\-Out}. +% \end{description} \subsection{Status and Error Bits} \label{LVL1errorbits} -The channel specific status and error bits contain information about mismatches between timing triggers and LVL1 trigger information +The channel specific status and error bits contain information about mismatches between timing triggers and LVL1 trigger information In general it is preferable to have soft interrupts before a buffer runs full instead of hard stops when the is nearly an overflow. Therefore information about the fill level of data buffers is included in the status bits. The CTS might then block some triggers to give the readout system the possibility to empty buffers again. @@ -89,11 +156,11 @@ In case a particular trigger type is not supported by one frontend, an empty eve 7 & \\ 8 & \\ 9 & MDC Calibration\\ -A & Shower Calibration\\ +A & Shower Calibration\\ B & Shower Pedestals\\ -C & RICH Calibration\\ +C & RICH Calibration\\ D & \\ -E & \\ +E & \\ F & \\ \end{tabular} \caption{Trigger Types. List is not complete. Triggers 8 to F are not sent in combination with a timing trigger.} diff --git a/mdc.tex b/mdc.tex index 2185341..b8b13b0 100755 --- a/mdc.tex +++ b/mdc.tex @@ -146,7 +146,27 @@ C1 & 27 -- 16 & Number of dummy data words (if enabled)\\ \end{center} \end{table} - +\begin{table} +\begin{center} +\begin{tabularx}{\textwidth}{|c|l|X|} +\hline +\textbf{Bits} & \textbf{Description} & \textbf{MDC}\\ +\hline\hline +31 -- 24 & reserved & n/a\\ +23 & frontend error & no token back. Timeout is 2.6 ms (set by trigger handler)\\ +22 & not configured & TDC / CPLD / DAC are not configured. No begin run trigger has been executed since the last reset (set in mdc control)\\ +21 & buffer almost full & The data buffers hold more than 7168 words or there are more than 498 events stored in the frontend (set by data handler in endpoint)\\ +20 & buffer half full & The data buffers hold more than 4096 words or there are more than 256 events stored in the frontend (set by data handler in endpoint)\\ +19 & reserved & n/a\\ +18 & multiple timing trg & There were to singals on the timing input but only one LVL1 trigger (as set by the LVL1 handler) \\ +17 & timing trg missing & A LVL1 trigger has been received which needs a timing trigger, but no timing trigger was seen. Set by trigger interface or user. (as set by the LVL1 handler) \\ +16 & trg. counter mismatch & The internal trigger number does not match the received trigger number. Set by trigger interface or user. (as set by the LVL1 handler)\\ +\hline +\end{tabularx} +\caption{Statusbits on LVL1 channel on MDC OEP} +\label{MDCLVL1Statusbits} +\end{center} +\end{table} \subsubsection{MDC Optical Endpoint Voltage Monitoring} The ADC monitoring most voltages on each OEP can be accessed using register addresses 0x8000 to 0x803F. The memory map is given in table \ref{MDCOEPADCMemoryMap}, the voltages connected in table \ref{MDCOEPADCChannels}. diff --git a/slowcontrol.tex b/slowcontrol.tex index b42e744..3e0c0a8 100755 --- a/slowcontrol.tex +++ b/slowcontrol.tex @@ -248,14 +248,16 @@ E000 -- FFFF & Debugging & Memories and Registers for Debugging \\ \end{table} -\paragraph{Common Control and Status Registers (0x00 - 0x01, 0x20 - 0x22)} +\paragraph{Common Control and Status Registers (0x00 - 0x03, 0x20 - 0x22)} The first common status register (0x00) is described in table \ref{CommonStatReg0}. It is used for error flags and readback of the boards temperature. The second status register (0x01) is used to read the LVL1 trigger number of the last timing trigger (Bits 15 -- 0) and the number of the event last read on the IPU channel (Bits 31 -- 16). +\noindent The third register (0x2) gives the status of the LVL1 handler and register 0x3 shows the number of received +timing signals in the lower 16 bits and the length of the last timing signal in the upper 16 bit. -\noindent The first common control register (0x20) consists of strobe signals for dummy timing triggers and reset +The first common control register (0x20) consists of strobe signals for dummy timing triggers and reset signals as shown in table \ref{CommonCtrlReg0}. N.B. before a complete reset or reboot is executed, a delay of about 3~us has to be included to allow the endpoint to send back a correct answer. @@ -312,21 +314,13 @@ A detailed bit definition can be found in table~\ref{CommonCtrlReg2}. 3 -- 0 & Status of LVL1 handler state machine. 0: idle, 1: timing trigger found, 3: LVL1 trigger received, 5: bad combination of timing trigger and LVL1 trigger, 7: done.\\ \hline \end{tabularx} -\caption{Common Status Register 2} +\caption{Common Status Register 2 (CSR2)} \label{CommonStatReg2} \end{center} \end{table} - - - - - - - - \begin{table} \begin{center} \begin{tabular}{|c|c|} diff --git a/software.tex b/software.tex index 090c3dd..fc550cc 100755 --- a/software.tex +++ b/software.tex @@ -210,6 +210,13 @@ voltage regulator (output): (0: 5.6V input, 1: 5V output, 2: 3.5V input, 3: 3.3V output, 4: 1.6V input, 5: 1.2V output, 6: +3V input, 7: -3V input). +\subsection{Shower} +\paragraph*{\$write shower pede(stals)? \$sector \$plane \$row \$column \$value} ~\\ +Sets the pedestal value for the selected front-end channel on Shower. \$sector, \$row +and \$column have to be plain numbers, \$value is the desired pedestal setting in hex +notation. \$plane is one of "pre", "post1", "post2". + + \subsection{Network Hubs} \paragraph*{\$read hub setup} optional: \verb|$addr|, \verb|raw| \\ diff --git a/timingtriggercase1.png b/timingtriggercase1.png new file mode 100644 index 0000000..929b48a Binary files /dev/null and b/timingtriggercase1.png differ diff --git a/timingtriggercase2.png b/timingtriggercase2.png new file mode 100644 index 0000000..3a029d8 Binary files /dev/null and b/timingtriggercase2.png differ diff --git a/timingtriggercase3.png b/timingtriggercase3.png new file mode 100644 index 0000000..03650d3 Binary files /dev/null and b/timingtriggercase3.png differ diff --git a/timingtriggercase4.png b/timingtriggercase4.png new file mode 100644 index 0000000..24e5f85 Binary files /dev/null and b/timingtriggercase4.png differ diff --git a/timingtriggercase5.png b/timingtriggercase5.png new file mode 100644 index 0000000..efb6420 Binary files /dev/null and b/timingtriggercase5.png differ diff --git a/timingtriggercase6.png b/timingtriggercase6.png new file mode 100644 index 0000000..60b4adc Binary files /dev/null and b/timingtriggercase6.png differ diff --git a/triggerinterface.png b/triggerinterface.png index f03e21c..214300b 100755 Binary files a/triggerinterface.png and b/triggerinterface.png differ