From: Jan Michel <j.michel@gsi.de>
Date: Thu, 29 Aug 2013 09:53:51 +0000 (+0200)
Subject: added variable SPI mode
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=66555ac34f96f1733fb7385906d5028b6ff6ace0;p=trbnet.git

added variable SPI mode
---

diff --git a/special/spi_ltc2600.vhd b/special/spi_ltc2600.vhd
index 4d2d2b3..cfb5b64 100644
--- a/special/spi_ltc2600.vhd
+++ b/special/spi_ltc2600.vhd
@@ -4,6 +4,10 @@ use IEEE.numeric_std.all;
 
 
 entity spi_ltc2600 is
+  generic(
+    BITS            : integer range 8 to 32 := 32;
+    WAITCYCLES      : integer range 2 to 1024 := 7
+    );
   port(
     CLK_IN          : in   std_logic;
     RESET_IN        : in   std_logic;
@@ -39,9 +43,9 @@ architecture spi_ltc2600_arch of spi_ltc2600 is
   signal spi_sck   : std_logic;
   signal spi_sd    : std_logic;
   
-  signal word_count : integer range 0 to 31;
-  signal bit_count  : integer range 0 to 31;
-  signal time_count : integer range 0 to 7;
+  signal word_count : integer range 0 to BITS-1;
+  signal bit_count  : integer range 0 to BITS-1;
+  signal time_count : integer range 0 to WAITCYCLES;
   signal readback   : std_logic_vector(31 downto 0);
   
   type fsm_t is (IDLE, WAIT_STATE, SET, TOGGLE_CS, TOGGLE_CS_0, TOGGLE_CS_1, TOGGLE_CS_2,  FINISH);
@@ -104,8 +108,8 @@ begin
         if start = '1' then
           ram_addr   <= 0;
           word_count <= to_integer(unsigned(ctrl_reg(4 downto 0)));
-          bit_count  <= 31;
-          time_count <= 7;
+          bit_count  <= BITS-1;
+          time_count <= WAITCYCLES;
           fsm_state  <= WAIT_STATE;
           spi_cs     <= not chipselect_reg;
           spi_sck    <= '1';
@@ -122,7 +126,7 @@ begin
         end if;
         
       when SET =>
-        time_count <= 7;
+        time_count <= WAITCYCLES;
         spi_sck      <= not spi_sck;
         if spi_sck = '1' then
           spi_sd     <= ram_data(bit_count);
@@ -131,7 +135,7 @@ begin
             fsm_state  <= WAIT_STATE;
           else
             ram_addr  <= ram_addr + 1;
-            bit_count <= 31;
+            bit_count <= BITS-1;
             if ram_addr /= word_count -1 then
               if ctrl_reg(7) = '0' then --one CS phase
                 fsm_state <= WAIT_STATE;
@@ -167,20 +171,20 @@ begin
          time_count <= time_count - 1;
          if time_count = 0 then
            spi_cs  <= not chipselect_reg;
-           bit_count <= 31;
+           bit_count <= BITS-1;
            fsm_state <= WAIT_STATE;
-           time_count <= 7;
+           time_count <= WAITCYCLES;
          end if;  
       when TOGGLE_CS_2 =>           
          time_count <= time_count - 1;
          if time_count = 0 then
            spi_sck <= not spi_sck;
            fsm_state <= WAIT_STATE;
-           time_count <= 7;
+           time_count <= WAITCYCLES;
          end if;
       when FINISH =>
         if time_count = 0 and spi_sck = '0' then
-          time_count <= 7;
+          time_count <= WAITCYCLES;
           spi_sck    <= not spi_sck;
           readback   <= readback(30 downto 0) & SPI_SDI_IN;          
         elsif time_count = 0 and spi_sck = '1' then