From: Thomas Gessler Date: Wed, 30 Sep 2020 13:37:39 +0000 (+0200) Subject: tx control: Fix signal_sync source clocks X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=66bc49708c3a7c70414a771722786e1bbe12a40f;p=trbnet.git tx control: Fix signal_sync source clocks TX_ALLOW_IN, RX_ALLOW_IN and SEND_LINK_RESET_IN are synchronous to the system clock. tx_allow_qtx is synchronous to the TXI clock. --- diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index 58d6d82..2126c74 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -356,16 +356,16 @@ begin -- ---------------------------------------------------------------------- - txallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, + txallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_100, CLK1 => CLK_200, D_IN(0) => TX_ALLOW_IN, D_OUT(0) => tx_allow_qtx); - rxallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, + rxallow_sync : signal_sync port map(RESET => '0',CLK0 => CLK_100, CLK1 => CLK_200, D_IN(0) => RX_ALLOW_IN, D_OUT(0) => rx_allow_qtx); - sendres_sync : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_200, + sendres_sync : signal_sync port map(RESET => '0',CLK0 => CLK_100, CLK1 => CLK_200, D_IN(0) => SEND_LINK_RESET_IN, D_OUT(0) => send_link_reset_qtx); - txallow_sync2 : signal_sync port map(RESET => '0',CLK0 => CLK_100, CLK1 => CLK_100, + txallow_sync2 : signal_sync port map(RESET => '0',CLK0 => CLK_200, CLK1 => CLK_100, D_IN(0) => tx_allow_qtx, D_OUT(0) => tx_allow_q);