From: Ingo Froehlich <ingo@nomail.fake>
Date: Thu, 25 Jan 2018 15:16:42 +0000 (+0100)
Subject: generic flash ctrl, IF
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=66fb7e33511f5129bccb142f42c4cf0fc36aebf8;p=logicbox.git

generic flash ctrl, IF
---

diff --git a/default/logicbox.prj b/default/logicbox.prj
index 23ee672..2b1374f 100644
--- a/default/logicbox.prj
+++ b/default/logicbox.prj
@@ -8,16 +8,19 @@ add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesi
 
 #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd"
 add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd"
-add_file -vhdl -lib work "../code/uart_sctrl.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/interface/uart_sctrl.vhd"
 add_file -vhdl -lib work "../code/sedcheck.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
 
-add_file -vhdl -lib work "../cores/flashram.vhd"
-add_file -vhdl -lib work "../cores/efb.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flashram.vhd"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/flash.vhd"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/efb_define_def.v"
+add_file -verilog -lib work "../../vhdlbasics/machxo3/flash/UFM_WB.v"
+add_file -vhdl -lib work "../../vhdlbasics/machxo3/flash/generic_flash_ctrl.vhd"
+
 add_file -vhdl -lib work "../cores/pll_in133_out33_133_266.vhd"
-add_file -verilog -lib work "../cores/efb_define_def.v"
-add_file -verilog -lib work "../cores/UFM_WB.v"
+
 
 add_file -vhdl -lib work "logicbox.vhd"
 
diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index 1229532..6e34b76 100644
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -290,27 +290,13 @@ THE_UART : entity work.uart_sctrl
     DEBUG     => open
     );
 
----------------------------------------------------------------------------
--- UFM (FLASH) CONTROLLER
----------------------------------------------------------------------------      
---THE_UFM : entity UFM_control
---  generic map(
---    NO_DATAPAGES => 1,
---    UFM_STARTPAGE => "00"&x"00"
---    )
---  port map(
---    CLK => clk_33,
---    CMD => ufm_cmd, --CMD=0 => Read; CMD=1 => Write
---    GO => ufm_go,
---    BUSY => ufm_busy,
---    RESET => '0',  
---    DATA_IN => ufm_data_in, 
---    DATA_OUT => ufm_data_out,
---    DATABYTE_COUNTER => ufm_databyte_counter,
---    BUS_READY_IN => ufm_bus_ready_in,
---    BUS_READY_OUT  => ufm_bus_ready_out,
---    FLASH_ERROR => open--ufmflasherror
---    );
+--uart_rx_data <= uart_data_out;
+--uart_data_in <= uart_tx_data;
+--uart_addr    <= uart_addr_out;
+--bus_write    <= uart_write_out;
+--bus_read     <= uart_read_out;
+--uart_ready_in <= bus_ready;
+--bus_busy     <= uart_busy_out;
 
 THE_FLASH_CONTROLLER : entity generic_flash_ctrl
   generic map(
@@ -318,7 +304,8 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     )
   port map(
 
-    CLK => clk_33,
+    CLK_l => clk_33,
+    CLK_f => clk_33,
     RESET => '0',
 
     SPI_DATA_IN   => uart_data_out,
@@ -337,7 +324,7 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     LOC_READY_IN  => bus_ready,
     LOC_BUSY_OUT  => bus_busy
 
-  );
+ );
 
 
 ---------------------------------------------------------------------------
@@ -365,7 +352,7 @@ PROC_REGS : process begin
       when x"ff" => uart_tx_data <= testreg1;              
       when x"fe" => uart_tx_data <= testreg2;                    
                     
-      when others =>null;
+      when others => uart_tx_data <= x"00000000";
     end case;
     
   elsif bus_write = '1' then
@@ -452,14 +439,14 @@ PROC_REGS : process begin
 end process;
 
 
--- THE_SED : entity work.sedcheck
---   port map(
---     CLK        => clk_i,
---     ERROR_OUT  => sed_error,
---     
---     CONTROL_IN => controlsed_i,
---     DEBUG      => sed_debug
---     );
+ THE_SED : entity work.sedcheck
+   port map(
+     CLK        => clk_i,
+     ERROR_OUT  => sed_error,
+     
+     CONTROL_IN => controlsed_i,
+     DEBUG      => sed_debug
+     );
 
 --   process begin
 --     wait until rising_edge(clk_i);