From: Adrian Weber Date: Fri, 9 Nov 2018 14:02:38 +0000 (+0100) Subject: MinEvSize=0; Adding Reg 0x7110 to 0x7114 to CTS X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=67298b5dfb5dab6d5d467eaf3e37ae25859a4134;p=trbnet.git MinEvSize=0; Adding Reg 0x7110 to 0x7114 to CTS --- diff --git a/special/handler_trigger_and_data.vhd b/special/handler_trigger_and_data.vhd index 0683e83..59002a3 100644 --- a/special/handler_trigger_and_data.vhd +++ b/special/handler_trigger_and_data.vhd @@ -60,7 +60,7 @@ entity handler_trigger_and_data is TMG_TRG_ERROR_IN : in std_logic; MAX_EVENT_SIZE_IN : in std_logic_vector(15 downto 0) := x"FFFF"; - MIN_EVENT_SIZE_IN : in std_logic_vector( 7 downto 0) := x"FF"; + MIN_EVENT_SIZE_IN : in std_logic_vector( 7 downto 0) := x"00"; BUFFER_DISABLE_IN : in std_logic_vector(15 downto 0) := x"0000"; --Status Registers STAT_DATA_BUFFER_LEVEL : out std_logic_vector(DATA_INTERFACE_NUMBER*32-1 downto 0); diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd index 1e0a50f..c56259f 100644 --- a/trb_net16_hub_streaming_port_sctrl_cts.vhd +++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd @@ -361,6 +361,20 @@ signal regio_no_more_data_i: std_logic; signal regio_unknown_addr_i: std_logic; signal external_send_reset_long : std_logic; signal external_send_reset_timer : std_logic; + +signal max_event_size : std_logic_vector(15 downto 0); +signal min_event_size : std_logic_vector( 7 downto 0); +signal buffer_disable : std_logic_vector(15 downto 0); +signal new_max_size : std_logic_vector(15 downto 0); + + signal info_rd_nack : std_logic; + signal info_wr_nack : std_logic; + +signal info_registers : std_logic_vector_array_32(0 to 4); + +signal info_rx : CTRLBUS_RX; +signal info_tx : CTRLBUS_TX; + begin --------------------------------------------------------------------- @@ -907,6 +921,10 @@ begin FEE_DATA_ALMOST_FULL_OUT => open, TMG_TRG_ERROR_IN => '0', + MAX_EVENT_SIZE_IN => max_event_size, + MIN_EVENT_SIZE_IN => min_event_size, + BUFFER_DISABLE_IN => buffer_disable, + --Status Registers STAT_DATA_BUFFER_LEVEL => stat_data_buffer_level, STAT_HEADER_BUFFER_LEVEL => stat_header_buffer_level, @@ -943,7 +961,7 @@ begin if rising_edge(CLK) then dbuf_unknown_addr <= '0'; dbuf_dataready <= '0'; - tbuf_dataready <= tbuf_read_enable; + --tbuf_dataready <= tbuf_read_enable; if dbuf_read_enable = '1' then tmp := to_integer(unsigned(dbuf_addr)); if tmp < DATA_INTERFACE_NUMBER then @@ -957,7 +975,9 @@ begin end if; end process; - + + + -- process(REGIO_COMMON_STAT_REG_IN, debug_ipu_handler_i,common_ctrl_reg_i, common_stat_reg_i) -- begin -- common_stat_reg_i(8 downto 0) <= REGIO_COMMON_STAT_REG_IN(8 downto 0); @@ -1034,7 +1054,8 @@ begin end if; end process; -COMMON_STAT_REGS <= common_stat; +COMMON_STAT_REGS <= common_stat; + --------------------------------------------------------------------------- -- RegIO Bus Handler --------------------------------------------------------------------------- @@ -1042,7 +1063,7 @@ COMMON_STAT_REGS <= common_stat; generic map( PORT_NUMBER => 7, PORT_ADDRESSES => (0 => x"8000", 1 => x"7100", 2 => x"7110", 3 => x"7200", 4 => x"7201", 5 => x"7202", 6 => x"7300", others => x"0000"), - PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 0, 3 => 0, 4 => 0, 5 => 0, 6 => 5, others => 0) + PORT_ADDR_MASK => (0 => 15, 1 => 4, 2 => 3, 3 => 0, 4 => 0, 5 => 0, 6 => 5, others => 0) ) port map( CLK => CLK, @@ -1061,66 +1082,66 @@ COMMON_STAT_REGS <= common_stat; --Fucking Modelsim wants it like this... BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT, BUS_READ_ENABLE_OUT(1) => dbuf_read_enable, - BUS_READ_ENABLE_OUT(2) => tbuf_read_enable, + BUS_READ_ENABLE_OUT(2) => info_rx.read,--tbuf_read_enable, BUS_READ_ENABLE_OUT(3) => read_enable(3), BUS_READ_ENABLE_OUT(4) => read_enable(4), BUS_READ_ENABLE_OUT(5) => read_enable(5), BUS_READ_ENABLE_OUT(6) => stat_buffer_read, BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT, BUS_WRITE_ENABLE_OUT(1) => dummy(0), - BUS_WRITE_ENABLE_OUT(2) => write_enable(2), + BUS_WRITE_ENABLE_OUT(2) => info_rx.write,--write_enable(2), BUS_WRITE_ENABLE_OUT(3) => write_enable(3), BUS_WRITE_ENABLE_OUT(4) => write_enable(4), BUS_WRITE_ENABLE_OUT(5) => write_enable(5), BUS_WRITE_ENABLE_OUT(6) => write_enable(6), BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT, BUS_DATA_OUT(63 downto 32) => dummy(33 downto 2), - BUS_DATA_OUT(95 downto 64) => dummy(65 downto 34), + BUS_DATA_OUT(95 downto 64) => info_rx.data,--dummy(65 downto 34), BUS_DATA_OUT(191 downto 96) => dummy(191 downto 96), BUS_DATA_OUT(223 downto 192)=> dummy(291 downto 260), BUS_ADDR_OUT(15 downto 0) => REGIO_ADDR_OUT, BUS_ADDR_OUT(19 downto 16) => dbuf_addr, BUS_ADDR_OUT(31 downto 20) => dummy(77 downto 66), - BUS_ADDR_OUT(47 downto 32) => dummy(93 downto 78), + BUS_ADDR_OUT(47 downto 32) => info_rx.addr,--dummy(93 downto 78), BUS_ADDR_OUT(95 downto 48) => dummy(242 downto 195), BUS_ADDR_OUT(100 downto 96)=> stat_buffer_address, BUS_ADDR_OUT(111 downto 101)=> dummy(259 downto 249), BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT, BUS_TIMEOUT_OUT(1) => dummy(94), - BUS_TIMEOUT_OUT(2) => dummy(95), + BUS_TIMEOUT_OUT(2) => info_rx.timeout,--dummy(95), BUS_TIMEOUT_OUT(3) => dummy(192), BUS_TIMEOUT_OUT(4) => dummy(193), BUS_TIMEOUT_OUT(5) => dummy(194), BUS_TIMEOUT_OUT(6) => dummy(243), BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN, BUS_DATA_IN(63 downto 32) => dbuf_data_in, - BUS_DATA_IN(95 downto 64) => stat_header_buffer_level, + BUS_DATA_IN(95 downto 64) => info_tx.data,--stat_header_buffer_level, BUS_DATA_IN(191 downto 96) => stat_handler_i(95 downto 0), BUS_DATA_IN(223 downto 192)=> stat_buffer_i, BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN, BUS_DATAREADY_IN(1) => dbuf_dataready, - BUS_DATAREADY_IN(2) => tbuf_dataready, + BUS_DATAREADY_IN(2) => info_tx.ack or info_tx.rack,--tbuf_dataready, BUS_DATAREADY_IN(3) => last_read_enable(3), BUS_DATAREADY_IN(4) => last_read_enable(4), BUS_DATAREADY_IN(5) => last_read_enable(5), BUS_DATAREADY_IN(6) => stat_buffer_ready, BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN, BUS_WRITE_ACK_IN(1) => '0', - BUS_WRITE_ACK_IN(2) => '0', + BUS_WRITE_ACK_IN(2) => info_tx.ack or info_tx.wack,--'0', BUS_WRITE_ACK_IN(3) => '0', BUS_WRITE_ACK_IN(4) => '0', BUS_WRITE_ACK_IN(5) => '0', BUS_WRITE_ACK_IN(6) => '0', BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN, BUS_NO_MORE_DATA_IN(1) => '0', - BUS_NO_MORE_DATA_IN(2) => '0', + BUS_NO_MORE_DATA_IN(2) => info_tx.nack,--'0', BUS_NO_MORE_DATA_IN(3) => '0', BUS_NO_MORE_DATA_IN(4) => '0', BUS_NO_MORE_DATA_IN(5) => '0', BUS_NO_MORE_DATA_IN(6) => '0', BUS_UNKNOWN_ADDR_IN(0) => REGIO_UNKNOWN_ADDR_IN, BUS_UNKNOWN_ADDR_IN(1) => dbuf_unknown_addr, - BUS_UNKNOWN_ADDR_IN(2) => last_write_enable(2), + BUS_UNKNOWN_ADDR_IN(2) => info_tx.unknown,--last_write_enable(2), BUS_UNKNOWN_ADDR_IN(3) => last_write_enable(3), BUS_UNKNOWN_ADDR_IN(4) => last_write_enable(4), BUS_UNKNOWN_ADDR_IN(5) => last_write_enable(5), @@ -1132,6 +1153,59 @@ COMMON_STAT_REGS <= common_stat; TIMER_TICKS_OUT <= timer_ticks; +--------------------------------------------------------------------------- +-- registers 0x7110 ff. +--------------------------------------------------------------------------- + + THE_HANDLER_INFO_REGS : bus_register_handler + generic map( + BUS_LENGTH => 5 + ) + port map( + RESET => RESET, + CLK => CLK, + DATA_IN => info_registers, + READ_EN_IN => info_rx.read, + WRITE_EN_IN => '0', + ADDR_IN(2 downto 0) => info_rx.addr(2 downto 0), + ADDR_IN(6 downto 3) => "0000", + DATA_OUT => info_tx.data, + DATAREADY_OUT => info_tx.rack, + UNKNOWN_ADDR_OUT => info_rd_nack + ); + + info_tx.unknown <= info_rd_nack or info_wr_nack; + info_registers(0) <= stat_header_buffer_level; + info_registers(1) <= std_logic_vector(to_unsigned((2**RDO_DATA_BUFFER_DEPTH-RDO_DATA_BUFFER_FULL_THRESH-1),16)) & max_event_size; + info_registers(2) <= std_logic_vector(to_unsigned(RDO_DATA_BUFFER_FULL_THRESH,16)) + & std_logic_vector(to_unsigned(RDO_DATA_BUFFER_DEPTH,8)) + & std_logic_vector(to_unsigned(DATA_INTERFACE_NUMBER,8)); + info_registers(3) <= std_logic_vector(to_unsigned(c_YES,1)) --TRIGGER_RELEASE_AFTER_DATA + & "0000000" + & std_logic_vector(to_unsigned(RDO_HEADER_BUFFER_FULL_THRESH,16)) + & std_logic_vector(to_unsigned(RDO_HEADER_BUFFER_DEPTH,8)); + info_registers(4) <= x"00" & min_event_size & buffer_disable; + + proc_maxeventsize : process begin + wait until rising_edge(CLK); + info_tx.wack <= '0'; + info_wr_nack <= info_rx.write; + if RESET = '1' then + max_event_size <= std_logic_vector(to_unsigned((2**RDO_DATA_BUFFER_DEPTH-RDO_DATA_BUFFER_FULL_THRESH-1),16)); + buffer_disable <= (others => '0'); + min_event_size <= (others => '0'); + elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "001" then + max_event_size <= info_rx.data(15 downto 0); + info_tx.wack <= '1'; + info_wr_nack <= '0'; + elsif info_rx.write = '1' and info_rx.addr(2 downto 0) = "100" then + buffer_disable <= info_rx.data(15 downto 0); + min_event_size <= info_rx.data(23 downto 16); + info_tx.wack <= '1'; + info_wr_nack <= '0'; + end if; + end process; + --------------------------------------------------------------------- -- Debug ---------------------------------------------------------------------