From: Cahit Date: Mon, 26 Jan 2015 15:27:25 +0000 (+0100) Subject: channel buffer limit control register explanation is added X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6747dabebad216c9553b83a908e098b50a1a8dcd;p=daqdocu.git channel buffer limit control register explanation is added --- diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex index 0bebb06..0ce0c49 100644 --- a/trb3/TdcSlowControl.tex +++ b/trb3/TdcSlowControl.tex @@ -2,76 +2,68 @@ A set of control registers are assigned in order to access the basic controls, edit the features and debug information of the TDC. A detailed explanation of the control registers are given in Table \ref{tab:tdcControlReg}. -\begin{table}[htbp] - \begin{center} - \begin{tabularx}{\textwidth}{|c|l|c|L|} - \hline - Address & \multicolumn{1}{c|}{Name} & Bits - & \multicolumn{1}{c|}{Explanation}\\ - - \hline \hline - \multirow{19}{*}{0xc800} & \multirow{19}{*}{Basic controls} - & 3-0 & Enables different signals to the HPLA* output for debugging -with logic analyser (For more details see Table -\ref{tab:tdcControlRegBasicLA}).\\ - & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug -words are sent after every trigger (see \ref{sec:tdcDebug}).\\ - & & 5 & Enables the \textit{Light Mode}. No header and reference channel -information is sent if there are no recorded hits. Works only in the free -streaming mode (trigger window off)\\ - & & 7-6 & reserved.\\ - & & 8 & Resets the internal counters (active high).\\ - & & 11-9 & reserved.\\ - & & 12 & Used to select the trigger mode. \textbf{0:} with trigger mode; -\textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}). -This feature is disabled after tdc\_v2.0.\\ - & & 13 & Used to reset the coarse counters. Setting this bit signals for -the coarse counter reset but the action will take place with the arrival of the -next valid trigger in order to synchronise the coarse counters in a large -system.\\ - & & 27-14 & reserved.\\ - & & 31-28 & Used to divide the calibration hit frequency.\\ - & & & $Freq_{hit}=2.5~MHz/2^n$ (Oscillator frequency is increased to -20~MHz after tdc\_v2.0.1\\ +\begin{center} +\begin{longtable}{|l|l|l|p{7.6cm}|} +\caption{The control registers of the TDC. Note that these registers have been moved from 0xc0\ldots0xc8 at the beginning of 2013.} +\label{tab:tdcControlReg}\\ + +\hline \multicolumn{1}{|c|}{\textbf{Address}} & \multicolumn{1}{c|}{\textbf{Name}} & \multicolumn{1}{c|}{\textbf{Bits}} & \multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline +\endfirsthead + +\multicolumn{4}{c}% +{{\bfseries \tablename\ \thetable{} -- continued from previous page}} \\ +\hline \multicolumn{1}{|c|}{\textbf{Address}} & +\multicolumn{1}{c|}{\textbf{Name}} & +\multicolumn{1}{c|}{\textbf{Bits}} & +\multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline +\endhead + +\hline \multicolumn{4}{|r|}{Continued on next page} \\ \hline +\endfoot + +\hline \hline +\endlastfoot + + 0xc800 & Basic controls & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\ + & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\ + & & 5 & Enables the \textit{Light Mode}. No header and reference channel information is sent if there are no recorded hits. Works only in the free streaming mode (trigger window off)\\ + & & 7-6 & reserved.\\ + & & 8 & Resets the internal counters (active high).\\ + & & 11-9 & reserved.\\ + & & 12 & Used to select the trigger mode. \textbf{0:} with trigger mode; \textbf{1:} trigger-less mode (For more details see \ref{sec:tdcTrigWin}). This feature is disabled after tdc\_v2.0.\\ + & & 13 & Used to reset the coarse counters. Setting this bit signals for the coarse counter reset but the action will take place with the arrival of the next valid trigger in order to synchronise the coarse counters in a large system.\\ + & & 27-14 & reserved.\\ + & & 31-28 & Used to divide the calibration hit frequency.\\ + & & & $Freq_{hit}=2.5~MHz/2^n$ (Oscillator frequency is increased to 20~MHz after tdc\_v2.0.1\\ \hline - \multirow{10}{*}{0xc801} & \multirow{10}{*}{Trigger window} - & 10-0 & Defines the trigger window width before the trigger with -granularity of 5~ns. Minimum value is x"000".\\ - & & 15-11 & reserved.\\ - & & 26-16 & Defines the trigger window width after the trigger with -granularity of 5~ns. \textbf{ATTENTION! Minimum value can be set is x"00f".}\\ - & & 30-27 & reserved.\\ - & & 31 & Enables trigger window feature.\\ + 0xc801 & Trigger window & 10-0 & Defines the trigger window width before the trigger with granularity of 5~ns. Minimum value is x"000".\\ + & & 15-11 & reserved.\\ + & & 26-16 & Defines the trigger window width after the trigger with granularity of 5~ns. \textbf{ATTENTION! Minimum value can be set is x"00f".}\\ + & & 30-27 & reserved.\\ + & & 31 & Enables trigger window feature.\\ \hline - 0xc802 & Channel enable 1 - & 31-0 & Enable signals for the channels 1-32.\\ + 0xc802 & Channel enable 1 & 31-0 & Enable signals for the channels 1-32.\\ \hline - 0xc803 & Channel enable 2 - & 31-0 & Enable signals for the channels 33-64.\\ + 0xc803 & Channel enable 2 & 31-0 & Enable signals for the channels 33-64.\\ \hline - \multirow{8}{*}{0xc804} & \multirow{8}{*}{Data transfer limit} - & 7-0 & Defines \# of data words per channel to be read-out. Set it to -0x80 for full readout. \textbf{ATTENTION! This conrol is implemented only for -debug readons. With this limit the earliest hit information is read out. If you -wish to get hits close to the trigger (latest hits) please use the trigger -window feature.}\\ - & & 31-8 & reserved.\\ + 0xc804 & Data transfer limit & 7-0 & Defines \# of data words per channel to be read-out. Set it to 0x80 for full readout. \textbf{ATTENTION! This conrol is implemented only for debug readons. With this limit the earliest hit information is read out. If you wish to get hits close to the trigger (latest hits) please use the trigger window feature.}\\ + & & 31-8 & reserved.\\ \hline -% \multirow{3}{*}{0xc805} & \multirow{3}{*}{TDC channel trigger} & 6-0 & The input signal on the defined channel is forwarded to the CTS for triggering.\\ -% & & 31-7 -% & reserved.\\ -% \hline - \end{tabularx} - \caption{The control registers of the TDC. Note that these registers - have been moved from 0xc0\ldots0xc8 at the beginning of 2013.} - \label{tab:tdcControlReg} - \end{center} -\end{table} + 0xc805 & TDC channel & 6-0 & Defines the size of the channel buffer size (from tdc\_v2.1).\\ + & buffer limit & & Possible values 0-126\\ + & & 31-7 & reserved.\\ + \hline + +\end{longtable} +\end{center} + + + \begin{table}[htbp] \begin{center} @@ -165,82 +157,84 @@ window feature.}\\ \end{center} \end{table} -\begin{table}[htbp] - \begin{center} - \begin{tabularx}{\textwidth}{|c|p{3.5cm}|c|L|} - \hline - Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\ - \hline \hline - \multirow{8}{*}{0xc100} & \multirow{8}{3.5cm}{Basic controls} & 3-0 & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\ - & & 7-4 & Debug word of the TDC writeout FSM (see \ref{tab:tdcWriteoutFsm})\\ - & & 15-8 & Implemented channel number.\\ - & & 16 & Reference time synchronised to 100~MHz TrbNet clock.\\ - & & 27-17 & reserved\\ - & & 31-28 & Trigger type\\ \hline +\newpage +The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1}. +\vspace{-0.5cm} - 0xc101 & Empty channels 1 & 31-0 & Empty signals of the channels 32-1\\ \hline - 0xc102 & Empty channels 2 & 31-0 & Empty signals of the channels 64-33\\ \hline - \multirow{7}{*}{0xc103} & \multirow{7}{3.5cm}{Trigger window controls} & 10-0 & Trigger window width before the trigger with granularity of 5~ns\\ - & & 15-11 & reserved\\ - & & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\ - & & 30-27 & reserved\\ - & & 31 & Trigger window status (1:enabled 0:disabled)\\ \hline - \multirow{2}{*}{0xc104} & \multirow{2}{3.5cm}{Trigger number} & 23-0 & Number of valid triggers received\\ - & & 31-24 & reserved\\ \hline - \multirow{2}{*}{0xc105} & \multirow{2}{3.5cm}{Valid timing trigger number} & 23-0 & Number of valid timing triggers received\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc106} & \multirow{3}{3.5cm}{Valid NOtiming trigger number} & 23-0 & Number of valid triggers received which are not timing triggers\\ - & & 31-24 & reserved\\ \hline - \multirow{2}{*}{0xc107} & \multirow{2}{3.5cm}{Invalid trigger number} & 23-0 & Number of invalid triggers received\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc108} & \multirow{3}{3.5cm}{Multi timing trigger number} & 23-0 & Number of multi timing triggers (triggers received before trigger is released) received\\ - & & 31-24 & reserved\\ \hline - \multirow{4}{*}{0xc109} & \multirow{4}{3.5cm}{Spurious trigger number} & 23-0 & Number of spurious triggers received (in case of timing trigger is validated although it was a timing-trigger-less trigger)\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc10a} & \multirow{3}{3.5cm}{Wrong readout number} & 23-0 & Number of wrong readouts due to spurious triggers\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc10b} & \multirow{3}{3.5cm}{Spike number} & 23-0 & Number of spikes (pulses narrower than 40~ns) detected at the timing trigger input\\ - & & 31-24 & reserved\\ \hline - \end{tabularx} - \caption{The status registers of the TDC.} - \label{tab:tdcStatusReg1} - \end{center} -\end{table} +\begin{center} +\begin{longtable}{|l|p{2.8cm}|r|p{7.6cm}|} +\caption{The status registers of the TDC.} +\label{tab:tdcStatusReg1}\\ -\begin{table}[htbp] - \begin{center} - \begin{tabularx}{\textwidth}{|c|p{3.5cm}|c|L|} - \hline - Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\ - \hline \hline - \multirow{3}{*}{0xc10c} & \multirow{3}{3.5cm}{Idle time} & 23-0 & Total time length, that the readout FSM waited in the idle state (with granularity of 10~ns)\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc10d} & \multirow{3}{3.5cm}{Wait time} & 23-0 & Total time length, that the readout FSM waited in the wait states (with granularity of 10~ns)\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc10e} & \multirow{3}{3.5cm}{Total empty channels} & 23-0 & Number of empty channels since the last reset signal\\ - & & 31-24 & reserved\\ \hline - \multirow{2}{*}{0xc10f} & \multirow{2}{3.5cm}{Release number} & 23-0 & Number of release signals sent\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc110} & \multirow{3}{3.5cm}{Readout time} & 23-0 & Total time length, that the readout occured (with granularity of 10~ns)\\ - & & 31-24 & reserved\\ \hline - \multirow{3}{*}{0xc111} & \multirow{3}{3.5cm}{Timeout number} & 23-0 & Number of timeouts detected (too long delay after the timing trigger)\\ - & & 31-24 & reserved\\ \hline - \multirow{2}{*}{0xc112} & \multirow{2}{3.5cm}{Finished number} & 23-0 & Number of sent finished signals\\ - & & - 31-24 & reserved\\ \hline - \multirow{2}{*}{0xc113} & \multirow{2}{3.5cm}{READ FSM history} & \multirow{2}{*}{31-0} - & History register for the last 8 states of the READ FSM debug word.\\ \hline - \multirow{2}{*}{0xc114} & \multirow{2}{3.5cm}{WRITE FSM history} & \multirow{2}{*}{31-0} - & History register for the last 8 states of the WRITE FSM debug word.\\ \hline +\hline \multicolumn{1}{|c|}{\textbf{Address}} & \multicolumn{1}{c|}{\textbf{Name}} & \multicolumn{1}{c|}{\textbf{Bits}} & \multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline +\endfirsthead - \end{tabularx} - \caption{The status registers of the TDC. (Continue)} - \label{tab:tdcStatusReg2} - \end{center} -\end{table} +\multicolumn{4}{c}% +{{\bfseries \tablename\ \thetable{} -- continued from previous page}} \\ +\hline \multicolumn{1}{|c|}{\textbf{Address}} & +\multicolumn{1}{c|}{\textbf{Name}} & +\multicolumn{1}{c|}{\textbf{Bits}} & +\multicolumn{1}{c|}{\textbf{Explanation}} \\ \hline +\endhead + +\hline \multicolumn{4}{|r|}{Continued on next page} \\ \hline +\endfoot + +\hline \hline +\endlastfoot + + 0xc100 & Basic controls & 3-0 & Debug word of the TDC readout FSM (see \ref{tab:tdcReadoutFsm})\\ + & & 7-4 & Debug word of the TDC writeout FSM (see \ref{tab:tdcWriteoutFsm})\\ + & & 15-8 & Implemented channel number.\\ + & & 16 & Reference time synchronised to 100~MHz TrbNet clock.\\ + & & 27-17 & reserved\\ + & & 31-28 & Trigger type\\ \hline + + 0xc101 & Empty channels 1 & 31-0 & Empty signals of the channels 32-1\\ \hline + 0xc102 & Empty channels 2 & 31-0 & Empty signals of the channels 64-33\\ \hline + 0xc103 & Trigger window controls & 10-0 & Trigger window width before the trigger with granularity of 5~ns\\ + & & 15-11 & reserved\\ + & & 26-16 & Trigger window width after the trigger with granularity of 5~ns\\ + & & 30-27 & reserved\\ + & & 31 & Trigger window status (1:enabled 0:disabled)\\ \hline + 0xc104 & Trigger number & 23-0 & Number of valid triggers received\\ + & & 31-24 & reserved\\ \hline + 0xc105 & Valid timing trigger number & 23-0 & Number of valid timing triggers received\\ + & & 31-24 & reserved\\ \hline + 0xc106 & Valid NOtiming trigger number & 23-0 & Number of valid triggers received which are not timing triggers\\ + & & 31-24 & reserved\\ \hline + 0xc107 & Invalid trigger number & 23-0 & Number of invalid triggers received\\ + & & 31-24 & reserved\\ \hline + 0xc108 & Multi timing trigger number & 23-0 & Number of multi timing triggers (triggers received before trigger is released) received\\ + & & 31-24 & reserved\\ \hline + 0xc109 & Spurious trigger number & 23-0 & Number of spurious triggers received (in case of timing trigger is validated although it was a timing-trigger-less trigger)\\ + & & 31-24 & reserved\\ \hline + 0xc10a & Wrong readout number & 23-0 & Number of wrong readouts due to spurious triggers\\ + & & 31-24 & reserved\\ \hline + 0xc10b & Spike number & 23-0 & Number of spikes (pulses narrower than 40~ns) detected at the timing trigger input\\ + & & 31-24 & reserved\\ \hline + 0xc10c & Idle time & 23-0 & Total time length, that the readout FSM waited in the idle state (with granularity of 10~ns)\\ + & & 31-24 & reserved\\ \hline + 0xc10d & Wait time & 23-0 & Total time length, that the readout FSM waited in the wait states (with granularity of 10~ns)\\ + & & 31-24 & reserved\\ \hline + 0xc10e & Total empty channels & 23-0 & Number of empty channels since the last reset signal\\ + & & 31-24 & reserved\\ \hline + 0xc10f & Release number & 23-0 & Number of release signals sent\\ + & & 31-24 & reserved\\ \hline + 0xc110 & Readout time & 23-0 & Total time length, that the readout occured (with granularity of 10~ns)\\ + & & 31-24 & reserved\\ \hline + 0xc111 & Timeout number & 23-0 & Number of timeouts detected (too long delay after the timing trigger)\\ + & & 31-24 & reserved\\ \hline + 0xc112 & Finished number & 23-0 & Number of sent finished signals\\ + & & 31-24 & reserved\\ \hline + 0xc113 & READ FSM history & 31-0 & History register for the last 8 states of the READ FSM debug word.\\ \hline + 0xc114 & WRITE FSM history & 31-0 & History register for the last 8 states of the WRITE FSM debug word.\\ \hline + + + +\end{longtable} +\end{center} -The status registers of the TDC are explained in Table \ref{tab:tdcStatusReg1} -and Table \ref{tab:tdcStatusReg2}. \newpage \subsubsection{Hit Scaler Registers}