From: Andreas Neiser Date: Thu, 10 Oct 2013 10:47:40 +0000 (+0200) Subject: First draft of TWEPP 2013, including figures X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=675935a61972816f5adf2c2b6ab8a279a1043b27;p=publication.git First draft of TWEPP 2013, including figures --- diff --git a/2013-twepp-neiser-trb3_applications/gfx b/2013-twepp-neiser-trb3_applications/gfx new file mode 120000 index 0000000..7edfd1a --- /dev/null +++ b/2013-twepp-neiser-trb3_applications/gfx @@ -0,0 +1 @@ +../figures \ No newline at end of file diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf index cf43dd8..a3b14e5 100644 Binary files a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf and b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.pdf differ diff --git a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex index 3fe212c..b79a7ec 100644 --- a/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex +++ b/2013-twepp-neiser-trb3_applications/twepp2013-neiser-trb3.tex @@ -40,7 +40,7 @@ E-mail: \email{neiser@kph.uni-mainz.de} total. One central FPGA provides flexible trigger functionality and GbE connectivity including powerful slow control. We present recent users' applications of this platform following the COME\&KISS - principle: Successful test beamtimes at CERN (CBM), in Juelich and + principle: Successful test beamtimes at CERN (CBM), in J\"{u}lich and Mainz with an FPGA-based discriminator board (PaDiWa), a charge-to-width FEE board with high dynamic range, read-out of the n-XYTER ASIC and software for data unpacking and TDC calibration in @@ -50,91 +50,298 @@ E-mail: \email{neiser@kph.uni-mainz.de} Digital electronic circuits; Data acquisition circuits} +\usepackage[poorman]{cleveref} + \begin{document} \section{Introduction} -The 4+1 FPGA board "TRB3" can serve various applications in -experimental particle physics and beyond due to its general-purpose -design. It uses FPGAs as complex commercial electronic components -while realizing the remaining auxiliary parts with simple standard -components. Consequently, the board provides flexible connectivity by -eight SFP ports and mezzanine extensions for every FPGA including a -high pin-out for the peripheral FPGAs. We call this concept COME\&KISS: -COMplex COMmercial Elements \& Keep It Small and Simple. This ensures a -wide range of applications in data acquisition scenarios as well as a -long-term maintainability of the platform. +The $4+1$ FPGA board ``TRB3'' (\cref{fig:trb3}a) can serve various +applications in experimental particle physics and beyond due to its +general-purpose design. It uses Lattice ECP3-150EA FPGAs as complex +commercial electronic components while realizing the remaining +auxiliary parts with simple standard components. Consequently, the +board provides flexible connectivity by eight SFP ports and mezzanine +extensions for every FPGA including a high pin-out for the peripheral +FPGAs. We call this concept COME\&KISS: COMplex COMmercial Elements \& +Keep It Small and Simple. This ensures a wide range of applications in +data acquisition scenarios as well as a long-term maintainability of +the platform. + +\begin{figure}[tbp] %figures (and tables) should go top or bottom of + % the page where they are first cited or in + % subsequent pages + \centering + \begin{minipage}{0.4\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/trb3/trb3-alone}\\ + (a) + \end{minipage} + \quad + \begin{minipage}{0.5\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/trb3/cts-web}\\ + (b) + \end{minipage} + \caption{(a) The TRB3 without any mezzazine cards. (b) Screenshot + showing the Central Trigger System webinterface.} + \label{fig:trb3} +\end{figure} Usually, in each of the four peripheral FPGAs a tapped delay line TDC -is implemented with <20ps RMS time precision between two channels -providing 64 channels plus one reference channel. The TDCs are used -for leading edge measurements or by using the TDC channels in pairs, -one can additionally extract the width of the digital pulse. The -central FPGA serves as a flexible central trigger system and manages -slow control and read-out of the peripheral FPGAs over a single -gigabit Ethernet connection. The project provides a comfortable, -robust and modular software environment, ranging from low-level -register access to the FPGA firmwares on the command line to -high-level control via web2.0 technologies. This is complemented by -comprehensive specifications and documentation. - -\section{Precise TDC in FPGA} - -Based on ref.~\cite{ugur-twepp-tdc}. - - -\section{Software Environment} - -Based on ref.~\cite{michel-twepp-hades-daq}. +is implemented with $<20$\,ps RMS time precision between two channels +providing $64$ channels plus one reference channel, see +\cref{sec:tdc}. The TDCs are typically used for leading edge +measurements or---by using the TDC channels in pairs---one can +additionally extract the width of the digital pulse. The central FPGA +serves as a flexible central trigger system and manages slow control +and read-out of the peripheral FPGAs over a single gigabit Ethernet +connection. Thus, only $48$\,V supply voltage and a desktop computer +are needed for a complete data acquisition system. + +The project provides a comfortable, robust and modular software +environment, ranging from low-level register access to the FPGA +firmwares on the command line to high-level control via web2.0 +technologies, see \cref{sec:software}. This is complemented by +comprehensive specifications and documentation \cite{trb-web} +provided by the large user base from the experiments HADES and PANDA +at GSI in Darmstadt, Germany. + +In \cref{sec:frontends}, existing front-ends and applications are +presented. In \cref{sec:juelich,sec:mainz}, results of two test +beamtimes are summarized in which the TRB3 platform has been +successfully deployed. + +\section{Precise Time Digitisation in FPGA}\label{sec:tdc} + +One key component of the TRB3 is the $64+1$ channel time-to-digital +converter (TDC) implemented in the peripheral FPGAs of the TRB3 with a +time precision down to $7.2$\,ps. It ``misuses'' FPGA resources (LUTs +as full-adders) as delay elements and can cope with burst hit rates of +up to $50$\,MHz. Owing to its flexible design, an application-specific +trade-off between number of channels, time precision and dead-time can +be achieved for each front-end design. Implementation details can be +found in \cite{ugur-twepp2011} and first applications are described in +\cite{ugur-twepp2012}. + +\section{Software Environment}\label{sec:software} \subsection{Central Trigger System and Slow Control} +The TRB3 firmwares as part of the HADES experiment use the TrbNet +\cite{michel-twepp2011} for asynchronous read-out and busy-release +scheme trigger distribution. Its configuration can be transparently +controlled via command line tools including bindings to PERL. +Furthermore, a Central Trigger System was developed +\cite{penschuck-bachelor}, which provides an user-friendly interface +with web2.0 interactivity (\cref{fig:trb3}b). The maximum trigger rate +is $700$\,kHz and owing to its modular design, external trigger +information can be easily integrated. Currently, modules for the +experiments CBM \cite{cbm-web} and A2@MAMI \cite{a2-web} decoding the +trigger event numbers are available. + \subsection{Data Stream Unpacker and TDC Delay Line Calibration} -\section{Front-end Electronics} - -To convert the analog signals from the detector to digital pulses -suitable for the TDC, the front-end electronics board PaDiWa was -designed using the differential input buffers of an FPGA as -discriminators with a PWM generated voltage as a variable threshold. -However, the charge information of the pulse extracted from time over -threshold is usually not precise enough for calorimeters. Thus, the -leading edge measurement can be complemented by a modified Wilkinson -ADC circuit, which encodes the charge in the width of the digital -pulse delivered to the TDC. A proof-of-concept board was successfully -tested and a version with an improved dynamic range is currently -designed. Both approaches follow again the COME\&KISS principle, -already enabling other groups to use the existing FEE boards without -major modifications. The overall reliability, flexibility and -performance of this platform was proven in three test beamtimes with -different detectors and FEEs at CERN (CBM), in Juelich and Mainz with -up to 2400 channels, of which results are shown. +Additionally, the platform enables every user group to profit from +common software developments, such as a ``standalone'' ROOT unpacker +\cite{unpacker-web} for the TDC datastream including methods for the +calibration of the delay lines. In this case, the data is usually +acquired with the HADES DAQ software system in HLD files and +subsequently analyzed offline. There are also interfaces to DABC +\cite{dabc-web} which enables online monitoring and calibration of the +TRB3 read-out. + +Since the length of each delay line of the TDC depends highly on the +specific placing and thus routing of the elements inside the FPGA, a +proper calibration of this fine-time is necessary. This can be done +simply by assuming that each element has the same propagation delay, +but this limits the time resolution to about $1$\,ns. If one assumes +that the read-out clock is uncorrelated to the measured signals, a +\emph{flat} fine-time histogram of all detected signals is expected. +Any deviation must be due to different propagation delays and thus +each element can be calibrated appropiately (details see +\cite{ugur-twepp2011}). However, if the detector signal rate is not +sufficient (leading to insufficient statistics in the fine-time +histogram), artifical hits stemming from an uncorrelated signal source +must be additionally generated and read-out. This technique is already +available on the TRB3 and is currently under test. + +\section{Front-end Electronics}\label{sec:frontends} + +% To convert the analog signals from the detector to digital pulses +% suitable for the TDC, the front-end electronics board PaDiWa was +% designed using the differential input buffers of an FPGA as +% discriminators with a PWM generated voltage as a variable threshold. +% However, Both approaches follow again the COME\&KISS principle, +% already enabling other groups to use the existing FEE boards without +% major modifications. The overall reliability, flexibility and +% performance of this platform was proven in three test beamtimes with +% different detectors and FEEs at CERN (CBM), in Juelich and Mainz with +% up to $2400$ channels, of which results are shown. \subsection{PaDiWa: COME\&KISS Leading Edge Discriminator} -\subsection{Charge-to-width Front-end for HADES ECAL} +\begin{figure}[tbp] %figures (and tables) should go top or bottom of + % the page where they are first cited or in + % subsequent pages + \centering + \begin{minipage}{0.4\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/frontends/padiwa}\\ + (a) + \end{minipage} + \quad + \begin{minipage}{0.5\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/frontends/padiwa-schem}\\ + (b) + \end{minipage} + \caption{(a) The PaDiWa leading edge discriminator front-end. Other + versions with different analog connectors are available. (b) The + schematic for one channel showing the KISS part (FPGA excluded).} + \label{fig:padiwa} +\end{figure} + +The PaDiWa\footnote{Acronym for PANDA, DIRC, WASA.} is the first +front-end board following the COME\&KISS principle +(\cref{fig:padiwa}). It uses the LVDS input buffers of a Lattice +MachXO2 FPGA to realize a leading edge discriminator for $16$ analog +input signals. Besides that, only standard components like an $10$x +MMIC wideband amplifier and and RC low-passes to generate the +threshold voltages via PWM are used. Using test pulses with an +amplitude of $500$\,$\mu$V and a length of $6$\,ns, a time resolution +of the full system including the TRB3 of $23$\,ps was measured +\cite{ugur-twepp2012}. This front-end has been successfully used in +the test beamtimes, see \cref{sec:juelich,sec:mainz}. -\subsection{n-XYTER ASIC for HADES Pion Tracker} -Furthermore, the TRB3 can be used as an infrastructure to read out -specialized integrated solutions using the peripheral FPGAs, for -example to provide a timing reference, transport the acquired data to -the eventbuilder and slow control configuration of the chip. This was -realized for the n-XYTER ASIC. Additionally, the platform enables -every user group to profit from common software developments, such as -a ROOT unpacker for the TDC datastream including the necessary -calibration of the delay lines. +\subsection{Charge-to-width Front-end for HADES ECAL} -\section{J\"{u}lich Test Beamtime 2012} +\begin{figure}[tbp] %figures (and tables) should go top or bottom of + % the page where they are first cited or in + % subsequent pages + \centering + \begin{minipage}{0.4\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/frontends/qdc-layout}\\ + (a) + \end{minipage} + \quad + \begin{minipage}{0.4\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/frontends/qdc-schem}\\ + (b) + \end{minipage} + \caption{The Charge-to-Width front-end for HADES ECAL. (a) The + layout again illustrating the COME\&KISS principle. (b) The + corresponding schematic for one channel (excluding the FPGA)} + \label{fig:qdc} +\end{figure} + +The charge information of the pulse extracted from time over threshold +is usually not precise enough for calorimeters. Thus, the leading edge +measurement can be complemented by a modified Wilkinson ADC circuit, +which encodes the charge in the width of the digital pulse delivered +to the TDC. A proof-of-concept board was already successfully tested +and a version with an improved dynamic range is currently designed for +the HADES ECAL detector (\cref{fig:qdc}). It is based on the +experience with the PaDiWa board and provides $8$ input channels +(using in total $32$ FPGA TDC channels for two leading edges and two +trailing edges for each input channel) with a charge resolution of +$0.2$\,\% and a high dynamic range of $250$. -\section{Mainz Test Beamtime 2013} +\subsection{n-XYTER ASIC for HADES Pion Tracker} -\section{Outlook and Future Developments} +The TRB3 can also be used as an infrastructure to read out specialized +integrated solutions using the peripheral FPGAs, for example to +provide a timing reference, transport the acquired data to the +eventbuilder and slow control configuration of the chip. This was +realized for the n-XYTER ASIC, which provides the timestamp and the +pulse height of self-triggered $128$ channels. In this case, the +integration of read-out and slow control (e.\,g. trigger windows) on +the peripheral FPGA was easily achieved due to the well-documented +VHDL interfaces of the TRB3 platform. + +\section{J\"{u}lich Test Beamtime 2012}\label{sec:juelich} + +\begin{figure}[tbp] %figures (and tables) should go top or bottom of + % the page where they are first cited or in + % subsequent pages + \centering + \begin{minipage}{0.25\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/beamtimes/juelich-setup}\\ + (a) + \end{minipage} + \quad + \begin{minipage}{0.6\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/beamtimes/juelich-pattern1}\\ + \includegraphics[width=\textwidth]{gfx/beamtimes/juelich-pattern2}\\ + (b) + \end{minipage} + \caption{Results of the test beamtime in J\"{u}lich: (a) Picture of + the test setup. (b) Hit patterns of the Cherenkov rings.} + \label{fig:juelich} +\end{figure} + +The test beamtime took place in J\"{u}lich behind the TOF experiment +(\cref{fig:juelich}) in October 2012. Here, protons with a momentum of +$2.95$\,GeV and a rate of $10^7$\,Hz were scattered at a target and +detected in two different DIRC detectors. Additionally, different +multi-anodes PMTs were tested. In total, 10 TRB3s with PaDiWa +front-ends were used providing $2400$ channels in total. It was the +largest system of TRB3s used in a test beamtime so far and has worked +successfully. + +\section{Mainz Test Beamtime 2013}\label{sec:mainz} + +\begin{figure}[tbp] %figures (and tables) should go top or bottom of + % the page where they are first cited or in + % subsequent pages + \centering + \begin{minipage}{0.25\linewidth} + \centering + \includegraphics[width=\textwidth]{gfx/beamtimes/mainz-setup}\\ + (a) + \end{minipage} + \quad + \begin{minipage}{0.7\linewidth} + \centering + \includegraphics[height=0.47\textwidth]{gfx/beamtimes/mainz-pattern30}\quad + \includegraphics[height=0.47\textwidth]{gfx/beamtimes/mainz-pattern33}\\ + (b) + \end{minipage} + \caption{Results of the test beamtime in Mainz 2013: (a) Picture of + the test setup with the tower of 4 TRB3s. (b) Hit patterns at different incident + angles and with different discriminator boards.} + \label{fig:mainz} +\end{figure} + +This most recent test beamtime took place in July 2013 at the MAMI-B +microtron in Mainz (electron accelarator) with an beam energy of +$855$\,MeV for the development of the Barrel DIRC detector at PANDA +(\cref{fig:mainz}). In total, 4 TRB3s with TDC implementations were +used with two different discriminator front-ends: The PaDiWa and the +NINO ASIC. It turned out that the difficult threshold setting for the +PaDiWa lead to worse results compared to the NINO ASIC. However, the +TRB3 provided a stable platform for a successful test beamtime. + +\section{Outlook and Future Developments}\label{sec:outlook} + +Finally, we present some planned or ongoing extensions of the +platform. The detection of leading and trailing edge in a single TDC +channel, which doubles the number of channels per board for timestamp +and width measurements. This feature is highly desired for the +described charge-to-width front-end. The temperature stability of the +PaDiWa thresholds and of the TDC calibration is currently +investigated. There are also two further front-end developments: +Integration of the MuPix ASIC for the PANDA luminosity detector and +the SPADIC ASIC for a TPC in Mainz. Since both ASICs use the CBMnet +protocol, an implementation of CBMnet on the TRB3 was started. +Furthermore, an extension of TrbNet with defined propagation delays of +trigger signals for PANDA is being developed and tested. -Finally, we present planned extensions of the platform: The detection -of leading and trailing edge in a single TDC channel, which doubles -the number of channels per board for timestamp and width measurements, -and the integration in data acquisition frameworks such as DABC. % \paragraph{Paragraph.} Lorem ipsum dolor sit amet, consectetur @@ -204,18 +411,47 @@ A.N. receives a Fellowship through GRK Symmetry Breaking (DFG/GRK % Authors, % \emph{Title}, % \emph{J. Ref.} \textbf{vol} (year) page. - -\bibitem{ugur-twepp-tdc} -C. U\u{g}ur, W. Koening, J. Michel, M. Palka and M. Traxler, - \emph{Field programmable gate array based data -digitisation with commercial elements}, -\jinst{8}{2013}{C01035}. - -\bibitem{michel-twepp-hades-daq} -J. Michel, M. B\"{o}hmer, M. Kajetanowicz, G. Korcyl, -L. Maier, M. Palka, J. Stroth, A. Tarantola, M. Traxler, C. U\u{g}ur and S. Yurevich, -\emph{The upgraded HADES trigger and data acquisition system}, -\jinst{6}{2011}{C12056} +\bibitem{ugur-twepp2011} + C. U\u{g}ur, E. Bayer, N. Kurz and M. Traxler + \emph{A 16 channel high resolution (<11 ps RMS) Time-to-Digital Converter + in a Field Programmable Gate Array} + \jinst{7}{2012}{C02004}. + +\bibitem{ugur-twepp2012} + C. U\u{g}ur, W. Koening, J. Michel, M. Palka and M. Traxler, + \emph{Field programmable gate array based data + digitisation with commercial elements}, + \jinst{8}{2013}{C01035}. + +\bibitem{michel-twepp2011} + J. Michel, M. B\"{o}hmer, M. Kajetanowicz, G. Korcyl, + L. Maier, M. Palka, J. Stroth, A. Tarantola, M. Traxler, C. U\u{g}ur and S. Yurevich, + \emph{The upgraded HADES trigger and data acquisition system}, + \jinst{6}{2011}{C12056}. + +\bibitem{penschuck-bachelor} M. Penschuck, \emph{Development and + Implementation of a Central Trigger System for TrbNet-based + systems}, Bachelor thesis, Goethe-University, Frankfurt, 2012. + +\bibitem{trb-web} +The TRB3 website, \href{http://trb.gsi.de}{http://trb.gsi.de}. + +\bibitem{cbm-web} +The CBM website, +\href{http://www.fair-center.eu/for-users/experiments/cbm.html}{http://www.fair-center.eu/for-users/experiments/cbm.html}. + +\bibitem{a2-web} +The A2@MAMI website, +\href{http://wwwa2.kph.uni-mainz.de}{http://wwwa2.kph.uni-mainz.de}. + +\bibitem{unpacker-web} +The Mainz TRB3 TDC Unpacker, +\href{https://github.com/neiser/mz-unpacker}{https://github.com/neiser/mz-unpacker}. + + +\bibitem{dabc-web} +The DABC website, +\href{http://dabc.gsi.de}{http://dabc.gsi.de}. % \bibitem{bib3} diff --git a/figures/beamtimes/juelich-pattern1.jpg b/figures/beamtimes/juelich-pattern1.jpg new file mode 100644 index 0000000..283ccba Binary files /dev/null and b/figures/beamtimes/juelich-pattern1.jpg differ diff --git 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+ + + + + + + + + + + + + + + + C138 + 100n + + + + + + + + + + + + + + + + + + + + PaDiWa input stage: + 10x Amplifier + FPGA asDiscriminator + + diff --git a/figures/frontends/padiwa.jpg b/figures/frontends/padiwa.jpg new file mode 100644 index 0000000..6abd39f Binary files /dev/null and b/figures/frontends/padiwa.jpg differ diff --git a/figures/frontends/qdc-layout.pdf b/figures/frontends/qdc-layout.pdf new file mode 100644 index 0000000..d7e99a1 Binary files /dev/null and b/figures/frontends/qdc-layout.pdf differ diff --git a/figures/frontends/qdc-layout.svg b/figures/frontends/qdc-layout.svg new file mode 100644 index 0000000..cb7baba --- /dev/null +++ b/figures/frontends/qdc-layout.svg @@ -0,0 +1,748 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + 8x input + + + (MMCX) + + + + + + FPGA with + + + threshold circuit + + + + output: LVDS + + + time signals + + + 88 mm + + + 52 mm + + +  + + + attenuator & + + + fast amp + + + + + power + + + connector + + + + integrator + + + + + + + + COME + + + - + + + Part + + + + + + + + KISS + + + - + + + Part + + + voltage + + + stabilizer + + + + diff --git a/figures/frontends/qdc-schem.pdf b/figures/frontends/qdc-schem.pdf new file mode 100644 index 0000000..a2b1a7e Binary files /dev/null and b/figures/frontends/qdc-schem.pdf differ diff --git a/figures/frontends/qdc-schem.svg b/figures/frontends/qdc-schem.svg new file mode 100644 index 0000000..d41435c --- /dev/null +++ b/figures/frontends/qdc-schem.svg @@ -0,0 +1,117 @@ + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + Padiwa: attenuator/amplifier/integrator for FPGA discriminator & feedback + + + + + Wolfgang Koenig May 2013, Version 1.0 + + + + + + + + + + diff --git a/figures/trb3/cts-web.pdf b/figures/trb3/cts-web.pdf new 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