From: Jan Michel <j.michel@gsi.de>
Date: Fri, 18 Mar 2016 14:32:14 +0000 (+0100)
Subject: Minor updates to dirich design and lpf
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=67a020742e249f2ef3b896d999ce478c384afdc6;p=dirich.git

Minor updates to dirich design and lpf
---

diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf
index 18434dc..5365515 100644
--- a/dirich/dirich.lpf
+++ b/dirich/dirich.lpf
@@ -4,17 +4,7 @@ BLOCK ASYNCPATHS ;
 BLOCK RD_DURING_WR_PATHS ;
 
 
-SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
-BANK 0 VCCIO 2.5 V;
-BANK 1 VCCIO 2.5 V;
-BANK 2 VCCIO 2.5 V;
-BANK 3 VCCIO 2.5 V;
-BANK 6 VCCIO 2.5 V;
-BANK 7 VCCIO 2.5 V;
-BANK 8 VCCIO 3.3 V;
-
-
-FREQUENCY PORT CLOCK_IN        240 MHz;
+FREQUENCY PORT CLOCK_IN        200 MHz;
 FREQUENCY PORT CLOCK_CAL       33 MHz;
 
 
diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd
index 5e600f7..3893f64 100644
--- a/dirich/dirich.vhd
+++ b/dirich/dirich.vhd
@@ -50,13 +50,6 @@ entity dirich is
   attribute syn_useioff of FLASH_CS   : signal is true;
   attribute syn_useioff of FLASH_IN   : signal is true;
   attribute syn_useioff of FLASH_OUT  : signal is true;
-
-  
-  --Serdes:                                Backplane
-  --Backplane A2,A3,A0,A1                  Slave 3,4,1,2,             A0: TrbNet from backplane
-  --AddOn     C2,C3,C0,C1,B0,B1,B2,D1(B3)  Slave --,--,5,9,8,7,6,--
-  --SFP       D0,B3(D1)                                               D0: GbE, B3: TrbNet
-  
   
 end entity;
 
@@ -270,7 +263,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record
       SPI_CLK_OUT => open,
       --Header
       HEADER_IO   => hdr_io,
-      LED_DISABLE => led_off,
+      ADDITIONAL_REG(0) => led_off,
       --LCD
       LCD_DATA_IN => lcd_data,
       --ADC
diff --git a/pinout/dirich.lpf b/pinout/dirich.lpf
index 8f020b1..012f2a5 100644
--- a/pinout/dirich.lpf
+++ b/pinout/dirich.lpf
@@ -1,3 +1,13 @@
+SYSCONFIG MCCLK_FREQ=38.8 CONFIG_IOVOLTAGE=3.3 ; #BACKGROUND_RECONFIG=ON
+BANK 0 VCCIO 2.5 V;
+BANK 1 VCCIO 2.5 V;
+BANK 2 VCCIO 2.5 V;
+BANK 3 VCCIO 2.5 V;
+BANK 6 VCCIO 2.5 V;
+BANK 7 VCCIO 2.5 V;
+BANK 8 VCCIO 3.3 V;
+
+
 LOCATE COMP "INPUT[1]"  SITE "E5";
 LOCATE COMP "INPUT[2]"  SITE "F4";
 LOCATE COMP "INPUT[3]"  SITE "E4";
@@ -104,7 +114,6 @@ LOCATE COMP "SIG[2]"                           SITE "N5";
 LOCATE COMP "SIG[3]"                           SITE "M5";
 LOCATE COMP "SIG[4]"                           SITE "M4";
 LOCATE COMP "SIG[5]"                           SITE "L5";
-LOCATE COMP "SIG[6]"                           SITE "L4";
 DEFINE PORT GROUP "SIG_group" "SIG*" ;
 IOBUF GROUP  "SIG_group" IO_TYPE=LVCMOS25  DRIVE=8 BANK_VCCIO=2.5;