From: Jan Michel Date: Fri, 22 Dec 2023 09:58:23 +0000 (+0100) Subject: add missing files to beamabort design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6864f9c1fd31e3b13c0fc7284107b2033f2abcc8;p=trb3sc.git add missing files to beamabort design --- diff --git a/shutdownlogic/code/shutdown_compare.vhd b/shutdownlogic/code/shutdown_compare.vhd index a886d18..94aae67 100644 --- a/shutdownlogic/code/shutdown_compare.vhd +++ b/shutdownlogic/code/shutdown_compare.vhd @@ -9,7 +9,7 @@ library work; entity shutdown_comp is generic( - INPUTS : integer := 24; + INPUTS : integer := 32; OUTPUTS : integer := 8 ); port( @@ -17,7 +17,6 @@ generic( signal_in : in std_logic_vector(INPUTS-1 downto 0); max_number_reg : in std_logic_vector(31 downto 0); disable_reg : in std_logic_vector(31 downto 0); - processed_signal : out std_logic_vector(OUTPUTS-1 downto 0) ); end shutdown_comp; diff --git a/shutdownlogic/code/shutdown_individual.vhd b/shutdownlogic/code/shutdown_individual.vhd index ccc23e8..3947bd5 100644 --- a/shutdownlogic/code/shutdown_individual.vhd +++ b/shutdownlogic/code/shutdown_individual.vhd @@ -12,8 +12,8 @@ entity shutdown_indv is signal_in : in std_logic; int_time : in std_logic_vector (31 downto 0); max_count : in std_logic_vector (31 downto 0); - current_hits_vctr : out std_logic_vector (31 downto 0); - reset_pulse : out std_logic; + current_hits_vctr : out std_logic_vector (31 downto 0); --egal + reset_pulse : out std_logic; --egal processed_signal : out std_logic ); end shutdown_indv; @@ -27,7 +27,7 @@ architecture behave of shutdown_indv is signal ms_timer : unsigned(15 downto 0):= x"0000"; signal ms_pulse : std_logic; signal integration_time_int: unsigned(31 downto 0):= x"00000000"; --- signal current_hits_vctr: std_logic_vector (31 downto 0); + signal max_hitcount: unsigned(31 downto 0):= x"00000000"; signal hitcounter : unsigned(31 downto 0):= x"00000000"; signal hitsaver : unsigned(31 downto 0):= x"00000000"; @@ -48,13 +48,12 @@ begin integration_time_int <= unsigned(int_time(31 downto 0)); max_hitcount <= unsigned(max_count(31 downto 0)); - current_hits_vctr <= std_logic_vector(hitteller); - reset_pulse <= reset_pulse_i; + current_hits_vctr <= std_logic_vector(hitteller); --egal + reset_pulse <= reset_pulse_i; --egal PROC_SAFETYOFF: process begin -- stops the entity from sending signals before there are values recieved from the bussystem wait until rising_edge(clk_in); - -if max_hitcount = x"00000000" or integration_time_int = x"00000000" then +if max_hitcount = x"00000000" or integration_time_int = x"00000000" then -- here processed_signal <= '0'; else processed_signal <= finalout; @@ -93,7 +92,6 @@ end process; MAXHITS_ALERT: process begin wait until rising_edge(clk_in); - if hitcounter >= max_hitcount then temp_out <= '1'; else @@ -102,7 +100,7 @@ end if; end process; -POC_OUTPUT: process begin +PROC_OUTPUT: process begin wait until rising_edge(clk_in); if reset_pulse_i='1' then hitteller <= hitsaver; @@ -116,19 +114,6 @@ wait until rising_edge(clk_in); end if; end process; - -PROC_MSPUSER: process begin -- generate a pulse every 0.1 ms -wait until rising_edge (clk_in); - if ms_timer = x"2710" then -- eqals 10.000 rising edges - ms_pulse <= '1'; - ms_timer <= x"0000" ; - else - ms_timer <= ms_timer+1; - ms_pulse<='0'; - end if; -end process; - - TIMERESETPULSE: process begin -- generates a pulse every time the integration window is closed wait until rising_edge(clk_in); if timecounter >= integration_time_int then @@ -143,7 +128,16 @@ wait until rising_edge(clk_in); end if; end process; - +PROC_MSPUSER: process begin -- generate a pulse every 0.1 ms +wait until rising_edge (clk_in); + if ms_timer = x"2710" then -- eqals 10.000 rising edges + ms_pulse <= '1'; + ms_timer <= x"0000" ; + else + ms_timer <= ms_timer+1; + ms_pulse<='0'; + end if; +end process; diff --git a/shutdownlogic/code/shutdown_logic.vhd b/shutdownlogic/code/shutdown_logic.vhd index a0b5e67..e0a8de5 100644 --- a/shutdownlogic/code/shutdown_logic.vhd +++ b/shutdownlogic/code/shutdown_logic.vhd @@ -7,8 +7,8 @@ library work; entity shutdown_logic is generic( - INPUTS : integer := 24; - OUTPUTS : integer := 8 + INPUTS : integer := 32; + OUTPUTS : integer := 2 ); port( CLK : in std_logic; @@ -54,14 +54,23 @@ signal shutdown_signal: std_logic; -- signal shutdown_signal:std_logic_vector(OUTPUTS-1 downto 0); -- Signals for the Monitoring/Fifo -signal fifo_writesignal: std_logic_vector(INPUTS-1 downto 0); -signal man_readFlag: std_logic_vector(31 downto 0); -signal read_mem_Flag: std_logic_vector(INPUTS-1 downto 0); +signal fifo_writesignal: std_logic_vector(INPUTS-1 downto 0); --dieses signal aendern um gleichmaessige bins zu erhalten, wsl einfach den timer auf dieses Signal legen + + +signal man_readFlag_plot :std_logic_vector(31 downto 0):=(others => '0'); +signal man_readFlag_failsave :std_logic_vector(31 downto 0):=(others => '0'); + +--signal read_mem_Flag: std_logic_vector(INPUTS-1 downto 0); +signal read_plot_Flag: std_logic_vector(INPUTS-1 downto 0); +signal read_failsave_Flag: std_logic_vector(INPUTS-1 downto 0); -- signal fifoEmpty: std_logic; -signal fifoEmpty: std_logic_vector(INPUTS-1 downto 0); +-- signal fifoEmpty: std_logic_vector(INPUTS-1 downto 0); +signal fifo1Empty: std_logic_vector(INPUTS-1 downto 0); +signal fifo2Empty: std_logic_vector(INPUTS-1 downto 0); -- signal store_values : Array32bit:=(others => (others => '0')); -signal plot_values : Array32bit:=(others => (others => '0')); +signal plot_values : Array32bit:=(others => (others => '0')); +signal failsave_values : Array32bit:=(others => (others => '0')); -- hand over the signals between entities @@ -70,11 +79,14 @@ signal indiv_2_comp :std_logic_vector(INPUTS-1 downto 0); signal comp_2_out :std_logic_vector(OUTPUTS-1 downto 0); signal address_i : integer range 0 to 255; - - - - - +signal plotsave_timer : unsigned(31 downto 0):= x"00000000"; +signal plotsave_pulse : std_logic; +signal failsave_timer : unsigned(31 downto 0):= x"00000000"; +signal failsave_pulse : std_logic; +signal reg_plotbin : std_logic_vector (31 downto 0); +signal reg_failsavebin: std_logic_vector (31 downto 0); +signal int_plotbin : unsigned(31 downto 0):= x"00000000"; +signal int_savebin : unsigned(31 downto 0):= x"00000000"; begin @@ -91,12 +103,20 @@ begin PROC_OFFSWITCH : process (comp_2_out) begin - if register_onoff(0) = '1' then + if register_onoff(0) = '1' then --switched on shutdown_signal <= comp_2_out(0); - else + OUTPUT(0) <= not comp_2_out(0); + OUTPUT(1) <= '0'; + else --switched off + OUTPUT <= (others => '1'); shutdown_signal <= '0'; end if; end process; + +--Pulser for plotdata + + + PROC_REGS : process begin @@ -104,6 +124,9 @@ PROC_REGS : process begin BUS_TX.ack <= '0'; BUS_TX.nack <= '0'; BUS_TX.unknown <= '0'; +-- read_mem_Flag <= (others => '0'); + read_failsave_Flag <= (others => '0'); + read_plot_Flag <= (others => '0'); if BUS_RX.read = '1' then -- READ BUS_TX.ack <= '1'; @@ -132,26 +155,48 @@ PROC_REGS : process begin elsif BUS_RX.addr(11 downto 8) = x"5" then BUS_TX.data <= individual_alerts; elsif BUS_RX.addr(11 downto 8) = x"6" then + if BUS_RX.addr(7 downto 4) = x"0" then BUS_TX.data <= register_onoff; + elsif BUS_RX.addr(7 downto 4) = x"1" then + BUS_TX.data <= reg_plotbin; --size of bin + elsif BUS_RX.addr(7 downto 4) = x"2" then + BUS_TX.data <= reg_failsavebin; --size of bin + end if; elsif BUS_RX.addr(11 downto 8) = x"7" then BUS_TX.data <= signal_register; - elsif BUS_RX.addr(11 downto 8) = x"8" then - - if address_i < INPUTS then - if fifoEmpty(address_i) = '1' then - BUS_TX.nack <= '1'; - BUS_TX.ack <= '0'; - else - BUS_TX.data <= plot_values(address_i); - read_mem_Flag(address_i) <= '1'; - end if; + elsif BUS_RX.addr(11 downto 8) = x"8" then --read out the fifos - else - BUS_TX.ack <= '0'; BUS_TX.unknown <= '1' ; - end if; - elsif BUS_RX.addr(11 downto 8) = x"9" then - BUS_TX.data <= man_readFlag; + if BUS_RX.addr(7 downto 4) = x"0" then + if address_i < INPUTS then + if fifo1Empty(address_i) = '1' then + BUS_TX.nack <= '1'; + BUS_TX.ack <= '0'; + else + read_plot_Flag(address_i) <= '1'; + BUS_TX.data <= plot_values(address_i); + end if; + else + BUS_TX.ack <= '0'; BUS_TX.unknown <= '1' ; + end if; + elsif BUS_RX.addr(7 downto 4) = x"4" then + if fifo2Empty(address_i) = '1' then + BUS_TX.nack <= '1'; + BUS_TX.ack <= '0'; + else + read_failsave_Flag(address_i) <= '1'; + BUS_TX.data <= failsave_values(address_i); + end if; + else + BUS_TX.ack <= '0'; BUS_TX.unknown <= '1' ; + end if; + + elsif BUS_RX.addr(11 downto 8) = x"9" then + if BUS_RX.addr(7 downto 4) = x"0" then + BUS_TX.data <= man_readFlag_plot; + elsif BUS_RX.addr(7 downto 4) = x"1" then + BUS_TX.data <= man_readFlag_failsave; + end if; else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end if; @@ -167,18 +212,29 @@ PROC_REGS : process begin elsif BUS_RX.addr(11 downto 8) =x"1" then if address_i < INPUTS then max_count(address_i) <= BUS_RX.data; -- Write max count values - else - BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; + else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end if; elsif BUS_RX.addr(11 downto 8) = x"2" then reg_compare_1 <= BUS_RX.data; elsif BUS_RX.addr(11 downto 8) = x"3" then disableReg_compare <= BUS_RX.data; - elsif BUS_RX.addr(11 downto 8) = x"6" then -- write the preset Value of ON/OFF in the boards register + elsif BUS_RX.addr(11 downto 8) = x"6" then -- write the preset Value of ON/OFF in the boards register + if BUS_RX.addr(7 downto 4) = x"0" then + register_onoff <= BUS_RX.data; + elsif BUS_RX.addr(7 downto 4) = x"1" then + reg_plotbin <= BUS_RX.data; + elsif BUS_RX.addr(7 downto 4) = x"2" then + reg_failsavebin <= BUS_RX.data; + end if; register_onoff <= BUS_RX.data; - elsif BUS_RX.addr(11 downto 8) = x"9" then - man_readFlag <= BUS_RX.data; + elsif BUS_RX.addr(11 downto 8) = x"9" then -- preset the read + if BUS_RX.addr(7 downto 4) = x"0" then + man_readFlag_plot <= BUS_RX.data; + elsif BUS_RX.addr(7 downto 4) = x"1" then + man_readFlag_failsave <= BUS_RX.data; + end if; + else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end if; end if; @@ -187,6 +243,34 @@ end process; +int_plotbin <= unsigned(reg_plotbin(31 downto 0)); +int_savebin <= unsigned(reg_plotbin(31 downto 0)); + +PROC_PLOTPUSER: process begin -- generate a pulse every 0.1 ms +wait until rising_edge (CLK); + if plotsave_timer = int_plotbin then -- eqals 10.000 rising edges + plotsave_pulse <= '1'; + plotsave_timer <= x"00000000"; + else + plotsave_timer <= plotsave_timer+1; + plotsave_pulse<='0'; + end if; +end process; + +-- Pulser for failsave +PROC_SAVEPUSER: process begin -- generate a pulse every 0.1 ms +wait until rising_edge (CLK); + if failsave_timer = int_savebin then -- eqals 10.000 rising edges + failsave_pulse <= '1'; + failsave_timer <= x"00000000" ; + else + failsave_timer <= failsave_timer+1; + failsave_pulse<='0'; + end if; +end process; + + + GEN_INDIV : for i in 0 to INPUTS-1 generate THE_INDIV: entity work.shutdown_indv @@ -196,8 +280,8 @@ THE_INDIV: entity work.shutdown_indv int_time => stretch_time(i), max_count => max_count(i), processed_signal => indiv_2_comp(i), - reset_pulse => fifo_writesignal(i), - current_hits_vctr => current_count(i) + reset_pulse => fifo_writesignal(i), + current_hits_vctr => current_count(i) ); end generate; @@ -218,20 +302,30 @@ generic map( ); + - +--auskommentiert um funktionierendes Bitfile zu erzeugen GEN_MONITOR: for i in 0 to INPUTS-1 generate THE_MONITOR: entity work.shutdown_mon port map( clk_in => CLK, reset => RESET, - hitvalue => current_count(i), - writeFlag => fifo_writesignal(i), - read_cmd => read_mem_Flag(i), -- automatic Read Flag - read_global => man_readFlag(i), -- manuell Read Flag - output_val => plot_values(i), - emptyFlag => fifoEmpty(i) + hitvalue => current_count(i), -- umbauen eigene Counter fur die fifos + + writeFlag_plot => plotsave_pulse, + writeFlag_failsave => failsave_pulse, + + read_cmd_plot => read_plot_Flag(i), + read_cmd_failsave => read_failsave_Flag(i), + + stop_cmd_plot => man_readFlag_plot(0), -- stop filling the plot ringbuffer + stop_cmd_failsave => man_readFlag_failsave(0), -- stop filling the failsafe ringbuffer + + output_plot => plot_values(i), + output_failsave => failsave_values(i), + emptyFlag1 => fifo1Empty(i), + emptyFlag2 => fifo2Empty(i) ); end generate; diff --git a/shutdownlogic/code/shutdown_monitoring.vhd b/shutdownlogic/code/shutdown_monitoring.vhd index 4a1176f..aeed084 100644 --- a/shutdownlogic/code/shutdown_monitoring.vhd +++ b/shutdownlogic/code/shutdown_monitoring.vhd @@ -11,90 +11,173 @@ entity shutdown_mon is -- declade all incoming signals port( clk_in : in std_logic; --- disable_reg : in std_logic; + --disable_reg : in std_logic; reset : in std_logic; hitvalue : in std_logic_vector (31 downto 0); - writeFlag : in std_logic; - read_cmd : in std_logic; --coming from BUS_RX.read '1' - read_global : in std_logic; --coming from register/manually - output_val : out std_logic_vector (31 downto 0); - emptyFlag : out std_logic); + + writeFlag_plot : in std_logic; + writeFlag_failsave : in std_logic; + + read_cmd_plot : in std_logic; --coming from BUS_RX.read '1' + read_cmd_failsave : in std_logic; --coming from BUS_RX.read '1' + + stop_cmd_plot : in std_logic; + stop_cmd_failsave : in std_logic; + + output_plot : out std_logic_vector (31 downto 0); + output_failsave : out std_logic_vector (31 downto 0); + + emptyFlag1 : out std_logic; + emptyFlag2 : out std_logic); end shutdown_mon; architecture behave of shutdown_mon is signal threshValue: std_logic_vector(9 downto 0):= "1111101000"; -signal data_2_fifo: std_logic_vector (31 downto 0); -signal writesignal: std_logic; -signal readsignal: std_logic:='0'; -signal amFull: std_logic; -signal last_amFull: std_logic; -signal allow_write: std_logic; +--signal data_2_fifo: std_logic_vector (31 downto 0); +signal writesignal1: std_logic:='0'; +signal readsignal1: std_logic:='0'; +signal amFull1: std_logic; +signal last_amFull1: std_logic; + +signal writesignal2: std_logic:='0'; +signal readsignal2: std_logic:='0'; +signal amFull2: std_logic; +signal last_amFull2: std_logic; signal in_2_fifo: std_logic_vector (35 downto 0):= x"000000000"; -signal timer: unsigned(15 downto 0):= x"0000"; -signal output_val_handler: std_logic_vector (35 downto 0); + +-- signal output_val_handler: std_logic_vector (35 downto 0); +signal output_plot_handler: std_logic_vector (35 downto 0); +signal output_failsave_handler: std_logic_vector (35 downto 0); -- signal helper: std_logic; begin -data_2_fifo <= hitvalue; -output_val <= output_val_handler(31 downto 0); +--data_2_fifo <= hitvalue; --ueberflussig +-- output_val <= output_val_handler(31 downto 0); +output_plot <= output_plot_handler(31 downto 0); +output_failsave <= output_failsave_handler(31 downto 0); in_2_fifo(31 downto 0) <= hitvalue; -- allow_write <= not read_global; -PROC_FIFOWRTITE: process is --- only write if the write flag is active + + + +PROC_PLOTFIFOLOAD: process is +--Trying to combine write and read begin wait until rising_edge(clk_in); - - if read_global = '0' and writeFlag = '1' then - writesignal <= '1'; - else - writesignal <= '0'; + last_amFull1 <= amFull1; + if reset = '0' then + if read_cmd_plot = '0' then --SCHREIBEN + -- readsignal1 <= '0'; + if last_amFull1 ='0' and amFull1 = '1' then + writesignal1 <= '0'; + readsignal1 <= '1'; + elsif writeFlag_plot = '1' then + writesignal1 <= '1'; + readsignal1 <= '0'; + else + writesignal1 <= '0'; + readsignal1 <= '0'; + end if; + + elsif read_cmd_plot = '1' and stop_cmd_plot = '0' then -- LESEN + writesignal1 <= '0'; + readsignal1 <= '1'; + end if; end if; - - end process; +THE_PLOTFIFO: entity work.fifo_36x1k_oreg + port map( + Data => in_2_fifo, -- Data: in std_logic_vector(35 downto 0); + Clock => clk_in, -- Clock: in std_logic; + WrEn => writesignal1, -- WrEn: in std_logic; + RdEn => readsignal1, -- RdEn: in std_logic; + Reset => reset, -- Reset: in std_logic; + AmFullThresh=> threshValue, -- AmFullThresh: in std_logic_vector(9 downto 0); + Q => output_plot_handler, -- Q: out std_logic_vector(35 downto 0); +-- WCNT => -- WCNT: out std_logic_vector(10 downto 0); + Empty => emptyFlag1, +-- Full =>-- Full: out std_logic; + AlmostFull => amFull1 -- AlmostFull: out std_logic); + ); - - -PROC_COMBINEDREAD: process is + + +PROC_FAILSAVEFIFOLOAD: process is +--Trying to combine write and read begin wait until rising_edge(clk_in); - last_amFull <= amFull; - if allow_write = '0' then - if read_cmd ='1' then - readsignal <= '1'; - elsif amFull ='1' and last_amFull='0' then - readsignal <='1'; - else - readsignal <='0'; + last_amFull2 <= amFull2; + if reset = '0' then + if read_cmd_failsave = '0' then --SCHREIBEN + -- readsignal2 <= '0'; + if last_amFull2 ='0' and amFull2 = '1' then + writesignal2 <= '0'; + readsignal2 <= '1'; + elsif writeFlag_failsave = '1' then + writesignal2 <= '1'; + readsignal2 <= '0'; + else + writesignal2 <= '0'; + readsignal2 <= '0'; + end if; + + elsif read_cmd_failsave = '1' and stop_cmd_failsave = '0' then -- LESEN + writesignal2 <= '0'; + readsignal2 <= '1'; end if; end if; end process; - - -THE_FIFO: entity work.fifo_36x1k_oreg +THE_FAILSAVEFIFO: entity work.fifo_36x1k_oreg port map( Data => in_2_fifo, -- Data: in std_logic_vector(35 downto 0); Clock => clk_in, -- Clock: in std_logic; - WrEn => writesignal, -- WrEn: in std_logic; - RdEn => readsignal, -- RdEn: in std_logic; + WrEn => writesignal2, -- WrEn: in std_logic; + RdEn => readsignal2, -- RdEn: in std_logic; Reset => reset, -- Reset: in std_logic; AmFullThresh=> threshValue, -- AmFullThresh: in std_logic_vector(9 downto 0); - Q => output_val_handler, -- Q: out std_logic_vector(35 downto 0); + Q => output_failsave_handler, -- Q: out std_logic_vector(35 downto 0); -- WCNT => -- WCNT: out std_logic_vector(10 downto 0); - Empty => emptyFlag, + Empty => emptyFlag2, -- Full =>-- Full: out std_logic; - AlmostFull => amFull -- AlmostFull: out std_logic); + AlmostFull => amFull2 -- AlmostFull: out std_logic); ); end behave; + +-- ---HIER liegt wsl der fehler mit dem Read_cmd +-- PROC_COMBINEDREAD: process is +-- begin +-- wait until rising_edge(clk_in); +-- last_amFull <= amFull; +-- if allow_write = '0' then +-- if read_cmd ='1' then +-- readsignal <= '1'; +-- elsif amFull ='1' and last_amFull='0' then +-- readsignal <='1'; +-- else +-- readsignal <='0'; +-- end if; +-- end if; +-- end process; +-- +-- + + + + + + + + + diff --git a/shutdownlogic/config.vhd b/shutdownlogic/config.vhd index 1725ffb..a6b5fba 100644 --- a/shutdownlogic/config.vhd +++ b/shutdownlogic/config.vhd @@ -37,11 +37,11 @@ package config is constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --input monitor and trigger generation logic - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; constant INCLUDE_STATISTICS : integer := c_YES; - constant TRIG_GEN_INPUT_NUM : integer := 64; + constant TRIG_GEN_INPUT_NUM : integer := 48; constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 64; + constant MONITOR_INPUT_NUM : integer := 48; ------------------------------------------------------------------------------ --End of design configuration diff --git a/shutdownlogic/par.p2t b/shutdownlogic/par.p2t index cb0ad8d..c1bae34 100644 --- a/shutdownlogic/par.p2t +++ b/shutdownlogic/par.p2t @@ -4,7 +4,7 @@ -n 1 -y -s 12 --t 26 +-t 27 -c 1 -e 2 #-g guidefile.ncd diff --git a/shutdownlogic/trb3sc_basic.prj b/shutdownlogic/trb3sc_basic.prj index f698ed8..68db6e3 100644 --- a/shutdownlogic/trb3sc_basic.prj +++ b/shutdownlogic/trb3sc_basic.prj @@ -45,6 +45,7 @@ project -result_file "workdir/trb3sc_basic.edf" #implementation attributes set_option -vlog_std v2001 +set_option -vhdl2008 1 set_option -project_relative_includes 1 impl -active "workdir" diff --git a/shutdownlogic/trb3sc_basic.vhd b/shutdownlogic/trb3sc_basic.vhd index 18f2d24..de5b04c 100644 --- a/shutdownlogic/trb3sc_basic.vhd +++ b/shutdownlogic/trb3sc_basic.vhd @@ -41,7 +41,7 @@ entity trb3sc_basic is --KEL Connector KEL : inout std_logic_vector(40 downto 1); - X : out std_logic_vector(12 downto 1); + -- X : out std_logic_vector(12 downto 1); --Additional IO HDR_IO : inout std_logic_vector(10 downto 1); @@ -97,7 +97,7 @@ entity trb3sc_basic is attribute syn_useioff of FLASH_CS : signal is true; attribute syn_useioff of FLASH_IN : signal is true; attribute syn_useioff of FLASH_OUT : signal is true; - + attribute syn_useioff of KEL : signal is false; --Serdes: Backplane --Backplane A2,A3,A0,A1 Slave 3,4,1,2, A0: TrbNet from backplane @@ -359,9 +359,9 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, --Trigger & Monitor - MONITOR_INPUTS => INP,--KEL(32 downto 1),--(others => '0'), - TRIG_GEN_INPUTS => INP,--KEL(32 downto 1),--(others => '0'), - TRIG_GEN_OUTPUTS => X(4 downto 1),--open, + MONITOR_INPUTS => INP(15 downto 0) & KEL(36 downto 21) & KEL(16 downto 1), --INP,--KEL(32 downto 1),--(others => '0'), + TRIG_GEN_INPUTS => INP(15 downto 0) & KEL(36 downto 21) & KEL(16 downto 1),--KEL(32 downto 1),--(others => '0'), + TRIG_GEN_OUTPUTS => open,--X(4 downto 1),--open, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -387,7 +387,7 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record -- I/O --------------------------------------------------------------------------- - RJ_IO <= "0000"; + -- RJ_IO <= "0000"; -- BACK_GPIO <= (others => 'Z'); BACK_LVDS <= (others => '0'); @@ -517,16 +517,17 @@ end process; --------------------------------------------------------------------------- THE_LOGIC : entity work.shutdown_logic generic map( - INPUTS => 24, - OUTPUTS =>8 + INPUTS => 32, + OUTPUTS =>2 ) port map( CLK => clk_sys, RESET => reset_i, BUS_RX => busshtdwn_rx, BUS_TX => busshtdwn_tx, - INPUT => KEL(24 downto 1), - OUTPUT => TEST_LINE(7 downto 0) + INPUT(15 downto 0) => KEL(16 downto 1), + INPUT(31 downto 16) => KEL(36 downto 21), + OUTPUT => RJ_IO(3 downto 2) );