From: Jan Michel Date: Tue, 26 Jul 2016 14:33:49 +0000 (+0200) Subject: Add design skeleton for PWM FPGAs X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=68b4699367993fe1d623fd652925b5cea629b67b;p=dirich.git Add design skeleton for PWM FPGAs --- diff --git a/thresholds/compile.pl b/thresholds/compile.pl new file mode 120000 index 0000000..8a19aa6 --- /dev/null +++ b/thresholds/compile.pl @@ -0,0 +1 @@ +../../trb3sc/scripts/compile.pl \ No newline at end of file diff --git a/thresholds/config_compile_frankfurt.pl b/thresholds/config_compile_frankfurt.pl new file mode 100644 index 0000000..cfd0459 --- /dev/null +++ b/thresholds/config_compile_frankfurt.pl @@ -0,0 +1,26 @@ +Familyname => 'MachXO3LF', +Devicename => 'LCMXO3LF-4300E', +Package => 'WLCSP81', +Speedgrade => '5', + +TOPNAME => "thresholds", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.7_x64', +synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +# synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", +# synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", +# synplify_command => "ssh -p 59222 jmichel\@cerberus \"cd /home/jmichel/git/trb3sc/template/workdir; LM_LICENSE_FILE=27000\@lxcad01.gsi.de /opt/synplicity/K-2015.09/bin/synplify_premier_dp -batch ../trb3sc_basic.prj\" #", +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, +no_ltxt2ptxt => 1, #if there is no serdes being used +make_jed => 1, diff --git a/thresholds/par.p2t b/thresholds/par.p2t new file mode 100644 index 0000000..39a0684 --- /dev/null +++ b/thresholds/par.p2t @@ -0,0 +1,21 @@ +-w +-i 15 +-l 5 +-n 1 +-y +-s 12 +-t 1 +-c 1 +-e 2 +#-g guidefile.ncd +#-m nodelist.txt +# -w +# -i 6 +# -l 5 +# -n 1 +# -t 1 +# -s 1 +# -c 0 +# -e 0 +# +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj new file mode 100644 index 0000000..d3897b3 --- /dev/null +++ b/thresholds/thresholds.prj @@ -0,0 +1,86 @@ +#-- Synopsys, Inc. +#-- Version J-2015.03L-SP1 +#-- Project file /d/jspc22/trb/git/LogicBox/diamond/LogicBox/run_options.txt + +#project files + +add_file -vhdl -lib work "/d/jspc29/lattice/diamond/3.6_x64/cae_library/synthesis/vhdl/machxo3lf.vhd" + +#add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../logicbox/code/uart_sctrl.vhd" +add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" +add_file -vhdl -lib work "../../mdcfee/code/pwm.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" + +add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" +add_file -vhdl -lib work "../../logicbox/cores/efb.vhd" +add_file -verilog -lib work "../../logicbox/cores/efb_define_def.v" +add_file -verilog -lib work "../../logicbox/cores/UFM_WB.v" + +add_file -vhdl -lib work "thresholds.vhd" + + + +#implementation: "Thresholds" +impl -add workdir -type fpga + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par + +#device options +set_option -technology MACHXO3LF +set_option -part LCMXO3LF_4300E +set_option -package UWG81CTR +set_option -speed_grade -5 +set_option -part_companion "" + +#compilation/mapping options +set_option -top_module "thresholds" + +# mapper_options +set_option -frequency 1 +set_option -write_verilog 0 +set_option -write_vhdl 0 +set_option -srs_instrumentation 1 + +# Lattice XP +set_option -maxfan 1000 +set_option -disable_io_insertion 0 +set_option -retiming 0 +set_option -pipe 1 +set_option -forcegsr false +set_option -fix_gated_and_generated_clocks 1 +set_option -rw_check_on_ram 1 +set_option -update_models_cp 0 +set_option -syn_edif_array_rename 1 +set_option -Write_declared_clocks_only 1 + +# sequential_optimization_options +set_option -symbolic_fsm_compiler 1 + +# Compiler Options +set_option -compiler_compatible 0 +set_option -resource_sharing 1 +set_option -multi_file_compilation_unit 1 + +# Compiler Options +set_option -auto_infer_blackbox 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_format "edif" +project -result_file "workdir/thresholds.edf" + +#set log file +set_option log_file "workdir/thresholds.srf" +impl -active "workdir" diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd new file mode 100644 index 0000000..33a5c59 --- /dev/null +++ b/thresholds/thresholds.vhd @@ -0,0 +1,227 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library machxo3lf; +use machxo3lf.all; + +library work; +use work.trb_net_std.all; + +entity thresholds is + port( + CLK : in std_logic; + + OUTPUT : out std_logic_vector(15 downto 0); + TX_IN : in std_logic; + RX_OUT : out std_logic +-- MISO_OUT : out std_logic; +-- MOSI_IN : in std_logic; +-- SCLK_IN : in std_logic; +-- CS_IN : in std_logic + ); +end entity; + +architecture arch of thresholds is + signal clk_osc, clk_i : std_logic; + + signal uart_rx_data : std_logic_vector(31 downto 0); + signal uart_tx_data : std_logic_vector(31 downto 0); + signal uart_addr : std_logic_vector(7 downto 0); + signal bus_read : std_logic := '0'; + signal bus_write : std_logic := '0'; + signal bus_ready : std_logic; + signal uart_busy : std_logic; + + signal sed_error : std_logic; + signal sed_debug : std_logic_vector(31 downto 0); + signal controlsed_i : std_logic_vector(3 downto 0); + + signal pwm_data_i : std_logic_vector(15 downto 0); + signal pwm_write_i : std_logic; + signal pwm_addr_i : std_logic_vector(4 downto 0); + + signal ram_write_i : std_logic; + signal ram_data_i: std_logic_vector(7 downto 0); + signal ram_data_o: std_logic_vector(7 downto 0); + signal ram_addr_i: std_logic_vector(3 downto 0); + + signal flashram_addr_i : std_logic_vector(3 downto 0); + signal flashram_cen_i : std_logic; + signal flashram_reset : std_logic; + signal flashram_write_i: std_logic; + signal flashram_data_i : std_logic_vector(7 downto 0); + signal flashram_data_o : std_logic_vector(7 downto 0); + + signal flash_command : std_logic_vector(2 downto 0); + signal flash_page : std_logic_vector(12 downto 0); + signal flash_go : std_logic; + signal flash_busy : std_logic; + signal flash_err : std_logic; + + + component OSCH + generic (NOM_FREQ: string := "33.25"); + port ( + STDBY :IN std_logic; + OSC :OUT std_logic; + SEDSTDBY :OUT std_logic + ); + end component; + + component UFM_WB + port( + clk_i : in std_logic; + rst_n : in std_logic; + cmd : in std_logic_vector(2 downto 0); + ufm_page : in std_logic_vector(12 downto 0); + GO : in std_logic; + BUSY : out std_logic; + ERR : out std_logic; + mem_clk : out std_logic; + mem_we : out std_logic; + mem_ce : out std_logic; + mem_addr : out std_logic_vector(3 downto 0); + mem_wr_data : out std_logic_vector(7 downto 0); + mem_rd_data : in std_logic_vector(7 downto 0) + ); + end component; + +begin + + + +--------------------------------------------------------------------------- +-- Clock +--------------------------------------------------------------------------- +clk_source: OSCH + generic map ( NOM_FREQ => "33.25" ) + port map ( + STDBY => '0', + OSC => clk_osc, + SEDSTDBY => open + ); + +clk_i <= clk_osc; + +--------------------------------------------------------------------------- +-- UART +--------------------------------------------------------------------------- +THE_UART : entity work.uart_sctrl + generic map( + CLOCK_SPEED => 133000000 + ) + port map( + CLK => clk_i, + RESET => '0', + UART_RX => TX_IN, + UART_TX => RX_OUT, + + DATA_OUT => uart_rx_data, + DATA_IN => uart_tx_data, + ADDR_OUT => uart_addr, + WRITE_OUT => bus_write, + READ_OUT => bus_read, + READY_IN => bus_ready, + + DEBUG => open + ); + + +PROC_REGS : process begin + wait until rising_edge(clk_i); + bus_ready <= '0'; + pwm_write_i<= '0'; + if bus_read = '1' then + bus_ready <= '1'; + case uart_addr is + when x"ee" => uart_tx_data <= sed_debug; + end case; + elsif bus_write = '1' then + if uart_addr < x"10" then + pwm_data_i <= uart_rx_data(15 downto 0); + pwm_addr_i <= uart_addr(4 downto 0); + pwm_write_i<= '1'; + else + case uart_addr is +-- when x"10" => reg <= uart_rx_data; + when x"ee" => controlsed_i <= uart_rx_data(3 downto 0); + end case; + end if; + end if; +end process; + + +THE_SED : entity work.sedcheck + port map( + CLK => clk_i, + ERROR_OUT => sed_error, + + CONTROL_IN => controlsed_i, + DEBUG => sed_debug + ); + +--------------------------------------------------------------------------- +-- PWM +--------------------------------------------------------------------------- +THE_PWM_GEN : entity work.pwm_generator + generic map( + CHANNELS => 16 + ) + port map( + CLK => clk_i, + DATA_IN => pwm_data_i, + DATA_OUT => open, + COMP_IN => (others => '0'), + WRITE_IN => pwm_write_i, + ADDR_IN => pwm_addr_i, + PWM => OUTPUT + ); + +--------------------------------------------------------------------------- +-- Flash Controller +--------------------------------------------------------------------------- + +THE_FLASH_RAM : entity work.flashram + port map( + DataInA => ram_data_i, + AddressA => ram_addr_i, + ClockA => clk_i, + ClockEnA => '1', + WrA => ram_write_i, + ResetA => '0', + QA => ram_data_o, + + DataInB => flashram_data_i, + AddressB => flashram_addr_i, + ClockB => clk_i, + ClockEnB => flashram_cen_i, + WrB => flashram_write_i, + ResetB => flashram_reset, + QB => flashram_data_o + ); + + + +THE_FLASH : UFM_WB + port map( + clk_i => clk_i, + rst_n => '1', + cmd => flash_command, + ufm_page => flash_page, + GO => flash_go, + BUSY => flash_busy, + ERR => flash_err, + mem_clk => open, + mem_we => flashram_write_i, + mem_ce => flashram_cen_i, + mem_addr => flashram_addr_i, + mem_wr_data => flashram_data_i, + mem_rd_data => flashram_data_o + ); + + +end architecture; + + + \ No newline at end of file