From: palka <palka>
Date: Tue, 12 Aug 2008 14:39:55 +0000 (+0000)
Subject: *** empty log message ***
X-Git-Tag: oldGBE~529
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=68d6c57cbb419bb192e0001d14bcb6125e636965;p=trbnet.git

*** empty log message ***
---

diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd
index 5f473ca..79283be 100644
--- a/optical_link/flexi_PCS_channel_synch.vhd
+++ b/optical_link/flexi_PCS_channel_synch.vhd
@@ -127,7 +127,7 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is
   signal fifo_opt_empty_synch_synch : std_logic;
   signal fifo_rd_en_hub : std_logic;
 begin
-  SEND_ERROR: process (SYSTEM_CLK, RESET)
+  SEND_ERROR: process (SYSTEM_CLK, RESET,SYNCH_CURRENT)
   begin 
     if rising_edge(SYSTEM_CLK) then
       if RESET = '1' then          
@@ -141,7 +141,7 @@ begin
       end if;
     end if;
   end process SEND_ERROR;
-  PACKET_NUM: process (SYSTEM_CLK, RESET)
+  PACKET_NUM: process (SYSTEM_CLK, RESET,fifo_rd_en)
   begin
     if rising_edge(SYSTEM_CLK) then 
       if RESET = '1' then  
@@ -152,7 +152,7 @@ begin
     end if;
   end process PACKET_NUM;
   MED_PACKET_NUM_OUT <= packet_number;
-  LINK_STATUS : process (SYSTEM_CLK)
+  LINK_STATUS : process (SYSTEM_CLK,RESET)
   begin
     if rising_edge(SYSTEM_CLK) then
       if RESET = '1' then
@@ -187,7 +187,7 @@ begin
         AlmostEmpty => fifo_opt_almost_empty,
         AlmostFull  => fifo_opt_almost_full
         );
-    DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN)
+    DATA_SEND_TO_LINK: process (TX_CLK, RESET, DATA_VALID_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch)
     begin 
       if rising_edge(TX_CLK) then          --falling ???
         if RESET = '1' then
@@ -258,6 +258,9 @@ begin
       elsif MED_READ_IN = '1' and fifo_empty = '1' and data_valid_out_i = '1' then
         data_valid_out_i <= '0';
         fifo_rd_en_hub <= '0';
+      elsif data_valid_out_i = '1' and fifo_empty = '0' then
+        data_valid_out_i <= '1';
+        fifo_rd_en_hub <= MED_READ_IN;
       end if;
     end if;
   end process READING_THE_FIFO;
@@ -301,7 +304,7 @@ begin
   begin
     if rising_edge (SYSTEM_CLK) then
       if RESET = '1' then
-        SYNCH_CURRENT <= IDLE;
+        SYNCH_CURRENT <= IDLE; --NORMAL_OPERATION_2;--IDLE; --sim
         cv_i <= (others => '0');
       else
         SYNCH_CURRENT <= SYNCH_NEXT;
@@ -313,7 +316,7 @@ begin
   begin
     case (SYNCH_CURRENT) is
       when IDLE    =>
-        fifo_rst <= '0';
+        fifo_rst <= '1';
         fifo_wr_en <= '0';
         fsm_debug_register(2 downto 0) <= "001";
         rx_rst_i       <= '0';
@@ -408,7 +411,7 @@ begin
            SYNCH_NEXT <= NORMAL_OPERATION_1;
          end if;
       when NORMAL_OPERATION_2 =>
-         fifo_rst <= '0';
+         fifo_rst <='0';--RESET;--'0';sim
          fifo_wr_en <= not rx_k_synch_i(0);              
          fsm_debug_register(2 downto 0) <= "111";
          rx_rst_i       <= '0';
diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd
index 3dddb6d..c27e291 100644
--- a/optical_link/hub.vhd
+++ b/optical_link/hub.vhd
@@ -790,7 +790,7 @@ begin
 
     TRB_HUB_INT : trb_hub_interface
       port map (
-        CLK                    => ref_pclk(0),
+        CLK                    => LVDS_CLK_200P,
         RESET                  => ADO_TTL(0),
         STROBE                 => ADO_TTL(9),
         internal_data_in       => ADO_TTL(18 downto 11),