From: Michael Boehmer Date: Tue, 16 Aug 2022 09:06:50 +0000 (+0200) Subject: path cleanup, DLM stuff starts X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=693214dc5d289ced87b92bd0c43e99b9fe54d5ef;p=trbnet.git path cleanup, DLM stuff starts --- diff --git a/gbe_trb/base/remover.vhd b/gbe_trb/base/remover.vhd index d598e07..48a4aac 100644 --- a/gbe_trb/base/remover.vhd +++ b/gbe_trb/base/remover.vhd @@ -59,6 +59,9 @@ architecture remover_arch of remover is signal replace_d : std_logic; signal dlm_data_int : std_logic_vector(7 downto 0); + signal rx_d_int : std_logic_vector(7 downto 0); + signal rx_k_int : std_logic; + begin DEBUG_OUT(0) <= dlm_found; @@ -69,8 +72,12 @@ begin DEBUG_OUT(5) <= fifoempty; DEBUG_OUT(15 downto 6) <= (others => '0'); + -- Pipeline stage + rx_d_int <= RX_D_IN when rising_edge(CLK); + rx_k_int <= RX_K_IN when rising_edge(CLK); + -- DLM komma detected in data stream - dlm_found_x <= '1' when ((RX_K_IN = '1') and (RX_D_IN = x"dc")) else '0'; + dlm_found_x <= '1' when ((rx_k_int = '1') and (rx_d_int = x"dc")) else '0'; dlm_found <= dlm_found_x when rising_edge(CLK); @@ -82,7 +89,7 @@ begin if ( RESET = '1' ) then dlm_data_int <= (others => '0'); elsif( dlm_found = '1' ) then - dlm_data_int <= RX_D_IN; + dlm_data_int <= rx_d_int; end if; end if; end process THE_STORE_PROC; @@ -91,18 +98,18 @@ begin -- write signal for FIFO fifo_wr_x <= '0' when ((dlm_found_x = '1') or (dlm_found = '1')) else '1'; - + -- FIFO THE_FIFO: fifo_remover port map( - DATA(8) => RX_K_IN, - DATA(7 downto 0) => RX_D_IN, + DATA(8) => rx_k_int, + DATA(7 downto 0) => rx_d_int, CLOCK => CLK, WREN => fifo_wr_x, RDEN => fifo_rd_x, RESET => RESET, Q(8) => phy_k_fifo, - Q(7 downto 0) => phy_d_fifo, + Q(7 downto 0) => phy_d_fifo, WCNT => open, EMPTY => fifoempty, FULL => open, diff --git a/gbe_trb_ecp3/cores/fifo_inserter.lpc b/gbe_trb_ecp3/cores/fifo_inserter.lpc new file mode 100644 index 0000000..d95b509 --- /dev/null +++ b/gbe_trb_ecp3/cores/fifo_inserter.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_inserter +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/09/2022 +Time=10:20:45 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=10 +regout=0 +CtrlByRdEn=0 +EmpFlg=1 +PeMode=Static - Single Threshold +PeAssert=2 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_inserter -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -pfu_fifo -addr_width 4 -data_width 10 -num_words 16 -no_enable -pe 2 -pf -1 -fill diff --git a/gbe_trb_ecp3/cores/fifo_inserter.vhd b/gbe_trb_ecp3/cores/fifo_inserter.vhd new file mode 100644 index 0000000..18210ad --- /dev/null +++ b/gbe_trb_ecp3/cores/fifo_inserter.vhd @@ -0,0 +1,578 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_inserter -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 16 -width 10 -depth 16 -no_enable -pe 2 -pf -1 -fill + +-- Tue Aug 9 10:20:45 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_inserter is + port ( + Data: in std_logic_vector(9 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(9 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic); +end fifo_inserter; + +architecture Structure of fifo_inserter is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal cnt_con: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal wren_i: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal scuba_vhi: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal ae_d: std_logic; + signal ae_d_c: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal scuba_vlo: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_1: std_logic; + signal rcount_0: std_logic; + signal dec0_wre3: std_logic; + signal wcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_inserter.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_inserter.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-9)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_inserter.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + FF_27: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_26: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_25: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_24: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_23: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_22: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_21: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_20: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_19: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_18: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_17: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_16: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_15: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_14: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_13: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_12: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_11: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_10: FD1P3DX + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_9: FD1P3DX + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_8: FD1P3DX + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_7: FD1P3DX + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_6: FD1P3DX + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_5: FD1P3DX + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_4: FD1P3DX + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_3: FD1P3DX + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_2: FD1P3DX + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_1: FD1P3DX + port map (D=>rdataout9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(9)); + + FF_0: FD1S3BX + port map (D=>ae_d, CK=>Clock, PD=>Reset, Q=>AlmostEmpty); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co1_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>iwcount_4, NC1=>open); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2, + NC0=>ircount_4, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + ae_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + S1=>open); + + ae_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, CI=>cmp_ci_2, LE=>co0_5); + + ae_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_5, LE=>co1_5); + + ae_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_5, LE=>ae_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>ae_d_c, COUT=>open, S0=>ae_d, S1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_pfu_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(8), DI1=>Data(9), DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>wcount_3, DO0=>rdataout8, DO1=>rdataout9, DO2=>open, + DO3=>open); + + fifo_pfu_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, + DO3=>rdataout7); + + fifo_pfu_0_2: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, + DO3=>rdataout3); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_inserter is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb_ecp3/cores/fifo_remover.lpc b/gbe_trb_ecp3/cores/fifo_remover.lpc new file mode 100644 index 0000000..7be2ffa --- /dev/null +++ b/gbe_trb_ecp3/cores/fifo_remover.lpc @@ -0,0 +1,48 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO +CoreRevision=5.1 +ModuleName=fifo_remover +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=08/09/2022 +Time=10:23:35 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=9 +regout=0 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=14 +PfDeassert=506 +RDataCount=1 +EnECC=0 +EnFWFT=0 + +[Command] +cmd_line= -w -n fifo_remover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifoblk -pfu_fifo -addr_width 4 -data_width 9 -num_words 16 -no_enable -pe -1 -pf 14 -fill diff --git a/gbe_trb_ecp3/cores/fifo_remover.vhd b/gbe_trb_ecp3/cores/fifo_remover.vhd new file mode 100644 index 0000000..db37064 --- /dev/null +++ b/gbe_trb_ecp3/cores/fifo_remover.vhd @@ -0,0 +1,572 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.1 +--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n fifo_remover -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 16 -width 9 -depth 16 -no_enable -pe -1 -pf 14 -fill + +-- Tue Aug 9 10:23:35 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity fifo_remover is + port ( + Data: in std_logic_vector(8 downto 0); + Clock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + Q: out std_logic_vector(8 downto 0); + WCNT: out std_logic_vector(4 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end fifo_remover; + +architecture Structure of fifo_remover is + + -- internal signal declarations + signal invout_2: std_logic; + signal invout_1: std_logic; + signal rden_i_inv: std_logic; + signal invout_0: std_logic; + signal r_nw_inv: std_logic; + signal r_nw: std_logic; + signal fcnt_en_inv: std_logic; + signal fcnt_en: std_logic; + signal empty_i: std_logic; + signal empty_d: std_logic; + signal full_i: std_logic; + signal full_d: std_logic; + signal ifcount_0: std_logic; + signal ifcount_1: std_logic; + signal bdcnt_bctr_ci: std_logic; + signal ifcount_2: std_logic; + signal ifcount_3: std_logic; + signal co0: std_logic; + signal ifcount_4: std_logic; + signal co2: std_logic; + signal cnt_con: std_logic; + signal co1: std_logic; + signal cmp_ci: std_logic; + signal rden_i: std_logic; + signal co0_1: std_logic; + signal co1_1: std_logic; + signal cmp_le_1: std_logic; + signal cmp_le_1_c: std_logic; + signal cmp_ci_1: std_logic; + signal co0_2: std_logic; + signal wren_i: std_logic; + signal co1_2: std_logic; + signal wren_i_inv: std_logic; + signal cmp_ge_d1: std_logic; + signal cmp_ge_d1_c: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_ctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0_3: std_logic; + signal iwcount_4: std_logic; + signal co2_1: std_logic; + signal co1_3: std_logic; + signal wcount_4: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_ctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_4: std_logic; + signal ircount_4: std_logic; + signal co2_2: std_logic; + signal co1_4: std_logic; + signal rcount_4: std_logic; + signal cmp_ci_2: std_logic; + signal fcnt_en_inv_inv: std_logic; + signal cnt_con_inv: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; + signal co0_5: std_logic; + signal scuba_vhi: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; + signal co1_5: std_logic; + signal fcount_4: std_logic; + signal af_d: std_logic; + signal af_d_c: std_logic; + signal rdataout8: std_logic; + signal scuba_vlo: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rcount_3: std_logic; + signal rcount_2: std_logic; + signal rcount_1: std_logic; + signal rcount_0: std_logic; + signal dec0_wre3: std_logic; + signal wcount_3: std_logic; + signal wcount_2: std_logic; + signal wcount_1: std_logic; + signal wcount_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component ALEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; LE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component CB2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CON: in std_logic; CO: out std_logic; NC0: out std_logic; + NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "fifo_remover.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "fifo_remover.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-8)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "fifo_remover.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + AND2_t4: AND2 + port map (A=>WrEn, B=>invout_2, Z=>wren_i); + + INV_8: INV + port map (A=>full_i, Z=>invout_2); + + AND2_t3: AND2 + port map (A=>RdEn, B=>invout_1, Z=>rden_i); + + INV_7: INV + port map (A=>empty_i, Z=>invout_1); + + AND2_t2: AND2 + port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); + + XOR2_t1: XOR2 + port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); + + INV_6: INV + port map (A=>rden_i, Z=>rden_i_inv); + + INV_5: INV + port map (A=>wren_i, Z=>wren_i_inv); + + LUT4_2: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_le_1, AD1=>wren_i, + AD0=>empty_i, DO0=>empty_d); + + LUT4_1: ROM16X1A + generic map (initval=> X"3232") + port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, + AD0=>full_i, DO0=>full_d); + + LUT4_0: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + AND2_t0: AND2 + port map (A=>rden_i, B=>invout_0, Z=>r_nw); + + INV_4: INV + port map (A=>wren_i, Z=>invout_0); + + INV_3: INV + port map (A=>fcnt_en, Z=>fcnt_en_inv); + + INV_2: INV + port map (A=>cnt_con, Z=>cnt_con_inv); + + INV_1: INV + port map (A=>r_nw, Z=>r_nw_inv); + + INV_0: INV + port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + + FF_26: FD1P3DX + port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_0); + + FF_25: FD1P3DX + port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_1); + + FF_24: FD1P3DX + port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_2); + + FF_23: FD1P3DX + port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_3); + + FF_22: FD1P3DX + port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_4); + + FF_21: FD1S3BX + port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); + + FF_20: FD1S3DX + port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); + + FF_19: FD1P3DX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_0); + + FF_18: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_1); + + FF_17: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_2); + + FF_16: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_3); + + FF_15: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_4); + + FF_14: FD1P3DX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_0); + + FF_13: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_1); + + FF_12: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_2); + + FF_11: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_3); + + FF_10: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_4); + + FF_9: FD1P3DX + port map (D=>rdataout0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(0)); + + FF_8: FD1P3DX + port map (D=>rdataout1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(1)); + + FF_7: FD1P3DX + port map (D=>rdataout2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(2)); + + FF_6: FD1P3DX + port map (D=>rdataout3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(3)); + + FF_5: FD1P3DX + port map (D=>rdataout4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(4)); + + FF_4: FD1P3DX + port map (D=>rdataout5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(5)); + + FF_3: FD1P3DX + port map (D=>rdataout6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(6)); + + FF_2: FD1P3DX + port map (D=>rdataout7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(7)); + + FF_1: FD1P3DX + port map (D=>rdataout8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>Q(8)); + + FF_0: FD1S3DX + port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + + bdcnt_bctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, + CI=>scuba_vlo, COUT=>bdcnt_bctr_ci, S0=>open, S1=>open); + + bdcnt_bctr_0: CB2 + port map (CI=>bdcnt_bctr_ci, PC0=>fcount_0, PC1=>fcount_1, + CON=>cnt_con, CO=>co0, NC0=>ifcount_0, NC1=>ifcount_1); + + bdcnt_bctr_1: CB2 + port map (CI=>co0, PC0=>fcount_2, PC1=>fcount_3, CON=>cnt_con, + CO=>co1, NC0=>ifcount_2, NC1=>ifcount_3); + + bdcnt_bctr_2: CB2 + port map (CI=>co1, PC0=>fcount_4, PC1=>scuba_vlo, CON=>cnt_con, + CO=>co2, NC0=>ifcount_4, NC1=>open); + + e_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, + S1=>open); + + e_cmp_0: ALEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>rden_i, B1=>scuba_vlo, + CI=>cmp_ci, LE=>co0_1); + + e_cmp_1: ALEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co0_1, LE=>co1_1); + + e_cmp_2: ALEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_1, LE=>cmp_le_1_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_le_1_c, COUT=>open, S0=>cmp_le_1, + S1=>open); + + g_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, + S1=>open); + + g_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>wren_i, B1=>wren_i, + CI=>cmp_ci_1, GE=>co0_2); + + g_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>wren_i, B1=>wren_i, + CI=>co0_2, GE=>co1_2); + + g_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>wren_i_inv, + B1=>scuba_vlo, CI=>co1_2, GE=>cmp_ge_d1_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>cmp_ge_d1_c, COUT=>open, S0=>cmp_ge_d1, + S1=>open); + + w_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_ctr_ci, S0=>open, + S1=>open); + + w_ctr_0: CU2 + port map (CI=>w_ctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0_3, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_ctr_1: CU2 + port map (CI=>co0_3, PC0=>wcount_2, PC1=>wcount_3, CO=>co1_3, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_ctr_2: CU2 + port map (CI=>co1_3, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>iwcount_4, NC1=>open); + + r_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_ctr_ci, S0=>open, + S1=>open); + + r_ctr_0: CU2 + port map (CI=>r_ctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_4, + NC0=>ircount_0, NC1=>ircount_1); + + r_ctr_1: CU2 + port map (CI=>co0_4, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_4, + NC0=>ircount_2, NC1=>ircount_3); + + r_ctr_2: CU2 + port map (CI=>co1_4, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_2, + NC0=>ircount_4, NC1=>open); + + af_cmp_ci_a: FADD2B + port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + S1=>open); + + af_cmp_0: AGEB2 + port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, + B1=>cnt_con_inv, CI=>cmp_ci_2, GE=>co0_5); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_cmp_1: AGEB2 + port map (A0=>fcount_2, A1=>fcount_3, B0=>scuba_vhi, + B1=>scuba_vhi, CI=>co0_5, GE=>co1_5); + + af_cmp_2: AGEB2 + port map (A0=>fcount_4, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>co1_5, GE=>af_d_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_pfu_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(8), DI1=>scuba_vlo, DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, + RAD1=>rcount_1, RAD2=>rcount_2, RAD3=>rcount_3, + WAD0=>wcount_0, WAD1=>wcount_1, WAD2=>wcount_2, + WAD3=>wcount_3, DO0=>rdataout8, DO1=>open, DO2=>open, + DO3=>open); + + fifo_pfu_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout4, DO1=>rdataout5, DO2=>rdataout6, + DO3=>rdataout7); + + fifo_pfu_0_2: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>Clock, WRE=>dec0_wre3, RAD0=>rcount_0, RAD1=>rcount_1, + RAD2=>rcount_2, RAD3=>rcount_3, WAD0=>wcount_0, + WAD1=>wcount_1, WAD2=>wcount_2, WAD3=>wcount_3, + DO0=>rdataout0, DO1=>rdataout1, DO2=>rdataout2, + DO3=>rdataout3); + + WCNT(0) <= fcount_0; + WCNT(1) <= fcount_1; + WCNT(2) <= fcount_2; + WCNT(3) <= fcount_3; + WCNT(4) <= fcount_4; + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of fifo_remover is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:ALEB2 use entity ecp3.ALEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:CB2 use entity ecp3.CB2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_trb_ecp3/base/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd similarity index 85% rename from gbe_trb_ecp3/base/gbe_med_fifo.vhd rename to gbe_trb_ecp3/media/gbe_med_fifo.vhd index 5192242..69d180d 100644 --- a/gbe_trb_ecp3/base/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd @@ -12,7 +12,8 @@ use work.med_sync_define_RS.all; entity gbe_med_fifo is generic( LINKS_ACTIVE : std_logic_vector(3 downto 0) := "1111"; - SNIFFER_PORT : integer range 0 to 3 := 0 + SNIFFER_PORT : integer range 0 to 3 := 0; + INCLUDE_DLM : int_array_t(3 downto 0) := (1, 1, 1, 1) ); port( RESET : in std_logic; @@ -51,6 +52,12 @@ entity gbe_med_fifo is PCS_AN_READY_OUT : out std_logic_vector(3 downto 0); -- for internal SCTRL LINK_ACTIVE_OUT : out std_logic_vector(3 downto 0); -- for internal SCTRL TICK_MS_IN : in std_logic; + -- DLM + DLM_INJECT_IN : in std_logic_vector(3 downto 0) := (others => '0'); + DLM_DATA_IN : in std_logic_vector(4 * 8 - 1 downto 0) := (others => '0'); + DLM_FOUND_OUT : out std_logic_vector(3 downto 0); + DLM_DATA_OUT : out std_logic_vector(4 * 8 - 1 downto 0); + DLM_CLK_OUT : out std_logic_vector(3 downto 0); -- Debug STATUS_OUT : out std_logic_vector(4 * 8 - 1 downto 0); DEBUG_OUT : out std_logic_vector(63 downto 0) @@ -169,13 +176,19 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is ); end component; + signal sd_tx_kcntl_src : std_logic_vector(3 downto 0); + signal sd_tx_kcntl_dst : std_logic_vector(3 downto 0); + signal sd_tx_data_src : std_logic_vector(4 * 8 - 1 downto 0); + signal sd_tx_data_dst : std_logic_vector(4 * 8 - 1 downto 0); + signal sd_tx_correct_disp_src : std_logic_vector(3 downto 0); + signal sd_tx_correct_disp_dst : std_logic_vector(3 downto 0); + signal sd_rx_data_src : std_logic_vector(4 * 8 - 1 downto 0); + signal sd_rx_data_dst : std_logic_vector(4 * 8 - 1 downto 0); + signal sd_rx_kcntl_src : std_logic_vector(3 downto 0); + signal sd_rx_kcntl_dst : std_logic_vector(3 downto 0); + signal sd_rx_clk : std_logic_vector(3 downto 0); - signal sd_tx_kcntl : std_logic_vector(3 downto 0); - signal sd_tx_data : std_logic_vector(4 * 8 - 1 downto 0); signal xmit : std_logic_vector(3 downto 0); - signal sd_tx_correct_disp : std_logic_vector(3 downto 0); - signal sd_rx_data : std_logic_vector(4 * 8 - 1 downto 0); - signal sd_rx_kcntl : std_logic_vector(3 downto 0); signal sd_rx_disp_error : std_logic_vector(3 downto 0); signal sd_rx_cv_error : std_logic_vector(3 downto 0); signal lsm_status : std_logic_vector(3 downto 0); @@ -267,12 +280,12 @@ begin tx_full_clk_ch0 => open, tx_half_clk_ch0 => open, fpga_rxrefclk_ch0 => CLK_125, - txdata_ch0 => sd_tx_data(7 downto 0), - tx_k_ch0 => sd_tx_kcntl(0), + txdata_ch0 => sd_tx_data_dst(7 downto 0), + tx_k_ch0 => sd_tx_kcntl_dst(0), xmit_ch0 => xmit(0), - tx_disp_correct_ch0 => sd_tx_correct_disp(0), - rxdata_ch0 => sd_rx_data(7 downto 0), - rx_k_ch0 => sd_rx_kcntl(0), + tx_disp_correct_ch0 => sd_tx_correct_disp_dst(0), + rxdata_ch0 => sd_rx_data_src(7 downto 0), + rx_k_ch0 => sd_rx_kcntl_src(0), rx_disp_err_ch0 => sd_rx_disp_error(0), rx_cv_err_ch0 => sd_rx_cv_error(0), rx_serdes_rst_ch0_c => rx_serdes_rst(0), @@ -297,12 +310,12 @@ begin tx_full_clk_ch1 => open, tx_half_clk_ch1 => open, fpga_rxrefclk_ch1 => CLK_125, - txdata_ch1 => sd_tx_data(15 downto 8), - tx_k_ch1 => sd_tx_kcntl(1), + txdata_ch1 => sd_tx_data_dst(15 downto 8), + tx_k_ch1 => sd_tx_kcntl_dst(1), xmit_ch1 => xmit(1), - tx_disp_correct_ch1 => sd_tx_correct_disp(1), - rxdata_ch1 => sd_rx_data(15 downto 8), - rx_k_ch1 => sd_rx_kcntl(1), + tx_disp_correct_ch1 => sd_tx_correct_disp_dst(1), + rxdata_ch1 => sd_rx_data_src(15 downto 8), + rx_k_ch1 => sd_rx_kcntl_src(1), rx_disp_err_ch1 => sd_rx_disp_error(1), rx_cv_err_ch1 => sd_rx_cv_error(1), rx_serdes_rst_ch1_c => rx_serdes_rst(1), @@ -327,12 +340,12 @@ begin tx_full_clk_ch2 => open, tx_half_clk_ch2 => open, fpga_rxrefclk_ch2 => CLK_125, - txdata_ch2 => sd_tx_data(23 downto 16), - tx_k_ch2 => sd_tx_kcntl(2), + txdata_ch2 => sd_tx_data_dst(23 downto 16), + tx_k_ch2 => sd_tx_kcntl_dst(2), xmit_ch2 => xmit(2), - tx_disp_correct_ch2 => sd_tx_correct_disp(2), - rxdata_ch2 => sd_rx_data(23 downto 16), - rx_k_ch2 => sd_rx_kcntl(2), + tx_disp_correct_ch2 => sd_tx_correct_disp_dst(2), + rxdata_ch2 => sd_rx_data_src(23 downto 16), + rx_k_ch2 => sd_rx_kcntl_src(2), rx_disp_err_ch2 => sd_rx_disp_error(2), rx_cv_err_ch2 => sd_rx_cv_error(2), rx_serdes_rst_ch2_c => rx_serdes_rst(2), @@ -357,12 +370,12 @@ begin tx_full_clk_ch3 => open, tx_half_clk_ch3 => open, fpga_rxrefclk_ch3 => CLK_125, - txdata_ch3 => sd_tx_data(31 downto 24), - tx_k_ch3 => sd_tx_kcntl(3), + txdata_ch3 => sd_tx_data_dst(31 downto 24), + tx_k_ch3 => sd_tx_kcntl_dst(3), xmit_ch3 => xmit(3), - tx_disp_correct_ch3 => sd_tx_correct_disp(3), - rxdata_ch3 => sd_rx_data(31 downto 24), - rx_k_ch3 => sd_rx_kcntl(3), + tx_disp_correct_ch3 => sd_tx_correct_disp_dst(3), + rxdata_ch3 => sd_rx_data_src(31 downto 24), + rx_k_ch3 => sd_rx_kcntl_src(3), rx_disp_err_ch3 => sd_rx_disp_error(3), rx_cv_err_ch3 => sd_rx_cv_error(3), rx_serdes_rst_ch3_c => rx_serdes_rst(3), @@ -424,7 +437,61 @@ begin D_OUT(0) => rx_pcs_rst_q(i), D_OUT(1) => rx_serdes_rst_q(i) ); - + + ------------------------------------------------------------ + --- Trudy and Eve ------------------------------------------ + ------------------------------------------------------------ + TRUDY_AND_EVE: if INCLUDE_DLM(i) = 1 generate + THE_TRUDY: entity inserter + port map( + CLK => CLK_125, + RESET => CLEAR, + -- PHY output + PHY_D_IN => sd_tx_data_src((i + 1) * 8 - 1 downto i * 8), + PHY_K_IN => sd_tx_kcntl_src(i), + PHY_CD_IN => sd_tx_correct_disp_src(i), + -- SerDes input + TX_D_OUT => sd_tx_data_dst((i + 1) * 8 - 1 downto i * 8), + TX_K_OUT => sd_tx_kcntl_dst(i), + TX_CD_OUT => sd_tx_correct_disp_dst(i), + -- DLM stuff + DLM_DATA_IN => DLM_DATA_IN((i + 1) * 8 - 1 downto i * 8), + DLM_INJECT_IN => DLM_INJECT_IN(i), + -- + DEBUG_OUT => open --inserter_dbg + ); + + THE_EVE: entity remover + port map( + CLK => sd_rx_clk(i), + RESET => CLEAR, + -- SerDes output + RX_D_IN => sd_rx_data_src((i + 1) * 8 - 1 downto i * 8), + RX_K_IN => sd_rx_kcntl_src(i), + -- PHY input + PHY_D_OUT => sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8), + PHY_K_OUT => sd_rx_kcntl_dst(i), + -- DLM stuff + DLM_DATA_OUT => DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8), + DLM_FOUND_OUT => DLM_FOUND_OUT(i), + -- + DEBUG_OUT => open --remover_dbg + ); + end generate TRUDY_AND_EVE; + + NO_TRUDY_AND_EVE: if INCLUDE_DLM(i) = 0 generate + sd_tx_data_dst((i + 1) * 8 - 1 downto i * 8) <= sd_tx_data_src((i + 1) * 8 - 1 downto i * 8); + sd_tx_kcntl_dst(i) <= sd_tx_kcntl_src(i); + sd_tx_correct_disp_dst(i) <= sd_tx_correct_disp_src(i); + sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8) <= sd_rx_data_src((i + 1) * 8 - 1 downto i * 8); + sd_rx_kcntl_dst(i) <= sd_rx_kcntl_src(i); + DLM_DATA_OUT((i + 1) * 8 - 1 downto i * 8) <= (others => '0'); + DLM_FOUND_OUT(i) <= 'i'; + end generate NO_TRUDY_AND_EVE; + ------------------------------------------------------------ + ------------------------------------------------------------ + ------------------------------------------------------------ + -- SGMII core SGMII_GBE_PCS : sgmii_gbe_pcs42 port map( @@ -457,13 +524,13 @@ begin col => open, crs => open, -- SerDes interface - tx_data => sd_tx_data((i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes - tx_kcntl => sd_tx_kcntl(i), -- TX komma control to SerDes - tx_disparity_cntl => sd_tx_correct_disp(i), -- idle parity state control in IPG (to SerDes) + tx_data => sd_tx_data_src((i + 1) * 8 - 1 downto i * 8), -- TX data to SerDes + tx_kcntl => sd_tx_kcntl_src(i), -- TX komma control to SerDes + tx_disparity_cntl => sd_tx_correct_disp_src(i), -- idle parity state control in IPG (to SerDes) xmit_autoneg => xmit(i), serdes_recovered_clk => sd_rx_clk(i), -- 125MHz recovered from receive bit stream - rx_data => sd_rx_data((i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes - rx_kcntl => sd_rx_kcntl(i), -- RX komma control from SerDes + rx_data => sd_rx_data_dst((i + 1) * 8 - 1 downto i * 8), -- RX data from SerDes + rx_kcntl => sd_rx_kcntl_dst(i), -- RX komma control from SerDes rx_err_decode_mode => '0', -- receive error control mode fixed to normal rx_even => '0', -- unused (receive error control mode = normal, tie to GND) rx_disp_err => sd_rx_disp_error(i), -- RX disparity error from SerDes diff --git a/gbe_trb_ecp5/media/gbe_med_fifo.vhd b/gbe_trb_ecp5/media/gbe_med_fifo.vhd index 3d589cb..562e7d5 100644 --- a/gbe_trb_ecp5/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp5/media/gbe_med_fifo.vhd @@ -62,6 +62,7 @@ entity gbe_med_fifo is DLM_DATA_IN : in std_logic_vector(7 downto 0) := (others => '0'); DLM_FOUND_OUT : out std_logic; DLM_DATA_OUT : out std_logic_vector(7 downto 0); + DLM_CLK_OUT : out std_logic; -- Debug STATUS_OUT : out std_logic_vector(7 downto 0); DEBUG_OUT : out std_logic_vector(63 downto 0) @@ -515,10 +516,12 @@ begin D_OUT(1) => rx_serdes_rst_q ); + -- recovered received clock + DLM_CLK_OUT <= sd_rx_clk; + ------------------------------------------------------------ --- Trudy and Eve ------------------------------------------ ------------------------------------------------------------ - TRUDY_AND_EVE: if INCLUDE_DLM = 1 generate THE_TRUDY: entity inserter port map( @@ -566,11 +569,12 @@ begin DLM_DATA_OUT <= (others => '0'); DLM_FOUND_OUT <= '0'; end generate NO_TRUDY_AND_EVE; - ------------------------------------------------------------ ------------------------------------------------------------ ------------------------------------------------------------ + -- NOTE: link_rx_ready as rst_n for SGMII core + -- SGMII core SGMII_GBE_PCS : sgmii_gbe_core port map(