From: palka Date: Thu, 21 Feb 2008 12:55:52 +0000 (+0000) Subject: checking lenght of event X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=69c0bf1fe00008a6acf170b7dd1dcb533e769c92;p=trbv2.git checking lenght of event --- diff --git a/trb_v2b_fpga_tb.vhd b/trb_v2b_fpga_tb.vhd index 894fcb3..687865f 100644 --- a/trb_v2b_fpga_tb.vhd +++ b/trb_v2b_fpga_tb.vhd @@ -171,7 +171,14 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS VIRT_TMS : out std_logic; VIRT_TRST : out std_logic); end component; - signal VIRT_CLK : std_logic; + component edge_to_pulse + port ( + clock : in std_logic; + en_clk : in std_logic; + signal_in : in std_logic; + pulse : out std_logic); + end component; + signal VIRT_CLK : std_logic; signal VIRT_CLKB : std_logic; signal RESET_VIRT : std_logic; signal DBAD : std_logic; @@ -339,6 +346,15 @@ ARCHITECTURE behavior OF trb_v2b_fpga_tb IS signal dtu_lvl2_tag : std_logic_vector(7 downto 0); signal lvl1_trig : std_logic; signal lvl2_trig : std_logic; + signal fpga_data_out : std_logic_vector(31 downto 0); + signal valid_pulse_i : std_logic; + signal not_valid_pulse_i : std_logic; + signal not_valid : std_logic; + signal etrax_ready : std_logic; + signal etrax_ready_pulse : std_logic; + signal save_lenght : std_logic_vector(15 downto 0); + signal compare_counter : std_logic_vector(15 downto 0); + signal wrong_lenght_of_event : std_logic; BEGIN trb: trb_v2b_fpga port map ( @@ -513,7 +529,7 @@ BEGIN --reading DSP(dev number 1) wait for 10 ns; RESET_VIRT <= '0'; - + etrax_ready <= '0'; wait for 10 ns; FS_PC(16) <= '1'; FS_PC(17) <= '1'; @@ -585,13 +601,13 @@ BEGIN wait for 20 ns; FS_PC(16) <= '0'; wait for 20 ns; - FS_PC(15 downto 0) <= x"0004"; --data upper part + FS_PC(15 downto 0) <= x"0000"; --data upper part FS_PC(16) <= '1'; FS_PC(17) <= '0'; wait for 20 ns; FS_PC(16) <= '0'; wait for 20 ns; - FS_PC(15 downto 0) <= x"0000"; --data lower part - 1 switch on + FS_PC(15 downto 0) <= x"0100"; --data lower part - 1 switch on --internal generation of trigger FS_PC(16) <= '1'; FS_PC(17) <= '0'; @@ -606,8 +622,11 @@ BEGIN -- wait on VIRT_CLK until FS_PB(16)= '1'; loop wait on VIRT_CLK until FS_PB(16) = '1'; + wait for 50 ns; FS_PC(17) <= '1'; + etrax_ready <= '1'; wait for 50 ns; + etrax_ready <= '0'; FS_PC(17) <= '0'; wait for 50 ns; end loop; @@ -682,9 +701,50 @@ BEGIN --TLK_RX_ER <= '0'; TLK_RX_DV <= '1'; ----------------------------------------------------------------------- + -- process check headers - number of words in event + ----------------------------------------------------------------------- + fpga_data_out <= FS_PC(15 downto 0) & FS_PB(15 downto 0); + valid_pulse: edge_to_pulse + port map ( + clock => VIRT_CLK, + en_clk => '1', + signal_in => FS_PB(16), + pulse => valid_pulse_i); + not_valid <= FS_PB(16); + not_valid_pulse: edge_to_pulse + port map ( + clock => VIRT_CLK, + en_clk => '1', + signal_in => not_valid, + pulse => not_valid_pulse_i); + etrax_pulse: edge_to_pulse + port map ( + clock => VIRT_CLK, + en_clk => '1', + signal_in => etrax_ready, + pulse => etrax_ready_pulse); + + ckeck_header: process(VIRT_CLK,valid_pulse_i,etrax_ready_pulse ) + begin + if rising_edge(VIRT_CLK) then + if valid_pulse_i = '1' then + save_lenght <= FS_PB(15 downto 0); + compare_counter <= (others => '0'); + elsif etrax_ready_pulse = '1' then + save_lenght <= save_lenght; + compare_counter <= compare_counter + 1; + else + save_lenght <= save_lenght; + compare_counter <= compare_counter; + end if; + end if; + end process ckeck_header; + wrong_lenght_of_event <= '1' when ((save_lenght /= compare_counter) and FS_PB(16) = '0') else '0'; + ----------------------------------------------------------------------- -- TDC ----------------------------------------------------------------------- clock_tdcclk : process + begin wait for 12 ns; loop @@ -697,6 +757,7 @@ BEGIN end loop; end process; trigger_lvl1 : process + variable valid_time : integer :=0; begin -- ADO_TTL(7) <= '0'; A_DATA_READY <= '0'; @@ -716,17 +777,21 @@ BEGIN wait for 10 ns; -- ADO_TTL(7) <= '0'; A_DATA_READY <= '1'; - wait for 50 ns; +-- wait for 50 ns; + wait for ((valid_time mod 2)*50*3+2*25)*ns; A_DATA_READY <= '0'; B_DATA_READY <= '1'; - wait for 50 ns; +-- wait for 50 ns; + wait for ((valid_time mod 3 )*50*2+2*25)*ns; B_DATA_READY <= '0'; C_DATA_READY <= '1'; - wait for 50 ns; +-- wait for 50 ns; + wait for ((valid_time mod 5 )*50+2*25)*ns; -- ADO_TTL(7) <= '0'; C_DATA_READY <= '0'; D_DATA_READY <= '1'; - wait for 50 ns; + --wait for 50 ns; + wait for ((valid_time mod 7 )*50+2*25)*ns; D_DATA_READY <= '0'; wait for 0 ns; -- ADO_TTL(6) <= '1'; @@ -735,6 +800,7 @@ BEGIN -- ADO_TTL(6) <= '0'; TOKEN_IN <= '0'; -- wait on REF_TDC_CLK until DBAD = '0'; + valid_time := valid_time*3/2 +1; end process; -- trigger_lvl2 : process -- begin @@ -752,172 +818,183 @@ BEGIN ----------------------------------------------------------------------- -- DTU ----------------------------------------------------------------------- - clock_dtu : process - begin - wait for 34 ns; +-- clock_dtu : process +-- begin +-- wait for 34 ns; - loop - dtu_clk <= '0'; - wait for 50 ns; - dtu_clk <= '1'; - wait for 50 ns; - end loop; - end process; - ADO_TTL(4) <= lvl1_trig; - ADO_TTL(10) <= lvl2_trig; +-- loop +-- dtu_clk <= '0'; +-- wait for 50 ns; +-- dtu_clk <= '1'; +-- wait for 50 ns; +-- end loop; +-- end process; +-- ADO_TTL(4) <= lvl1_trig; +-- ADO_TTL(10) <= lvl2_trig; - -- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig) - -- begin - -- if rising_edge(dtu_clk) then - -- if RESET_VIRT = '0' then - -- dtu_lvl1_tag <= x"00"; - -- elsif ADO_TTL(17) = '1' then - -- dtu_lvl1_tag <= dtu_lvl1_tag +1; - -- end if; - -- end if; - -- end process LVL1_TAG_COUNTER; - LVL1_COUNT:process - begin - wait for 100 ns; - dtu_lvl1_tag <= x"00"; - wait on dtu_clk until ADO_TTL(0) = '0'; - wait on dtu_clk until lvl1_trig = '1'; - wait for 500 ns; - dtu_lvl1_tag <= dtu_lvl1_tag +1; - loop - wait on dtu_clk until ADO_TTL(0) = '1'; - -- wait for 1000 ns; - dtu_lvl1_tag <= dtu_lvl1_tag +1; - wait on dtu_clk until ADO_TTL(0) = '0'; - end loop; - end process LVL1_COUNT; - LVL2_COUNT:process - begin - wait for 100 ns; - dtu_lvl2_tag <= x"00"; - wait on dtu_clk until ADO_TTL(2) = '0'; - loop - -- wait on dtu_clk until ADO_TTL(2) = '1'; - wait on dtu_clk until lvl2_trig = '1'; - -- wait for 1000 ns; - wait for 500 ns; - dtu_lvl2_tag <= dtu_lvl2_tag +1; - wait on dtu_clk until ADO_TTL(2) = '0'; - end loop; - end process LVL2_COUNT; +-- -- LVL1_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl1_trig) +-- -- begin +-- -- if rising_edge(dtu_clk) then +-- -- if RESET_VIRT = '0' then +-- -- dtu_lvl1_tag <= x"00"; +-- -- elsif ADO_TTL(17) = '1' then +-- -- dtu_lvl1_tag <= dtu_lvl1_tag +1; +-- -- end if; +-- -- end if; +-- -- end process LVL1_TAG_COUNTER; +-- LVL1_COUNT:process +-- begin +-- wait for 100 ns; +-- dtu_lvl1_tag <= x"00"; +-- wait on dtu_clk until ADO_TTL(0) = '0'; +-- wait on dtu_clk until lvl1_trig = '1'; +-- wait for 500 ns; +-- dtu_lvl1_tag <= dtu_lvl1_tag +1; +-- loop +-- wait on dtu_clk until ADO_TTL(0) = '1'; +-- -- wait for 1000 ns; +-- dtu_lvl1_tag <= dtu_lvl1_tag +1; +-- wait on dtu_clk until ADO_TTL(0) = '0'; +-- end loop; +-- end process LVL1_COUNT; +-- LVL2_COUNT:process +-- begin +-- wait for 100 ns; +-- dtu_lvl2_tag <= x"00"; +-- wait on dtu_clk until ADO_TTL(2) = '0'; +-- loop +-- -- wait on dtu_clk until ADO_TTL(2) = '1'; +-- wait on dtu_clk until lvl2_trig = '1'; +-- -- wait for 1000 ns; +-- wait for 500 ns; +-- dtu_lvl2_tag <= dtu_lvl2_tag +1; +-- wait on dtu_clk until ADO_TTL(2) = '0'; +-- end loop; +-- end process LVL2_COUNT; - -- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig) - -- begin - -- if rising_edge(dtu_clk) then - -- if RESET_VIRT = '0' then - -- dtu_lvl2_tag <= x"00"; - -- elsif lvl2_trig = '1' then - -- dtu_lvl2_tag <= dtu_lvl2_tag +1; - -- end if; - -- end if; - -- end process LVL2_TAG_COUNTER; - -- ADO_TTL(20 downto 17) <= (others => 'Z'); +-- -- LVL2_TAG_COUNTER: process (dtu_clk,RESET_VIRT,lvl2_trig) +-- -- begin +-- -- if rising_edge(dtu_clk) then +-- -- if RESET_VIRT = '0' then +-- -- dtu_lvl2_tag <= x"00"; +-- -- elsif lvl2_trig = '1' then +-- -- dtu_lvl2_tag <= dtu_lvl2_tag +1; +-- -- end if; +-- -- end if; +-- -- end process LVL2_TAG_COUNTER; +-- -- ADO_TTL(20 downto 17) <= (others => 'Z'); - ADO_TTL(4) <= lvl1_trig; - DTU_EMULATION_LVL1: process - begin - ADO_TTL(9) <= '0'; - lvl1_trig <= '0'; - wait for 1000 ns; - wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1 - lvl1_trig <= '1'; - ADO_TTL(8 downto 5) <= x"d"; - wait for 100 ns; - lvl1_trig <= '0'; - wait for 100 ns; - ADO_TTL(9) <= '1'; - ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0); - wait for 100 ns; - ADO_TTL(9) <= '0'; - wait for 100 ns; - ADO_TTL(9) <= '1'; - ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4); - loop - wait for 100 ns; - ADO_TTL(9) <= '0'; - wait for 100 ns; - ADO_TTL(9) <= '1'; - wait for 100 ns; - ADO_TTL(9) <= '0'; - wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1 - wait for 300 ns; - lvl1_trig <= '1'; - ADO_TTL(8 downto 5) <= x"1"; - wait for 100 ns; - lvl1_trig <= '0'; - wait for 100 ns; - ADO_TTL(9) <= '1'; - ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0); - wait for 100 ns; - ADO_TTL(9) <= '0'; - wait for 100 ns; - ADO_TTL(9) <= '1'; - ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4); - end loop; - end process DTU_EMULATION_LVL1; +-- ADO_TTL(4) <= lvl1_trig; +-- DTU_EMULATION_LVL1: process +-- begin +-- ADO_TTL(9) <= '0'; +-- lvl1_trig <= '0'; +-- wait for 1000 ns; +-- wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1 +-- lvl1_trig <= '1'; +-- ADO_TTL(8 downto 5) <= x"d"; +-- wait for 100 ns; +-- lvl1_trig <= '0'; +-- wait for 100 ns; +-- ADO_TTL(9) <= '1'; +-- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0); +-- wait for 100 ns; +-- ADO_TTL(9) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(9) <= '1'; +-- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4); +-- loop +-- wait for 100 ns; +-- ADO_TTL(9) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(9) <= '1'; +-- wait for 100 ns; +-- ADO_TTL(9) <= '0'; +-- wait on dtu_clk until ADO_TTL(0) = '0' and dtu_clk = '1'; --busylvl1 +-- wait for 300 ns; +-- lvl1_trig <= '1'; +-- ADO_TTL(8 downto 5) <= x"1"; +-- wait for 100 ns; +-- lvl1_trig <= '0'; +-- wait for 100 ns; +-- ADO_TTL(9) <= '1'; +-- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(3 downto 0); +-- wait for 100 ns; +-- ADO_TTL(9) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(9) <= '1'; +-- ADO_TTL(8 downto 5) <= dtu_lvl1_tag(7 downto 4); +-- end loop; +-- end process DTU_EMULATION_LVL1; - ADO_TTL(10) <= lvl2_trig; - DTU_EMULATION_LVL2:process - begin - ADO_TTL(15) <= '0'; - lvl2_trig <= '0'; - wait for 26000 ns; - loop - ADO_TTL(15) <= '0'; - wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; --busylvl2 - -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1; - wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01"; - wait for 300 ns; - lvl2_trig <= '1'; - ADO_TTL(14 downto 11) <= x"1"; - wait for 100 ns; - lvl2_trig <= '0'; - wait for 100 ns; - ADO_TTL(15) <= '1'; - ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0); - wait for 100 ns; - ADO_TTL(15) <= '0'; - wait for 100 ns; - ADO_TTL(15) <= '1'; - ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4); - wait for 100 ns; - ADO_TTL(15) <= '0'; - wait for 100 ns; - ADO_TTL(15) <= '1'; - wait for 100 ns; - ADO_TTL(15) <= '0'; +-- ADO_TTL(10) <= lvl2_trig; +-- DTU_EMULATION_LVL2:process +-- begin +-- ADO_TTL(15) <= '0'; +-- lvl2_trig <= '0'; +-- wait for 26000 ns; +-- loop +-- ADO_TTL(15) <= '0'; +-- wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; --busylvl2 +-- -- wait on dtu_clk until dtu_lvl1_tag > dtu_lvl2_tag + 1; +-- wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01"; +-- wait for 300 ns; +-- lvl2_trig <= '1'; +-- ADO_TTL(14 downto 11) <= x"1"; +-- wait for 100 ns; +-- lvl2_trig <= '0'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '1'; +-- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0); +-- wait for 100 ns; +-- ADO_TTL(15) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '1'; +-- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4); +-- wait for 100 ns; +-- ADO_TTL(15) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '1'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '0'; - wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; - wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01"; - wait for 100 ns; - lvl2_trig <= '1'; - ADO_TTL(14 downto 11) <= x"9"; - wait for 100 ns; - lvl2_trig <= '0'; - wait for 100 ns; - ADO_TTL(15) <= '1'; - ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0); - wait for 100 ns; - ADO_TTL(15) <= '0'; - wait for 100 ns; - ADO_TTL(15) <= '1'; - ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4); - wait for 100 ns; - ADO_TTL(15) <= '0'; - wait for 100 ns; - ADO_TTL(15) <= '1'; - wait for 100 ns; - ADO_TTL(15) <= '0'; +-- wait on dtu_clk until ADO_TTL(2) = '0'and dtu_clk = '1'; +-- wait on dtu_clk until dtu_lvl1_tag - dtu_lvl2_tag > x"01"; +-- wait for 100 ns; +-- lvl2_trig <= '1'; +-- ADO_TTL(14 downto 11) <= x"9"; +-- wait for 100 ns; +-- lvl2_trig <= '0'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '1'; +-- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(3 downto 0); +-- wait for 100 ns; +-- ADO_TTL(15) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '1'; +-- ADO_TTL(14 downto 11) <= dtu_lvl2_tag(7 downto 4); +-- wait for 100 ns; +-- ADO_TTL(15) <= '0'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '1'; +-- wait for 100 ns; +-- ADO_TTL(15) <= '0'; +-- end loop; +-- end process DTU_EMULATION_LVL2; +------------------------------------------------------------------------------- +-- if external trigger +------------------------------------------------------------------------------- + send_external_trigger: process + begin + loop + ADO_TTL(0) <= '0'; + wait for 10 ns; + ADO_TTL(0) <= '1'; + wait for 10 ns; end loop; - end process DTU_EMULATION_LVL2; - + end process send_external_trigger; -- ETRAX_RESPONSE: process -- begin -- FS_PC(16) <= '0';