From: Thomas Gessler Date: Tue, 23 Mar 2021 15:15:46 +0000 (+0100) Subject: Adapt TrbNet-DCA bridge for synthesis X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6a3d1a49ab9a75853cd45e36a3b424af3ec0bdd6;p=cri.git Adapt TrbNet-DCA bridge for synthesis This includes the addition of XCKU FIFO cores and some changes to the HDL codes. This likely breaks the current simulation testbench, which will have to be fixed in a future commit. --- diff --git a/src/DCA_cores/xcku/.gitignore b/src/DCA_cores/xcku/.gitignore new file mode 100644 index 0000000..de8b137 --- /dev/null +++ b/src/DCA_cores/xcku/.gitignore @@ -0,0 +1 @@ +/*/build/ diff --git a/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd b/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd new file mode 100644 index 0000000..a3388e2 --- /dev/null +++ b/src/DCA_cores/xcku/fifo_2kx34x17_wcnt.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_2kx34x17_wcnt is + port ( + Data : in std_logic_vector(33 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(16 downto 0); + WCNT : out std_logic_vector(11 downto 0); + Empty : out std_logic; + Full : out std_logic + ); +end fifo_2kx34x17_wcnt; + +architecture structural of fifo_2kx34x17_wcnt is + component fifo_2kx34x17_wcnt_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(33 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(16 downto 0); + full : out std_logic; + empty : out std_logic; + wr_data_count : out std_logic_vector(10 downto 0); + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; + + signal full_i : std_logic; +begin + fifo : fifo_2kx34x17_wcnt_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => full_i, + empty => Empty, + wr_data_count => WCNT(10 downto 0), + wr_rst_busy => open, + rd_rst_busy => open + ); + + WCNT(11) <= full_i; + Full <= full_i; +end architecture structural; diff --git a/src/DCA_cores/xcku/fifo_2kx34x17_wcnt_xcku/fifo_2kx34x17_wcnt_xcku.xci b/src/DCA_cores/xcku/fifo_2kx34x17_wcnt_xcku/fifo_2kx34x17_wcnt_xcku.xci new file mode 100644 index 0000000..827fbb7 --- /dev/null +++ b/src/DCA_cores/xcku/fifo_2kx34x17_wcnt_xcku/fifo_2kx34x17_wcnt_xcku.xci @@ -0,0 +1,577 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_2kx34x17_wcnt_xcku + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + BlankString + 34 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 17 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintexu + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 2kx18 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2045 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 2044 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 12 + 4096 + 1 + 12 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 2048 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 11 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_2kx34x17_wcnt_xcku + 64 + false + 11 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + true + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 0 + 2045 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 2044 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 34 + 2048 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 17 + 4096 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 12 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + true + 11 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + build + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd b/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd new file mode 100644 index 0000000..460b318 --- /dev/null +++ b/src/DCA_cores/xcku/fifo_4kx16x32_wcnt.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_4kx16x32_wcnt is + port ( + Data : in std_logic_vector(15 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(31 downto 0); + WCNT : out std_logic_vector(11 downto 0); + Empty : out std_logic; + Full : out std_logic + ); +end fifo_4kx16x32_wcnt; + +architecture structural of fifo_4kx16x32_wcnt is + component fifo_4kx16x32_wcnt_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(15 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(31 downto 0); + full : out std_logic; + empty : out std_logic; + wr_data_count : out std_logic_vector(10 downto 0); + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; + + signal full_i : std_logic; +begin + fifo : fifo_4kx16x32_wcnt_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => full_i, + empty => Empty, + wr_data_count => WCNT(10 downto 0), + wr_rst_busy => open, + rd_rst_busy => open + ); + + WCNT(11) <= full_i; + Full <= full_i; +end architecture structural; diff --git a/src/DCA_cores/xcku/fifo_4kx16x32_wcnt_xcku/fifo_4kx16x32_wcnt_xcku.xci b/src/DCA_cores/xcku/fifo_4kx16x32_wcnt_xcku/fifo_4kx16x32_wcnt_xcku.xci new file mode 100644 index 0000000..2e698a9 --- /dev/null +++ b/src/DCA_cores/xcku/fifo_4kx16x32_wcnt_xcku/fifo_4kx16x32_wcnt_xcku.xci @@ -0,0 +1,577 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_4kx16x32_wcnt_xcku + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 11 + BlankString + 16 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintexu + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 2kx18 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2045 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 2044 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 10 + 1024 + 1 + 10 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 11 + 2048 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 11 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_4kx16x32_wcnt_xcku + 64 + false + 11 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + true + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 0 + 2045 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 2044 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 16 + 2048 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 32 + 1024 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 10 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + true + 11 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + build + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd b/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd new file mode 100644 index 0000000..e07874d --- /dev/null +++ b/src/DCA_cores/xcku/fifo_64kx16x32_wcnt.vhd @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity fifo_64kx16x32_wcnt is + port ( + Data : in std_logic_vector(15 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(31 downto 0); + WCNT : out std_logic_vector(15 downto 0); + Empty : out std_logic; + Full : out std_logic + ); +end fifo_64kx16x32_wcnt; + +architecture structural of fifo_64kx16x32_wcnt is + component fifo_64kx16x32_wcnt_xcku + port ( + rst : in std_logic; + wr_clk : in std_logic; + rd_clk : in std_logic; + din : in std_logic_vector(15 downto 0); + wr_en : in std_logic; + rd_en : in std_logic; + dout : out std_logic_vector(31 downto 0); + full : out std_logic; + empty : out std_logic; + wr_data_count : out std_logic_vector(14 downto 0); + wr_rst_busy : out std_logic; + rd_rst_busy : out std_logic + ); + end component; + + signal full_i : std_logic; +begin + fifo : fifo_64kx16x32_wcnt_xcku + port map ( + rst => Reset, + wr_clk => WrClock, + rd_clk => RdClock, + din => Data, + wr_en => WrEn, + rd_en => RdEn, + dout => Q, + full => full_i, + empty => Empty, + wr_data_count => WCNT(14 downto 0), + wr_rst_busy => open, + rd_rst_busy => open + ); + + WCNT(15) <= full_i; + Full <= full_i; +end architecture structural; diff --git a/src/DCA_cores/xcku/fifo_64kx16x32_wcnt_xcku/fifo_64kx16x32_wcnt_xcku.xci b/src/DCA_cores/xcku/fifo_64kx16x32_wcnt_xcku/fifo_64kx16x32_wcnt_xcku.xci new file mode 100644 index 0000000..e66b0e9 --- /dev/null +++ b/src/DCA_cores/xcku/fifo_64kx16x32_wcnt_xcku/fifo_64kx16x32_wcnt_xcku.xci @@ -0,0 +1,577 @@ + + + xilinx.com + xci + unknown + 1.0 + + + fifo_64kx16x32_wcnt_xcku + + + + + + 100000000 + 0 + 0 + 0.000 + + + 100000000 + 0 + 0 + 0.000 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + + 100000000 + 0 + 0 + 0.000 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + + 100000000 + 0 + 0 + 0 + 0 + 0 + undef + 0.000 + 0 + 0 + 0 + 0 + + + + 100000000 + 0 + 0 + 0.000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 1 + 1 + 1 + 4 + 0 + 32 + 1 + 1 + 1 + 64 + 1 + 8 + 1 + 1 + 1 + 1 + 0 + 0 + 15 + BlankString + 16 + 1 + 32 + 64 + 1 + 64 + 2 + 0 + 32 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + kintexu + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 2 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + BlankString + 1 + 0 + 0 + 0 + 1 + 0 + 8kx4 + 1kx18 + 512x36 + 512x72 + 512x36 + 512x72 + 512x36 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 32765 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 32764 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 14 + 16384 + 1 + 14 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 15 + 32768 + 1024 + 16 + 1024 + 16 + 1024 + 16 + 1 + 15 + 10 + 4 + 10 + 4 + 10 + 4 + 1 + 32 + 0 + 0 + false + false + false + 0 + 0 + Slave_Interface_Clock_Enable + Common_Clock + fifo_64kx16x32_wcnt_xcku + 64 + false + 15 + false + false + 0 + 2 + 1022 + 1022 + 1022 + 1022 + 1022 + 1022 + 3 + false + false + false + false + false + false + false + false + false + Hard_ECC + false + false + false + false + false + false + true + true + false + true + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Data_FIFO + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Common_Clock_Block_RAM + Independent_Clocks_Block_RAM + 0 + 32765 + 1023 + 1023 + 1023 + 1023 + 1023 + 1023 + 32764 + false + false + false + 0 + Native + false + false + false + false + false + false + false + false + false + false + false + false + false + false + 16 + 32768 + 1024 + 16 + 1024 + 16 + 1024 + 16 + false + 32 + 16384 + Embedded_Reg + false + false + Active_High + Active_High + AXI4 + Standard_FIFO + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Empty_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + No_Programmable_Full_Threshold + READ_WRITE + 0 + 1 + false + 14 + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + Fully_Registered + true + Asynchronous_Reset + false + 1 + 0 + 0 + 1 + 1 + 4 + false + false + Active_High + Active_High + true + false + false + false + false + Active_High + 0 + false + Active_High + 1 + true + 15 + true + FIFO + false + false + false + false + FIFO + FIFO + 2 + 2 + false + FIFO + FIFO + FIFO + kintexu + + + xcku115 + flvf1924 + VHDL + + MIXED + -2 + + E + TRUE + TRUE + IP_Flow + 5 + TRUE + build + + . + 2020.1 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/agwb_handler_dca_sim.vhd b/src/agwb_handler_dca_sim.vhd index 6aed9db..1579ec8 100644 --- a/src/agwb_handler_dca_sim.vhd +++ b/src/agwb_handler_dca_sim.vhd @@ -5,8 +5,8 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; --- just for simulation purpose -use work.wishbone_pkg.all; +library general_cores; +use general_cores.wishbone_pkg.all; entity agwb_handler_dca_sim is port ( diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd index 22cfa89..f84303b 100644 --- a/src/cri_trbnet_dca_bridge.vhd +++ b/src/cri_trbnet_dca_bridge.vhd @@ -7,8 +7,8 @@ library work; use work.trb_net_std.all; use work.trb_net_components.all; --- just for simulation purpose -use work.wishbone_pkg.all; +library general_cores; +use general_cores.wishbone_pkg.all; entity cri_trbnet_dca_bridge is generic ( @@ -18,6 +18,7 @@ entity cri_trbnet_dca_bridge is CLK : in std_logic; -- system clock RESET : in std_logic; CLK_DCA : in std_logic; -- 40 MHz clock of DCA + RST_N_DCA : in std_logic; -- DCA INTERFACE WB_SLAVE_IN : in t_wishbone_slave_in; @@ -45,6 +46,8 @@ end entity cri_trbnet_dca_bridge; architecture RTL of cri_trbnet_dca_bridge is +signal reset_dca : std_logic; + attribute syn_encoding : string; type dissect_states is (IDLE, GET_DCA_DATA, WAIT_FOR_HUB, LOAD_TO_HUB, WAIT_FOR_RESPONSE, SAVE_RESPONSE, CHECK_RESPONSE, LOAD_FRAME, WAIT_FOR_LOAD, CLEANUP); @@ -124,6 +127,7 @@ signal preload_word_tx_fifo : std_logic; signal tx_data_out : std_logic_vector(31 downto 0); begin + reset_dca <= not RST_N_DCA; -- from wishbone: -- rx_data_wr -> both delayed by one clk_cyc to rearrange data. @@ -131,7 +135,7 @@ begin THE_DCA_HANDLER : entity work.cri_trbnet_dca_bridge_handler port map ( CLK => CLK, - RESET => RESET, + RST_N => RST_N_DCA, CLK_DCA => CLK_DCA, -- DCA INTERFACE @@ -191,7 +195,7 @@ THE_SYNC_RX_DATA : entity work.signal_sync THE_SYNC_RX_STB : entity work.pulse_sync port map( - RESET_A_IN => RESET, + RESET_A_IN => reset_dca, CLK_A_IN => CLK_DCA, PULSE_A_IN => rx_data_wr, @@ -202,7 +206,7 @@ THE_SYNC_RX_DATA : entity work.signal_sync THE_SYNC_TX_RD_ACK : entity work.pulse_sync port map( - RESET_A_IN => RESET, + RESET_A_IN => reset_dca, CLK_A_IN => CLK_DCA, PULSE_A_IN => tx_rd_ack, @@ -213,7 +217,7 @@ THE_SYNC_RX_DATA : entity work.signal_sync THE_SYNC_TX_SIZE_ACK : entity work.pulse_sync port map( - RESET_A_IN => RESET, + RESET_A_IN => reset_dca, CLK_A_IN => CLK_DCA, PULSE_A_IN => tx_rd_size_ack, diff --git a/src/cri_trbnet_dca_bridge_handler.vhd b/src/cri_trbnet_dca_bridge_handler.vhd index 6e37bcf..0b704ca 100644 --- a/src/cri_trbnet_dca_bridge_handler.vhd +++ b/src/cri_trbnet_dca_bridge_handler.vhd @@ -6,16 +6,18 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; --- just for simulation purpose -use work.wishbone_pkg.all; +library general_cores; +use general_cores.wishbone_pkg.all; + +library agwb; entity cri_trbnet_dca_bridge_handler is generic ( - SIMULATION : integer := c_YES + SIMULATION : integer := c_NO ); port ( CLK : in std_logic; -- system clock - RESET : in std_logic; + RST_N : in std_logic; CLK_DCA : in std_logic; -- 40 MHz clock of DCA -- DCA INTERFACE @@ -89,34 +91,29 @@ GEN_AGWB_HANDLER_SIM: if SIMULATION = c_YES generate ); end generate; ---GEN_AGWB_HANDLER_REAL: if SIMULATION = c_NO generate --- trbnetBridge : entity agwb.trbnetBridge --- generic map ( --- g_ver_id => v_test_device_ver_id(g_slr) --- ) --- port map ( --- slave_i => WB_SLAVE_IN, --- slave_o => WB_SLAVE_OUT, --- --- RX_DATA_MAIN_o => data_in_normal, --- RX_DATA_MAIN_o_stb => data_in_normal_stb, --- --- RX_DATA_END_o => data_in_end, --- RX_DATA_END_o_stb => data_in_end_stb, --- --- TX_DATA_i => TX_DATA_IN, --- TX_DATA_i_ack => TX_READ_ACK, --- --- TX_SIZE_i(31 downto 16) => (others => '0'), --- TX_SIZE_i(15 downto 0) => TX_DATA_SIZE, --- TX_SIZE_i_ack => TX_READ_SIZE_ACK, --- --- rst_n_i => rst_n_i, --- clk_sys_i => CLK_DCA --- ); --- end generate; - -rst_n_i <= not RESET; +GEN_AGWB_HANDLER_REAL: if SIMULATION = c_NO generate + trbnetBridge : entity agwb.trbnetBridge + port map ( + slave_i => WB_SLAVE_IN, + slave_o => WB_SLAVE_OUT, + + RX_DATA_MAIN_o => data_in_normal, + RX_DATA_MAIN_o_stb => data_in_normal_stb, + + RX_DATA_END_o => data_in_end, + RX_DATA_END_o_stb => data_in_end_stb, + + TX_DATA_i => TX_DATA_IN, + TX_DATA_i_ack => TX_READ_ACK, + + TX_SIZE_i(31 downto 16) => (others => '0'), + TX_SIZE_i(15 downto 0) => TX_DATA_SIZE, + TX_SIZE_i_ack => TX_READ_SIZE_ACK, + + rst_n_i => rst_n_i, + clk_sys_i => CLK_DCA + ); +end generate; THE_RX_FSM : process begin @@ -124,7 +121,7 @@ begin RX_DATA_RDY <= '0'; - if RESET = '1' then + if RST_N = '0' then rx_state <= IDLE; data_in_buf <= x"0000"; else