From: Your Name <you@example.com>
Date: Fri, 8 Jul 2016 12:46:52 +0000 (+0200)
Subject: gbe update
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6a59812489b22f22f487283e06d70a3f09a916f9;p=trb3.git

gbe update
---

diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj
index fc2db73..3a05cc6 100644
--- a/cts/trb3_central.prj
+++ b/cts/trb3_central.prj
@@ -87,7 +87,7 @@ add_file -vhdl -lib work "../base/code/trigger_clock_manager.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd"
 add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd"
 
-add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
+#add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd"
 add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd"
diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd
index 88c0a89..8bd5827 100644
--- a/cts/trb3_central.vhd
+++ b/cts/trb3_central.vhd
@@ -2011,22 +2011,22 @@ begin
 ---------------------------------------------------------------------------
 -- Debugging UART
 --------------------------------------------------------------------------- 
-  THE_DEBUG : entity work.debuguart
-    port map(
-      CLK => clk_100_i,
-      RESET => reset_i, 
+--  THE_DEBUG : entity work.debuguart
+--    port map(
+--      CLK => clk_100_i,
+--      RESET => reset_i, 
       
-      RX_IN  => TEST_LINE(30),
-      TX_OUT => TEST_LINE(31),
+--      RX_IN  => TEST_LINE(30),
+--      TX_OUT => TEST_LINE(31),
       
-      DEBUG_ACTIVE  => debug_active,
+--      DEBUG_ACTIVE  => debug_active,
     
-      BUS_DEBUG_TX  => bus_debug_tx_in,
-      BUS_DEBUG_RX  => bus_debug_rx_out,
+--      BUS_DEBUG_TX  => bus_debug_tx_in,
+--      BUS_DEBUG_RX  => bus_debug_rx_out,
       
-      STATUS => open
+--      STATUS => open
       
-      );  
+--      );  
 
   handler_addr     <= bus_debug_rx_out.addr  when debug_active = '1' else regio_addr_out;
   handler_data_out <= bus_debug_rx_out.data  when debug_active = '1' else regio_data_out;
diff --git a/trb3_gbe/trb3_central_gbe.vhd b/trb3_gbe/trb3_central_gbe.vhd
index e7fd3f2..29d5a81 100644
--- a/trb3_gbe/trb3_central_gbe.vhd
+++ b/trb3_gbe/trb3_central_gbe.vhd
@@ -689,13 +689,13 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4
       FIXED_DELAY               => 100,
 
       NUMBER_OF_GBE_LINKS       => 4,
-      LINKS_ACTIVE              => "1100",
+      LINKS_ACTIVE              => "1000",
 
-      LINK_HAS_READOUT  => "1100",
+      LINK_HAS_READOUT  => "1000",
       LINK_HAS_SLOWCTRL => "1000",
-      LINK_HAS_DHCP     => "1100",
-      LINK_HAS_ARP      => "1100",
-      LINK_HAS_PING     => "1100"
+      LINK_HAS_DHCP     => "1000",
+      LINK_HAS_ARP      => "1000",
+      LINK_HAS_PING     => "1000"
       
       )
     port map(