From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Fri, 19 Aug 2022 06:19:48 +0000 (+0200)
Subject: new SCI reader
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6b287c4910aa46aaeb94e5b6944d3930eb172584;p=trbnet.git

new SCI reader
---

diff --git a/gbe_trb/base/gbe_sci_reader.vhd b/gbe_trb/base/gbe_sci_reader.vhd
new file mode 100644
index 0000000..f1adca5
--- /dev/null
+++ b/gbe_trb/base/gbe_sci_reader.vhd
@@ -0,0 +1,88 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.numeric_std.all;
+  
+library work;
+  use work.trb_net_components.all;
+  use work.trb_net_std.all;
+  use work.trb3_components.all;
+  use work.config.all;
+
+entity gbe_sci_reader is
+
+  port(
+    CLK              : in std_logic;
+    RESET            : in std_logic;
+    --SCI
+    SCI_WRDATA       : out std_logic_vector(7 downto 0);
+    SCI_RDDATA       : in  std_logic_vector(7 downto 0);
+    SCI_ADDR         : out std_logic_vector(5 downto 0);
+    SCI_SEL          : out std_logic_vector(4 downto 0);
+    SCI_RD           : out std_logic;
+    SCI_WR           : out std_logic;
+    -- WAP stuff
+    WA_POS_OUT       : out std_logic_vector(15 downto 0)
+  );
+end entity gbe_sci_reader;
+
+architecture gbe_sci_reader_arch of gbe_sci_reader is
+
+type sci_ctrl is (IDLE, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH);
+
+signal sci_state         : sci_ctrl;
+signal sci_timer         : unsigned(16 downto 0) := (others => '0');
+
+signal wa_position       : std_logic_vector(15 downto 0);
+
+begin
+
+------------------------------------------------      
+-- SCI
+-------------------------------------------------      
+
+  PROC_SCI_CTRL: process 
+    variable cnt : integer range 0 to 4 := 0;
+  begin
+    wait until rising_edge(CLK);
+      
+    case sci_state is
+      when IDLE =>
+        SCI_SEL     <= (others => '0');
+        SCI_RD      <= '0';
+        sci_timer   <= sci_timer + 1;
+        if( sci_timer(sci_timer'left) = '1' ) then
+          sci_timer     <= (others => '0');
+          sci_state     <= GET_WA;
+        end if;      
+      when GET_WA =>
+        if( ((cnt = 4) and (FPGA_TYPE = 3)) or ((cnt = 2) and (FPGA_TYPE = 5)) ) then
+          cnt           := 0;
+          sci_state     <= IDLE;
+        else
+          sci_state     <= GET_WA_WAIT;
+          if   ( FPGA_TYPE = 3 ) then
+            SCI_ADDR      <= "100010"; -- x"22" for ECP3
+          elsif( FPGA_TYPE = 5 ) then
+            SCI_ADDR      <= "110010"; -- x"32" for ECP5
+          end if;  
+          SCI_SEL       <= (others => '0');
+          SCI_SEL(cnt)  <= '1';
+          SCI_RD        <= '1';
+        end if;
+      when GET_WA_WAIT  =>
+        sci_state       <= GET_WA_WAIT2;
+      when GET_WA_WAIT2 =>
+        sci_state       <= GET_WA_FINISH;
+      when GET_WA_FINISH =>
+        wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0);
+        sci_state       <= GET_WA;
+        cnt             := cnt + 1;
+    end case;
+  
+  end process PROC_SCI_CTRL;
+
+  SCI_WR <= '0';
+  
+  WA_POS_OUT <= wa_position;
+  
+end architecture;