From: Adrian Weber <adrian.a.weber@exp2.physik.uni-giessen.de>
Date: Thu, 3 Sep 2020 08:34:33 +0000 (+0200)
Subject: recovered clock for mbs and debug outputs on rj45
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6b87fefe80ff3ff3ab4b3bce9c4a72c0cfaad967;p=dirich.git

recovered clock for mbs and debug outputs on rj45
---

diff --git a/combiner_cts/combiner.prj b/combiner_cts/combiner.prj
index f9bca51..fa8d943 100644
--- a/combiner_cts/combiner.prj
+++ b/combiner_cts/combiner.prj
@@ -208,8 +208,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd"
 add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd"
 add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd"
 
-add_file -vhdl -lib work "../../trbnet/xilinx/xcku/trb_net_xdna.vhd"
-add_file -vhdl -lib work "../../trbnet/xilinx/xcku/read_dna_address.vhd"
+#add_file -vhdl -lib work "../../trbnet/xilinx/xcku/trb_net_xdna.vhd"
+#add_file -vhdl -lib work "../../trbnet/xilinx/xcku/read_dna_address.vhd"
 
 add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd"
 add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd"
diff --git a/combiner_cts/combiner.vhd b/combiner_cts/combiner.vhd
index ece1b95..d531d74 100644
--- a/combiner_cts/combiner.vhd
+++ b/combiner_cts/combiner.vhd
@@ -849,7 +849,7 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
      FEE_DATA_FINISHED_OUT  => cts_rdo_finished
      );   
 
-  cts_addon_triggers_in(1 downto 0) <= '0' & mbs_trigger when rising_edge(clk_sys);
+  --cts_addon_triggers_in(1 downto 0) <= '0' & mbs_trigger when rising_edge(clk_sys);
 
   buscts_tx.nack <= '0';
   buscts_tx.ack  <= '0';
@@ -861,14 +861,15 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
    THE_LOCAL_MBS_CREATE : process
      variable cnt : unsigned(16 downto 0) := (others => '0');
    begin
-     wait until rising_edge(clk_sys);
+--     wait until rising_edge(clk_sys);
+     wait until rising_edge(med2int(INTERFACE_NUM).clk_half);
      mbs_local_trigger_in <= '0';
      if (reset_i = '1') then
        cnt := 0;
        mbs_local_trigger_num_in <= (others => '0');
      else
        cnt := cnt + 1;
-       if (cnt = 100000) then
+       if (cnt = 10240) then
          mbs_local_trigger_in     <= '1';
          mbs_local_trigger_num_in <= std_logic_vector(unsigned(mbs_local_trigger_num_in) + 1);
          cnt := 0;
@@ -896,6 +897,9 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
   
   
    THE_MBS_REC : entity work.mbs_recv
+      generic map(
+        USE_40MHz => c_NO
+      )
       port map (
         CLK      => clk_sys,
         RESET_IN => reset_i,
@@ -1089,7 +1093,10 @@ THE_CRI_INTERFACE : entity work.trb_net16_cri_interface
 ---------------------------------------------------------------------------  
 
   --TRIGGER_TO_CTS <= trig_gen_out_i(1);
-  --RJ45_SIG_4     <= trig_gen_out_i(0);
+  RJ45_SIG_4     <= cts_trigger_out;--trig_gen_out_i(0);
+  RJ45_SIG_5     <= mbs_trigger;
+  TRIGGER_TO_CTS <= mbs_local_trigger_in;
+
   --TRIGGER_OUT    <= RJ45_SIG_1;
   --cts_ext_trigger <= TRIGGER_IN;      --  
   TRIGGER_OUT     <= cts_trigger_out; -- trigger from internal CTS to DiRICH/Power