From: local account Date: Mon, 18 Jan 2016 17:22:09 +0000 (+0100) Subject: Added internal delay via stretcher, new discharge generation X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6bde99d042ba2c4a44a9aeafedbdf965f70bc096;p=padiwa.git Added internal delay via stretcher, new discharge generation --- diff --git a/amps/compile_padiwa_amps_gsi.pl b/amps/compile_padiwa_amps_gsi.pl index 69d233b..67387f3 100755 --- a/amps/compile_padiwa_amps_gsi.pl +++ b/amps/compile_padiwa_amps_gsi.pl @@ -10,9 +10,9 @@ use FileHandle; ################################################################################### #Settings for this project my $TOPNAME = "padiwa_amps"; #Name of top-level entity -my $lattice_path = '/opt/lattice/diamond/2.2_x64'; +my $lattice_path = '/opt/lattice/diamond/3.6_x64'; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $synplify_path = '/opt/synplicity/K-2015.09'; my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de'; my $lm_license_file_for_par = '1702@hadeb05.gsi.de'; ################################################################################### diff --git a/amps/padiwa_amps.ldf b/amps/padiwa_amps.ldf index 754a5fd..f180a13 100644 --- a/amps/padiwa_amps.ldf +++ b/amps/padiwa_amps.ldf @@ -1,21 +1,18 @@ - + - + - - - - + @@ -24,30 +21,36 @@ - + + + + + + + - + - + - + - + - + - + - + - + diff --git a/amps/padiwa_amps.prj b/amps/padiwa_amps.prj index 39d2d51..12aa866 100644 --- a/amps/padiwa_amps.prj +++ b/amps/padiwa_amps.prj @@ -11,8 +11,8 @@ add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../source/spi_slave.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_sctrl.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_recv.vhd" +###add_file -vhdl -lib work "../../trbnet/special/uart_sctrl.vhd" +###add_file -vhdl -lib work "../../trbnet/special/uart_recv.vhd" add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../source/pwm.vhd" add_file -vhdl -lib work "../cores/pll_shifted_clocks.vhd" @@ -27,6 +27,9 @@ add_file -vhdl -lib work "../cores/pll.vhd" add_file -verilog -lib work "../cores/efb_define_def.v" add_file -verilog -lib work "../cores/UFM_WB.v" +add_file -vhdl -lib work "../source/Stretcher.vhd" +add_file -vhdl -lib work "../source/Stretcher_A.vhd" +add_file -vhdl -lib work "../source/Stretcher_B.vhd" add_file -vhdl -lib work "padiwa_amps.vhd" diff --git a/amps/padiwa_amps.vhd b/amps/padiwa_amps.vhd index 0f83dca..78613b7 100644 --- a/amps/padiwa_amps.vhd +++ b/amps/padiwa_amps.vhd @@ -155,7 +155,7 @@ end component; component PUR port(PUR : in std_logic); end component; component GSR port(GSR : in std_logic); end component; - +constant DELAYDEPTH : integer := 16; attribute NOM_FREQ : string; attribute NOM_FREQ of clk_source : label is "133.00"; @@ -211,7 +211,7 @@ signal flash_busy : std_logic; signal flash_err : std_logic; signal inp_select : integer range 0 to 31 := 0; -signal inp_invert : std_logic_vector(15 downto 0); +signal inp_invert : std_logic_vector(15 downto 0) := (others => '1'); signal input_enable : std_logic_vector(15 downto 0); signal inp_status : std_logic_vector(15 downto 0); signal led_status : std_logic_vector(8 downto 0) := "100000000"; @@ -266,7 +266,9 @@ signal comp_setting_s : std_logic_vector(15 downto 0); signal ffarr_data : std_logic_vector(15 downto 0); signal ffarr_read : std_logic; - +signal delayed_inputs : std_logic_vector(127 downto 0); +signal selected_delay : std_logic_vector(8 downto 1); +signal delayselect : integer range 0 to 15; begin @@ -541,6 +543,7 @@ THE_IO_REG_READ : process begin when x"8" => spi_reg20_i <= x"00" & discharge_override; when x"9" => spi_reg20_i <= x"00" & discharge_highz; when x"a" => spi_reg20_i <= x"00" & delay_invert; + when x"b" => spi_reg20_i <= x"00" & std_logic_vector(to_unsigned(delayselect,8)); when x"f" => spi_reg20_i <= ffarr_data; when others => null; end case; @@ -569,6 +572,7 @@ THE_IO_REG_WRITE : process begin when x"8" => discharge_override <= spi_data_i(7 downto 0); when x"9" => discharge_highz <= spi_data_i(7 downto 0); when x"a" => delay_invert <= spi_data_i(7 downto 0); + when x"b" => delayselect <= to_integer(unsigned(spi_data_i(7 downto 0))); when others => null; end case; end if; @@ -590,18 +594,50 @@ end generate; --------------------------------------------------------------------------- --- Delay generation +-- Stretcher --------------------------------------------------------------------------- +THE_STRETCHER : entity work.Stretcher + generic map( + CHANNEL => 8, + DEPTH => DELAYDEPTH + ) + port map( + PULSE_IN => fast_input, + PULSE_OUT => delayed_inputs + ); +--------------------------------------------------------------------------- +-- Delay generation +--------------------------------------------------------------------------- +--git delay +------------ +--gen_discharge : for i in 1 to 8 generate +--DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else +-- (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else +-- discharge_override(i) when discharge_disable(i) = '1'; +-- +--DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i); +--end generate; + +--delay intern: standard latch +------------------------- gen_discharge : for i in 1 to 8 generate -DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else - (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else - discharge_override(i) when discharge_disable(i) = '1'; - -DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i); +process (slow_input, selected_delay) +begin + if (slow_input(i)='0') then + DISCHARGE(i)<='0'; + elsif (selected_delay(i)='1') then + DISCHARGE(i)<='1'; + end if; +end process; + +-- delayed_inputs(i) <= selected_delay(i); +selected_delay(i) <= delayed_inputs(i*DELAYDEPTH-1-delayselect); end generate; - + + + fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0); slow_input <= inp_gated(15) & inp_gated(13) & inp_gated(11) & inp_gated(9) & inp_gated(7) & inp_gated(5) & inp_gated(3) & inp_gated(1); @@ -654,8 +690,11 @@ inp_long_reg <= inp_long_or when rising_edge(clk_i); last_inp_long_reg <= inp_long_reg when rising_edge(clk_i); -TEST_LINE <= (others => '0'); - +-- TEST_LINE <= (others => '0'); +--TEST_LINE(7 downto 0) <= delayed_inputs(7 downto 0); +--TEST_LINE(8) <= fast_input(1); +--TEST_LINE(13 downto 9) <= (others => '0'); +TEST_LINE(7 downto 0) <= selected_delay; gen_leds : for i in 1 to 8 generate LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else not led_status(i-1); diff --git a/pinout/padiwa_amps.lpf b/pinout/padiwa_amps.lpf index 3de9338..7dbbdd7 100644 --- a/pinout/padiwa_amps.lpf +++ b/pinout/padiwa_amps.lpf @@ -204,3 +204,16 @@ IOBUF GROUP "DELAY_C_OUT_group" IO_TYPE=LVCMOS33 DRIVE=4 PULLMODE=DOWN; DEFINE PORT GROUP "DELAY_C_IN_group" "DELAY_*_IN*" ; IOBUF GROUP "DELAY_C_IN_group" IO_TYPE=LVCMOS33 ; + +UGROUP "StretchA" BBOX 8 2 + BLKNAME THE_STRETCHER/Stretcher_A_1 + ; +LOCATE UGROUP "StretchA" SITE "R2C2D"; + +UGROUP "StretchB" BBOX 8 2 + BLKNAME THE_STRETCHER/Stretcher_B_1 + ; +LOCATE UGROUP "StretchB" SITE "R2C30D"; + + + \ No newline at end of file