From: Tobias Weber Date: Fri, 22 Jun 2018 09:51:52 +0000 (+0200) Subject: adjusting fifo input data with to 40 bit X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6beba96448f5b5831249125775643593b1d79560;p=trb3.git adjusting fifo input data with to 40 bit --- diff --git a/mupix/Mupix8/sources/DataMuxWithConversion.vhd b/mupix/Mupix8/sources/DataMuxWithConversion.vhd index 93cfe04..f8d7f6b 100644 --- a/mupix/Mupix8/sources/DataMuxWithConversion.vhd +++ b/mupix/Mupix8/sources/DataMuxWithConversion.vhd @@ -13,7 +13,7 @@ use ieee.numeric_std.all; use work.StdTypes.all; use work.Constants.all; -entity FiFoDataMux is +entity FiFoDataMuxWithConversion is generic( g_datawidthfifo : integer := 40; -- data width of input fifos g_datawidthtrb : integer := 32; -- data width of trb data bus @@ -33,10 +33,10 @@ entity FiFoDataMux is wordin_freq : out std_logic_vector(32*g_inputs - 1 downto 0); -- number of input words from FIFOs fifo_full_o : out std_logic -- or over input fifo full flags ); -end entity FiFoDataMux; +end entity FiFoDataMuxWithConversion; -architecture RTL of FiFoDataMux is +architecture RTL of FiFoDataMuxWithConversion is signal ticks_counter : unsigned(f_log2(g_clockspeed) - 1 downto 0) := (others => '0'); signal inword_counter : t_counter_array(0 to g_inputs - 1) := (others => (others => '0')); diff --git a/mupix/Mupix8/sources/FrameGenMux2.vhd b/mupix/Mupix8/sources/FrameGenMux2.vhd index d9f5d13..bbbcc4d 100644 --- a/mupix/Mupix8/sources/FrameGenMux2.vhd +++ b/mupix/Mupix8/sources/FrameGenMux2.vhd @@ -11,8 +11,6 @@ use IEEE.NUMERIC_STD.ALL; entity FrameGeneratorMux is generic( - fpga_clk_speed : integer := 1e8; - spi_clk_speed : integer := 1e4; FIFODEPTH : positive := 256; DATAWIDTH : natural := 32 ); diff --git a/mupix/Mupix8/sources/Generator3.vhd b/mupix/Mupix8/sources/Generator3.vhd index 8f3f5f2..9a3a7f0 100644 --- a/mupix/Mupix8/sources/Generator3.vhd +++ b/mupix/Mupix8/sources/Generator3.vhd @@ -121,8 +121,8 @@ begin end case; end if; writeEn <= writeEn_int; - data_out(iWIDTH - 1 downto iWIDTH - 16) <= std_logic_vector(num_ctr(15 downto 0)); - data_out(iWIDTH - 17 downto 16) <= (others => '0'); + data_out(iWIDTH - 1 downto 32) <= (others => '0'); + data_out(31 downto 16) <= std_logic_vector(num_ctr(15 downto 0)); data_out(15 downto 0) <= chan_sig(to_integer(unsigned(chan_sel))); end if; end process generator; diff --git a/mupix/Mupix8/sources/MupixBoard.vhd b/mupix/Mupix8/sources/MupixBoard.vhd index 5b13b01..1fa2ea1 100644 --- a/mupix/Mupix8/sources/MupixBoard.vhd +++ b/mupix/Mupix8/sources/MupixBoard.vhd @@ -12,6 +12,7 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.StdTypes.all; +use wirk.Constants.all; entity MupixBoard8 is port( @@ -199,7 +200,8 @@ architecture Behavioral of MupixBoard8 is generic( g_mupix_links : natural := 4; g_cyc_mem_address_width : integer := 13; - g_datawidth : integer := 32 + g_datawidthfifo : integer := 40; + g_datawidthtrb : integer := 32 ); port( clk : in std_logic; @@ -257,8 +259,6 @@ architecture Behavioral of MupixBoard8 is component FrameGeneratorMux generic( - fpga_clk_speed : integer; - spi_clk_speed : integer; FIFODEPTH : positive; DATAWIDTH : natural ); @@ -312,12 +312,11 @@ architecture Behavioral of MupixBoard8 is end component MupixDataLink; constant FIFO_DEPTH : positive := 256; --size of pseudo data generator fifos - constant DATA_WIDTH : natural := 32; --width of datawords - signal mux_fifo_data : std_logic_vector(127 downto 0); - signal mux_fifo_full : std_logic_vector(3 downto 0); - signal mux_fifo_empty : std_logic_vector(3 downto 0); - signal mux_fifo_rden : std_logic_vector(3 downto 0); + signal mux_fifo_data : std_logic_vector(c_mupixhitsize*c_links downto 0); + signal mux_fifo_full : std_logic_vector(c_links - 1 downto 0); + signal mux_fifo_empty : std_logic_vector(c_links - 1 downto 0); + signal mux_fifo_rden : std_logic_vector(c_links - 1 downto 0); --signal declarations -- Bus Handler @@ -338,10 +337,10 @@ architecture Behavioral of MupixBoard8 is signal mupixdata_i : std_logic_vector(31 downto 0); --connections between mupix data fifos and mupix board - signal fifo_rden_serdes_i : std_logic_vector(3 downto 0); - signal fifo_empty_serdes_i : std_logic_vector(3 downto 0); - signal fifo_full_serdes_i : std_logic_vector(3 downto 0); - signal fifo_data_serdes_i : std_logic_vector(127 downto 0); + signal fifo_rden_serdes_i : std_logic_vector(c_links - 1 downto 0); + signal fifo_empty_serdes_i : std_logic_vector(c_links - 1 downto 0); + signal fifo_full_serdes_i : std_logic_vector(c_links - 1 downto 0); + signal fifo_data_serdes_i : std_logic_vector(c_mupixhitsize*c_links downto 0); begin -- Behavioral @@ -404,7 +403,7 @@ begin -- Behavioral STAT_DEBUG => open ); - mupixboardinterface_1 : component MupixBoardInterface + mupixboardinterface_1 : entity work.MupixBoardInterface port map( clk_in => clk, fast_clk_in => fast_clk, @@ -427,7 +426,7 @@ begin -- Behavioral hit_sync => hit_sync ); - hitbushistogram_1 : component HitbusHistogram + hitbushistogram_1 : entity work.HitbusHistogram generic map( HistogramRange => 10, PostOscillationWaitCycles => 5 @@ -446,7 +445,7 @@ begin -- Behavioral SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(0) ); - pixelcontrol_1 : component PixelControl + pixelcontrol_1 : entity work.PixelControl generic map( fpga_clk_speed => fpga_clk_speed, spi_clk_speed => mupix_spi_clk_speed @@ -473,7 +472,7 @@ begin -- Behavioral ctrl_rb <= mupixslctrl_i.rb; - boardcontrol_1 : component MupixBoardDAC + boardcontrol_1 : entity work.MupixBoardDAC port map( clk => clk, reset => reset, @@ -521,7 +520,8 @@ begin -- Behavioral generic map( g_mupix_links => 4, g_cyc_mem_address_width => 12, - g_datawidth => 32 + g_datawidthfifo => c_mupixhitsize, + g_datawidthtrb => 32 ) port map( clk => clk, @@ -575,12 +575,10 @@ begin -- Behavioral SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(4) ); - hitgenerator_1: component FrameGeneratorMux + hitgenerator_1: entity work.FrameGeneratorMux generic map( - fpga_clk_speed => fpga_clk_speed, - spi_clk_speed => mupix_spi_clk_speed, FIFODEPTH => FIFO_DEPTH, - DATAWIDTH => DATA_WIDTH + DATAWIDTH => c_mupixhitsize ) port map( clk => clk, diff --git a/mupix/Mupix8/sources/MupixTRBReadout.vhd b/mupix/Mupix8/sources/MupixTRBReadout.vhd index dbf57f9..8c992e1 100644 --- a/mupix/Mupix8/sources/MupixTRBReadout.vhd +++ b/mupix/Mupix8/sources/MupixTRBReadout.vhd @@ -8,9 +8,10 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity MupixTRBReadout is - generic(g_mupix_links : natural := 4; -- number of input data channels from mupix + generic(g_mupix_links : natural := 4; -- number of input data channels from mupix g_cyc_mem_address_width : integer := 13; -- memory depth of circular buffer - g_datawidth : integer := 32 -- width of data words + g_datawidthfifo : integer := 40; -- width of data words from fifos + g_datawidthtrb : integer := 32 -- trb data width ); port( clk : in std_logic; -- clock input @@ -18,11 +19,11 @@ entity MupixTRBReadout is -- input fifo signals (maybe we need word width conversion somewhere ?) fifo_empty : in std_logic_vector(g_mupix_links - 1 downto 0); fifo_full : in std_logic_vector(g_mupix_links - 1 downto 0); - fifo_datain : in std_logic_vector(g_mupix_links*g_datawidth - 1 downto 0); + fifo_datain : in std_logic_vector(g_mupix_links*g_datawidthfifo - 1 downto 0); fifo_rden : out std_logic_vector(g_mupix_links - 1 downto 0); -- readout and trigger trb_trigger : in std_logic; -- signal from trb to start readout - dataout : out std_logic_vector(g_datawidth - 1 downto 0); -- data to TRB data channel + dataout : out std_logic_vector(g_datawidthtrb - 1 downto 0); -- data to TRB data channel data_valid : out std_logic; -- output data is valid busy : out std_logic; -- readout controller is busy -- TRB slow Control channel @@ -50,11 +51,11 @@ architecture rtl of MupixTRBReadout is clk : in std_logic; rst : in std_logic; wr_en : in std_logic; - data_in : in std_logic_vector(g_datawidth - 1 downto 0); + data_in : in std_logic_vector(g_datawidthtrb - 1 downto 0); rd_en : in std_logic; offset_en : in std_logic; offset : in std_logic_vector(g_addresswidth - 1 downto 0); - data_out : out std_logic_vector(g_datawidth - 1 downto 0); + data_out : out std_logic_vector(g_datawidthtrb - 1 downto 0); empty : out std_logic; full : out std_logic; almost_empty : out std_logic; @@ -65,9 +66,10 @@ architecture rtl of MupixTRBReadout is ); end component CircularMemory; - component FiFoDataMux + component FiFoDataMuxWithConversion generic( - g_datawidth : integer := 32; + g_datawidthfifo : integer := 40; + g_datawidthtrb : integer := 32; g_inputs : integer := 4; g_clockspeed : integer := 1e8 ); @@ -76,15 +78,15 @@ architecture rtl of MupixTRBReadout is rst : in std_logic; fifo_empty : in std_logic_vector(g_inputs - 1 downto 0); fifo_full : in std_logic_vector(g_inputs - 1 downto 0); - fifo_datain : in std_logic_vector(g_inputs*g_datawidth - 1 downto 0); + fifo_datain : in std_logic_vector(g_inputs*g_datawidthfifo - 1 downto 0); fifo_mask : in std_logic_vector(g_inputs - 1 downto 0); fifo_rden : out std_logic_vector(g_inputs - 1 downto 0); buff_wren : out std_logic; - dataout : out std_logic_vector(g_datawidth - 1 downto 0); + dataout : out std_logic_vector(g_datawidthtrb - 1 downto 0); wordin_freq : out std_logic_vector(32*g_inputs - 1 downto 0); fifo_full_o : out std_logic ); - end component FiFoDataMux; + end component FiFoDataMuxWithConversion; component ReadoutController generic( @@ -127,12 +129,12 @@ architecture rtl of MupixTRBReadout is signal cycl_almost_empty : std_logic; signal fifo_mux_wren : std_logic; - signal fifo_mux_data_out : std_logic_vector(g_datawidth - 1 downto 0); + signal fifo_mux_data_out : std_logic_vector(g_datawidthtrb - 1 downto 0); signal start_readout_slow_to_buffer : std_logic := '0'; signal start_readout : std_logic := '0'; - signal readout_controller_data_in : std_logic_vector(g_datawidth - 1 downto 0); - signal readout_controller_data_out : std_logic_vector(g_datawidth - 1 downto 0); + signal readout_controller_data_in : std_logic_vector(g_datawidthtrb - 1 downto 0); + signal readout_controller_data_out : std_logic_vector(g_datawidthtrb - 1 downto 0); signal readout_controller_busy : std_logic; signal readout_controller_offset_en : std_logic; signal readout_controller_rd_en : std_logic; @@ -140,7 +142,7 @@ architecture rtl of MupixTRBReadout is type slow_readout_fsm_type is (idle, waitstate); signal slow_readout_fsm : slow_readout_fsm_type := idle; - signal slow_data : std_logic_vector(g_datawidth - 1 downto 0) := (others => '0'); + signal slow_data : std_logic_vector(g_datawidthtrb - 1 downto 0) := (others => '0'); signal start_slow_read : std_logic := '0'; signal slow_read_busy : std_logic := '0'; signal slow_read_done : std_logic := '0'; @@ -149,9 +151,10 @@ begin start_readout <= start_readout_slow_to_buffer or trb_trigger; - data_mux_1 : entity work.FiFoDataMux + data_mux_1 : entity work.FiFoDataMuxWithConversion generic map( - g_datawidth => g_datawidth, + g_datawidthfifo => g_datawidthfifo, + g_datawidthtrb => g_datawidthtrb, g_inputs => g_mupix_links, g_clockspeed => 1e8 ) @@ -171,7 +174,7 @@ begin cycl_buffer_1 : entity work.CircularMemory generic map( - g_datawidth => g_datawidth, + g_datawidth => g_datawidthtrb, g_addresswidth => g_cyc_mem_address_width, g_clockspeed => 1e8, g_boundedbuf => false @@ -196,7 +199,7 @@ begin readout_controller_1 : entity work.ReadoutController generic map( - g_datawidth => g_datawidth, + g_datawidth => g_datawidthtrb, g_addresswidth => g_cyc_mem_address_width ) port map( diff --git a/mupix/Mupix8/sources/constants.vhd b/mupix/Mupix8/sources/constants.vhd index bead1ca..c29e9d0 100644 --- a/mupix/Mupix8/sources/constants.vhd +++ b/mupix/Mupix8/sources/constants.vhd @@ -4,8 +4,9 @@ use IEEE.numeric_std.all; package Constants is + constant c_links : integer := 4: -- number of links from mupix constant c_mupixhitsize : integer := 40; -- Link(8) & Row(8) & Col(8) & Charge(7) & TS(9) in hit mode - -- binary counter(24) & link(4) & x"3" & gray counter + -- binary counter(24) & link(4) & x"3" & gray counte constant k28_5 : std_logic_vector(7 downto 0) := x"bc"; constant k28_0 : std_logic_vector(7 downto 0) := x"1c";