From: Andreas Neiser Date: Thu, 12 Feb 2015 11:13:54 +0000 (+0100) Subject: Try with 64MHz X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6c0a0f5b936d61cb2d4e702867b98a5700e3c371;p=trb3.git Try with 64MHz --- diff --git a/ADC/config.vhd b/ADC/config.vhd index abb7dea..60a05c9 100644 --- a/ADC/config.vhd +++ b/ADC/config.vhd @@ -24,8 +24,8 @@ package config is constant INIT_ADDRESS : std_logic_vector := x"F30a"; constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"4b"; ---ADC sampling frequency: 40 or 65 MHz supported - constant ADC_SAMPLING_RATE : integer := 65; +--ADC sampling frequency: 40 or 64 MHz supported + constant ADC_SAMPLING_RATE : integer := 64; --These are currently used for the included features table only constant ADC_PROCESSING_TYPE : integer := 0; diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd index e79246f..a00f49d 100644 --- a/ADC/source/adc_ad9219.vhd +++ b/ADC/source/adc_ad9219.vhd @@ -31,8 +31,8 @@ architecture adc_ad9219_arch of adc_ad9219 is type q_t is array (0 to NUM_DEVICES - 1) of std_logic_vector(19 downto 0); signal q : q_t; - signal clk_adcfast_i : std_logic; --200MHz/325MHz - signal clk_adcdata : std_logic; --100MHz/162.5MHz + signal clk_adcfast_i : std_logic; --200MHz/320MHz + signal clk_adcdata : std_logic; --100MHz/160MHz signal restart_i : std_logic; begin @@ -51,14 +51,14 @@ begin ); end generate; - gen_65MHz : if ADC_SAMPLING_RATE = 65 generate - THE_ADC_REF : entity work.pll_in200_out65 + gen_64MHz : if ADC_SAMPLING_RATE = 64 generate + THE_ADC_REF : entity work.pll_in200_out64 port map( CLK => CLK_ADCRAW, CLKOP => ADCCLK_OUT, LOCK => open ); - THE_ADC_PLL_0 : entity work.pll_adc10bit_65 + THE_ADC_PLL_0 : entity work.pll_adc10bit_64 port map( CLK => CLK_ADCRAW, CLKOP => clk_adcfast_i, diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj index f2bc8b1..ff5d304 100644 --- a/ADC/trb3_periph_adc.prj +++ b/ADC/trb3_periph_adc.prj @@ -142,9 +142,9 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd" -add_file -vhdl -lib "work" "../base/cores/pll_in200_out65.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_in200_out64.vhd" add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd" -add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_65.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_adc10bit_64.vhd" add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd" add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd" add_file -vhdl -lib "work" "../base/cores/fifo_cdt_200_50.vhd" diff --git a/ADC/trb3_periph_adc.sdc b/ADC/trb3_periph_adc.sdc index 9ffbb0f..1115327 100644 --- a/ADC/trb3_periph_adc.sdc +++ b/ADC/trb3_periph_adc.sdc @@ -13,8 +13,8 @@ define_clock {CLK_PCLK_RIGHT} -name {CLK_PCLK_RIGHT} -freq 200 -clockgroup default_clkgroup_0 define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_1 define_clock {TRIGGER_LEFT} -name {TRIGGER_LEFT} -freq 10 -clockgroup default_clkgroup_2 -define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -freq 163 -clockgroup default_clkgroup_3 -define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -freq 163 -clockgroup default_clkgroup_4 +define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_LEFT.gen_7\.THE_7.sclk} -freq 160 -clockgroup default_clkgroup_3 +define_clock {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -name {n:gen_reallogic\.THE_ADC.THE_ADC_RIGHT.gen_5\.THE_5.sclk} -freq 160 -clockgroup default_clkgroup_4 define_clock {n:THE_MAIN_PLL.CLKOP} -name {n:THE_MAIN_PLL.CLKOP} -freq 100 -clockgroup default_clkgroup_5 define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.rx_half_clk_ch1} -freq 100 -clockgroup default_clkgroup_6 define_clock {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -name {n:THE_MEDIA_UPLINK.gen_serdes_1_200\.THE_SERDES.refclkdiv2_rx_ch1} -freq 100 -clockgroup default_clkgroup_7 diff --git a/base/cores/pll_adc10bit_64.ipx b/base/cores/pll_adc10bit_64.ipx new file mode 100644 index 0000000..d5bd241 --- /dev/null +++ b/base/cores/pll_adc10bit_64.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/pll_adc10bit_65.lpc b/base/cores/pll_adc10bit_64.lpc similarity index 86% rename from base/cores/pll_adc10bit_65.lpc rename to base/cores/pll_adc10bit_64.lpc index db62bad..4422850 100644 --- a/base/cores/pll_adc10bit_65.lpc +++ b/base/cores/pll_adc10bit_64.lpc @@ -13,11 +13,11 @@ CoreType=LPM CoreStatus=Demo CoreName=PLL CoreRevision=5.3 -ModuleName=pll_adc10bit_65 +ModuleName=pll_adc10bit_64 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/10/2015 -Time=14:29:38 +Date=02/12/2015 +Time=12:01:33 [Parameters] Verilog=0 @@ -30,16 +30,16 @@ IO=0 Type=ehxpllb mode=normal IFrq=200 -Div=8 +Div=5 ClkOPBp=0 Post=2 -U_OFrq=325 +U_OFrq=320 OP_Tol=0.0 -OFrq=325.000000 +OFrq=320.000000 DutyTrimP=Rising DelayMultP=0 fb_mode=Internal -Mult=13 +Mult=8 Phase=0.0 Duty=8 DelayMultS=0 @@ -57,7 +57,7 @@ ClkRst=0 PCDR=0 FINDELA=0 VcoRate= -Bandwidth=1.348655 +Bandwidth=2.191564 ;DelayControl=No EnCLKOS=0 ClkOSBp=0 diff --git a/base/cores/pll_adc10bit_65.vhd b/base/cores/pll_adc10bit_64.vhd similarity index 88% rename from base/cores/pll_adc10bit_65.vhd rename to base/cores/pll_adc10bit_64.vhd index 3d2b2ca..f58f5e1 100644 --- a/base/cores/pll_adc10bit_65.vhd +++ b/base/cores/pll_adc10bit_64.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.3 ---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit_65 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 325 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw -e +--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_adc10bit_64 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 320 -fclkop_tol 0.0 -fb_mode INTERNAL -noclkos -noclkok -norst -noclkok2 -bw -e --- Tue Feb 10 14:29:38 2015 +-- Thu Feb 12 12:01:33 2015 library IEEE; use IEEE.std_logic_1164.all; @@ -11,16 +11,16 @@ library ecp3; use ecp3.components.all; -- synopsys translate_on -entity pll_adc10bit_65 is +entity pll_adc10bit_64 is port ( CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); attribute dont_touch : boolean; - attribute dont_touch of pll_adc10bit_65 : entity is true; -end pll_adc10bit_65; + attribute dont_touch of pll_adc10bit_64 : entity is true; +end pll_adc10bit_64; -architecture Structure of pll_adc10bit_65 is +architecture Structure of pll_adc10bit_64 is -- internal signal declarations signal CLKOP_t: std_logic; @@ -54,7 +54,7 @@ architecture Structure of pll_adc10bit_65 is end component; attribute FREQUENCY_PIN_CLKOP : string; attribute FREQUENCY_PIN_CLKI : string; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "325.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "320.000000"; attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; attribute syn_keep : boolean; attribute syn_noprune : boolean; @@ -74,7 +74,7 @@ begin CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", - CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 13, CLKI_DIV=> 8, + CLKOK_DIV=> 2, CLKOP_DIV=> 2, CLKFB_DIV=> 8, CLKI_DIV=> 5, FIN=> "200.000000") port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, @@ -90,7 +90,7 @@ end Structure; -- synopsys translate_off library ecp3; -configuration Structure_CON of pll_adc10bit_65 is +configuration Structure_CON of pll_adc10bit_64 is for Structure for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; for all:VLO use entity ecp3.VLO(V); end for; diff --git a/base/cores/pll_adc10bit_65.ipx b/base/cores/pll_adc10bit_65.ipx deleted file mode 100644 index a895feb..0000000 --- a/base/cores/pll_adc10bit_65.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/base/cores/pll_in200_out64.ipx b/base/cores/pll_in200_out64.ipx new file mode 100644 index 0000000..2e556a9 --- /dev/null +++ b/base/cores/pll_in200_out64.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/base/cores/pll_in200_out65.lpc b/base/cores/pll_in200_out64.lpc similarity index 79% rename from base/cores/pll_in200_out65.lpc rename to base/cores/pll_in200_out64.lpc index 15c16bc..e9aa7b5 100644 --- a/base/cores/pll_in200_out65.lpc +++ b/base/cores/pll_in200_out64.lpc @@ -1,9 +1,9 @@ [Device] Family=latticeecp3 PartType=LFE3-150EA -PartName=LFE3-150EA-6FN1156C -SpeedGrade=6 -Package=FPBGA1156 +PartName=LFE3-150EA-8FN672C +SpeedGrade=8 +Package=FPBGA672 OperatingCondition=COM Status=P @@ -13,11 +13,11 @@ CoreType=LPM CoreStatus=Demo CoreName=PLL CoreRevision=5.3 -ModuleName=pll_in200_out65 +ModuleName=pll_in200_out64 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=02/10/2015 -Time=09:55:42 +Date=02/12/2015 +Time=12:06:16 [Parameters] Verilog=0 @@ -30,16 +30,16 @@ IO=0 Type=ehxpllb mode=normal IFrq=200 -Div=40 +Div=25 ClkOPBp=0 Post=8 -U_OFrq=65 +U_OFrq=64 OP_Tol=0.0 -OFrq=65.000000 +OFrq=64.000000 DutyTrimP=Rising DelayMultP=0 fb_mode=CLKOP -Mult=13 +Mult=8 Phase=0.0 Duty=8 DelayMultS=0 @@ -57,7 +57,7 @@ ClkRst=0 PCDR=0 FINDELA=0 VcoRate= -Bandwidth=1.053636 +Bandwidth=1.712159 ;DelayControl=No EnCLKOS=0 ClkOSBp=0 diff --git a/base/cores/pll_in200_out65.vhd b/base/cores/pll_in200_out64.vhd similarity index 88% rename from base/cores/pll_in200_out65.vhd rename to base/cores/pll_in200_out64.vhd index b22960c..ddac92f 100644 --- a/base/cores/pll_in200_out65.vhd +++ b/base/cores/pll_in200_out64.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.3 ---/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out65 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 65 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e +--/home/soft/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out64 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -fclkop 64 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw -e --- Tue Feb 10 09:55:42 2015 +-- Thu Feb 12 12:06:16 2015 library IEEE; use IEEE.std_logic_1164.all; @@ -11,16 +11,16 @@ library ecp3; use ecp3.components.all; -- synopsys translate_on -entity pll_in200_out65 is +entity pll_in200_out64 is port ( CLK: in std_logic; CLKOP: out std_logic; LOCK: out std_logic); attribute dont_touch : boolean; - attribute dont_touch of pll_in200_out65 : entity is true; -end pll_in200_out65; + attribute dont_touch of pll_in200_out64 : entity is true; +end pll_in200_out64; -architecture Structure of pll_in200_out65 is +architecture Structure of pll_in200_out64 is -- internal signal declarations signal CLKOP_t: std_logic; @@ -53,7 +53,7 @@ architecture Structure of pll_in200_out65 is end component; attribute FREQUENCY_PIN_CLKOP : string; attribute FREQUENCY_PIN_CLKI : string; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "65.000000"; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "64.000000"; attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; attribute syn_keep : boolean; attribute syn_noprune : boolean; @@ -73,7 +73,7 @@ begin CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", - CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 13, CLKI_DIV=> 40, + CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 8, CLKI_DIV=> 25, FIN=> "200.000000") port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, @@ -89,7 +89,7 @@ end Structure; -- synopsys translate_off library ecp3; -configuration Structure_CON of pll_in200_out65 is +configuration Structure_CON of pll_in200_out64 is for Structure for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; for all:VLO use entity ecp3.VLO(V); end for; diff --git a/base/cores/pll_in200_out65.ipx b/base/cores/pll_in200_out65.ipx deleted file mode 100644 index b804250..0000000 --- a/base/cores/pll_in200_out65.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - -