From: Ludwig Maier Date: Fri, 29 Nov 2013 11:35:22 +0000 (+0100) Subject: nxyter ADC Working, TS Working X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6c27e9969e6e75ce1551f37e6887575fe7b2613a;p=trb3.git nxyter ADC Working, TS Working --- diff --git a/nxyter/cores/fifo_adc_48to48_dc.ipx b/nxyter/cores/fifo_adc_48to48_dc.ipx index aef5a3b..41b81ed 100644 --- a/nxyter/cores/fifo_adc_48to48_dc.ipx +++ b/nxyter/cores/fifo_adc_48to48_dc.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/nxyter/cores/fifo_adc_48to48_dc.lpc b/nxyter/cores/fifo_adc_48to48_dc.lpc index b41f15b..bf0fa8a 100644 --- a/nxyter/cores/fifo_adc_48to48_dc.lpc +++ b/nxyter/cores/fifo_adc_48to48_dc.lpc @@ -16,8 +16,8 @@ CoreRevision=5.4 ModuleName=fifo_adc_48to48_dc SourceFormat=VHDL ParameterFileVersion=1.0 -Date=11/24/2013 -Time=18:14:05 +Date=11/26/2013 +Time=10:38:44 [Parameters] Verilog=0 @@ -33,7 +33,7 @@ Width=48 RDepth=4 RWidth=48 regout=1 -CtrlByRdEn=1 +CtrlByRdEn=0 EmpFlg=0 PeMode=Static - Dual Threshold PeAssert=10 diff --git a/nxyter/cores/fifo_adc_48to48_dc.vhd b/nxyter/cores/fifo_adc_48to48_dc.vhd index d6823b9..c4737e7 100644 --- a/nxyter/cores/fifo_adc_48to48_dc.vhd +++ b/nxyter/cores/fifo_adc_48to48_dc.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 48 -depth 4 -rdata_width 48 -regout -pe -1 -pf -1 -e +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4 -width 48 -depth 4 -rdata_width 48 -regout -no_enable -pe -1 -pf -1 -e --- Sun Nov 24 18:14:05 2013 +-- Tue Nov 26 10:38:44 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -40,54 +40,6 @@ architecture Structure of fifo_adc_48to48_dc is signal rptr_0: std_logic; signal rptr_1: std_logic; signal rptr_2: std_logic; - signal ffidata_0: std_logic; - signal ffidata_1: std_logic; - signal ffidata_2: std_logic; - signal ffidata_3: std_logic; - signal ffidata_4: std_logic; - signal ffidata_5: std_logic; - signal ffidata_6: std_logic; - signal ffidata_7: std_logic; - signal ffidata_8: std_logic; - signal ffidata_9: std_logic; - signal ffidata_10: std_logic; - signal ffidata_11: std_logic; - signal ffidata_12: std_logic; - signal ffidata_13: std_logic; - signal ffidata_14: std_logic; - signal ffidata_15: std_logic; - signal ffidata_16: std_logic; - signal ffidata_17: std_logic; - signal ffidata_18: std_logic; - signal ffidata_19: std_logic; - signal ffidata_20: std_logic; - signal ffidata_21: std_logic; - signal ffidata_22: std_logic; - signal ffidata_23: std_logic; - signal ffidata_24: std_logic; - signal ffidata_25: std_logic; - signal ffidata_26: std_logic; - signal ffidata_27: std_logic; - signal ffidata_28: std_logic; - signal ffidata_29: std_logic; - signal ffidata_30: std_logic; - signal ffidata_31: std_logic; - signal ffidata_32: std_logic; - signal ffidata_33: std_logic; - signal ffidata_34: std_logic; - signal ffidata_35: std_logic; - signal ffidata_36: std_logic; - signal ffidata_37: std_logic; - signal ffidata_38: std_logic; - signal ffidata_39: std_logic; - signal ffidata_40: std_logic; - signal ffidata_41: std_logic; - signal ffidata_42: std_logic; - signal ffidata_43: std_logic; - signal ffidata_44: std_logic; - signal ffidata_45: std_logic; - signal ffidata_46: std_logic; - signal ffidata_47: std_logic; signal w_gcount_0: std_logic; signal w_gcount_1: std_logic; signal w_gcount_2: std_logic; @@ -267,54 +219,6 @@ architecture Structure of fifo_adc_48to48_dc is attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_adc_48to48_dc.lpc"; attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; - attribute GSR of FF_79 : label is "ENABLED"; - attribute GSR of FF_78 : label is "ENABLED"; - attribute GSR of FF_77 : label is "ENABLED"; - attribute GSR of FF_76 : label is "ENABLED"; - attribute GSR of FF_75 : label is "ENABLED"; - attribute GSR of FF_74 : label is "ENABLED"; - attribute GSR of FF_73 : label is "ENABLED"; - attribute GSR of FF_72 : label is "ENABLED"; - attribute GSR of FF_71 : label is "ENABLED"; - attribute GSR of FF_70 : label is "ENABLED"; - attribute GSR of FF_69 : label is "ENABLED"; - attribute GSR of FF_68 : label is "ENABLED"; - attribute GSR of FF_67 : label is "ENABLED"; - attribute GSR of FF_66 : label is "ENABLED"; - attribute GSR of FF_65 : label is "ENABLED"; - attribute GSR of FF_64 : label is "ENABLED"; - attribute GSR of FF_63 : label is "ENABLED"; - attribute GSR of FF_62 : label is "ENABLED"; - attribute GSR of FF_61 : label is "ENABLED"; - attribute GSR of FF_60 : label is "ENABLED"; - attribute GSR of FF_59 : label is "ENABLED"; - attribute GSR of FF_58 : label is "ENABLED"; - attribute GSR of FF_57 : label is "ENABLED"; - attribute GSR of FF_56 : label is "ENABLED"; - attribute GSR of FF_55 : label is "ENABLED"; - attribute GSR of FF_54 : label is "ENABLED"; - attribute GSR of FF_53 : label is "ENABLED"; - attribute GSR of FF_52 : label is "ENABLED"; - attribute GSR of FF_51 : label is "ENABLED"; - attribute GSR of FF_50 : label is "ENABLED"; - attribute GSR of FF_49 : label is "ENABLED"; - attribute GSR of FF_48 : label is "ENABLED"; - attribute GSR of FF_47 : label is "ENABLED"; - attribute GSR of FF_46 : label is "ENABLED"; - attribute GSR of FF_45 : label is "ENABLED"; - attribute GSR of FF_44 : label is "ENABLED"; - attribute GSR of FF_43 : label is "ENABLED"; - attribute GSR of FF_42 : label is "ENABLED"; - attribute GSR of FF_41 : label is "ENABLED"; - attribute GSR of FF_40 : label is "ENABLED"; - attribute GSR of FF_39 : label is "ENABLED"; - attribute GSR of FF_38 : label is "ENABLED"; - attribute GSR of FF_37 : label is "ENABLED"; - attribute GSR of FF_36 : label is "ENABLED"; - attribute GSR of FF_35 : label is "ENABLED"; - attribute GSR of FF_34 : label is "ENABLED"; - attribute GSR of FF_33 : label is "ENABLED"; - attribute GSR of FF_32 : label is "ENABLED"; attribute GSR of FF_31 : label is "ENABLED"; attribute GSR of FF_30 : label is "ENABLED"; attribute GSR of FF_29 : label is "ENABLED"; @@ -421,8 +325,8 @@ begin AD0=>scuba_vlo, DO0=>full_cmp_clr); pdp_ram_0_0_1: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), @@ -443,25 +347,21 @@ begin ADR2=>scuba_vlo, ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, - ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>rden_i, - CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, - CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, - DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21, - DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24, - DO7=>ffidata_25, DO8=>ffidata_26, DO9=>ffidata_27, - DO10=>ffidata_28, DO11=>ffidata_29, DO12=>ffidata_30, - DO13=>ffidata_31, DO14=>ffidata_32, DO15=>ffidata_33, - DO16=>ffidata_34, DO17=>ffidata_35, DO18=>ffidata_0, - DO19=>ffidata_1, DO20=>ffidata_2, DO21=>ffidata_3, - DO22=>ffidata_4, DO23=>ffidata_5, DO24=>ffidata_6, - DO25=>ffidata_7, DO26=>ffidata_8, DO27=>ffidata_9, - DO28=>ffidata_10, DO29=>ffidata_11, DO30=>ffidata_12, - DO31=>ffidata_13, DO32=>ffidata_14, DO33=>ffidata_15, - DO34=>ffidata_16, DO35=>ffidata_17); + ADR12=>scuba_vlo, ADR13=>scuba_vlo, CER=>scuba_vhi, + CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>Q(18), DO1=>Q(19), + DO2=>Q(20), DO3=>Q(21), DO4=>Q(22), DO5=>Q(23), DO6=>Q(24), + DO7=>Q(25), DO8=>Q(26), DO9=>Q(27), DO10=>Q(28), DO11=>Q(29), + DO12=>Q(30), DO13=>Q(31), DO14=>Q(32), DO15=>Q(33), + DO16=>Q(34), DO17=>Q(35), DO18=>Q(0), DO19=>Q(1), DO20=>Q(2), + DO21=>Q(3), DO22=>Q(4), DO23=>Q(5), DO24=>Q(6), DO25=>Q(7), + DO26=>Q(8), DO27=>Q(9), DO28=>Q(10), DO29=>Q(11), + DO30=>Q(12), DO31=>Q(13), DO32=>Q(14), DO33=>Q(15), + DO34=>Q(16), DO35=>Q(17)); pdp_ram_0_1_0: PDPW16KC - generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", - REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + generic map (CSDECODE_R=> "0b001", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "OUTREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) port map (DI0=>Data(36), DI1=>Data(37), DI2=>Data(38), DI3=>Data(39), DI4=>Data(40), DI5=>Data(41), DI6=>Data(42), DI7=>Data(43), DI8=>Data(44), DI9=>Data(45), DI10=>Data(46), @@ -483,272 +383,89 @@ begin ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, ADR7=>scuba_vlo, ADR8=>scuba_vlo, ADR9=>scuba_vlo, ADR10=>scuba_vlo, ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, - CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CER=>scuba_vhi, CLKR=>RdClock, CSR0=>rden_i, CSR1=>scuba_vlo, CSR2=>scuba_vlo, RST=>Reset, DO0=>open, DO1=>open, DO2=>open, DO3=>open, DO4=>open, DO5=>open, DO6=>open, DO7=>open, DO8=>open, DO9=>open, DO10=>open, DO11=>open, DO12=>open, DO13=>open, DO14=>open, DO15=>open, DO16=>open, DO17=>open, - DO18=>ffidata_36, DO19=>ffidata_37, DO20=>ffidata_38, - DO21=>ffidata_39, DO22=>ffidata_40, DO23=>ffidata_41, - DO24=>ffidata_42, DO25=>ffidata_43, DO26=>ffidata_44, - DO27=>ffidata_45, DO28=>ffidata_46, DO29=>ffidata_47, + DO18=>Q(36), DO19=>Q(37), DO20=>Q(38), DO21=>Q(39), + DO22=>Q(40), DO23=>Q(41), DO24=>Q(42), DO25=>Q(43), + DO26=>Q(44), DO27=>Q(45), DO28=>Q(46), DO29=>Q(47), DO30=>open, DO31=>open, DO32=>open, DO33=>open, DO34=>open, DO35=>open); - FF_79: FD1P3BX + FF_31: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_78: FD1P3DX + FF_30: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_77: FD1P3DX + FF_29: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_76: FD1P3DX + FF_28: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_75: FD1P3DX + FF_27: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_74: FD1P3DX + FF_26: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_73: FD1P3DX + FF_25: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_72: FD1P3DX + FF_24: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_71: FD1P3DX + FF_23: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_70: FD1P3BX + FF_22: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_69: FD1P3DX + FF_21: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_68: FD1P3DX + FF_20: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_67: FD1P3DX + FF_19: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_66: FD1P3DX + FF_18: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_65: FD1P3DX + FF_17: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_64: FD1P3DX + FF_16: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_63: FD1P3DX + FF_15: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_62: FD1P3DX + FF_14: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_61: FD1P3DX - port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0)); - - FF_60: FD1P3DX - port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1)); - - FF_59: FD1P3DX - port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2)); - - FF_58: FD1P3DX - port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3)); - - FF_57: FD1P3DX - port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4)); - - FF_56: FD1P3DX - port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5)); - - FF_55: FD1P3DX - port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6)); - - FF_54: FD1P3DX - port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7)); - - FF_53: FD1P3DX - port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8)); - - FF_52: FD1P3DX - port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9)); - - FF_51: FD1P3DX - port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(10)); - - FF_50: FD1P3DX - port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(11)); - - FF_49: FD1P3DX - port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(12)); - - FF_48: FD1P3DX - port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(13)); - - FF_47: FD1P3DX - port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(14)); - - FF_46: FD1P3DX - port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(15)); - - FF_45: FD1P3DX - port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(16)); - - FF_44: FD1P3DX - port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(17)); - - FF_43: FD1P3DX - port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(18)); - - FF_42: FD1P3DX - port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(19)); - - FF_41: FD1P3DX - port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(20)); - - FF_40: FD1P3DX - port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(21)); - - FF_39: FD1P3DX - port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(22)); - - FF_38: FD1P3DX - port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(23)); - - FF_37: FD1P3DX - port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(24)); - - FF_36: FD1P3DX - port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(25)); - - FF_35: FD1P3DX - port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(26)); - - FF_34: FD1P3DX - port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(27)); - - FF_33: FD1P3DX - port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(28)); - - FF_32: FD1P3DX - port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(29)); - - FF_31: FD1P3DX - port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(30)); - - FF_30: FD1P3DX - port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(31)); - - FF_29: FD1P3DX - port map (D=>ffidata_32, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(32)); - - FF_28: FD1P3DX - port map (D=>ffidata_33, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(33)); - - FF_27: FD1P3DX - port map (D=>ffidata_34, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(34)); - - FF_26: FD1P3DX - port map (D=>ffidata_35, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(35)); - - FF_25: FD1P3DX - port map (D=>ffidata_36, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(36)); - - FF_24: FD1P3DX - port map (D=>ffidata_37, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(37)); - - FF_23: FD1P3DX - port map (D=>ffidata_38, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(38)); - - FF_22: FD1P3DX - port map (D=>ffidata_39, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(39)); - - FF_21: FD1P3DX - port map (D=>ffidata_40, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(40)); - - FF_20: FD1P3DX - port map (D=>ffidata_41, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(41)); - - FF_19: FD1P3DX - port map (D=>ffidata_42, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(42)); - - FF_18: FD1P3DX - port map (D=>ffidata_43, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(43)); - - FF_17: FD1P3DX - port map (D=>ffidata_44, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(44)); - - FF_16: FD1P3DX - port map (D=>ffidata_45, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(45)); - - FF_15: FD1P3DX - port map (D=>ffidata_46, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(46)); - - FF_14: FD1P3DX - port map (D=>ffidata_47, SP=>RdEn, CK=>RdClock, CD=>rRst, - Q=>Q(47)); - FF_13: FD1S3DX port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index b83ea7b..006606a 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -45,6 +45,8 @@ entity adc_ad9228 is ADC0_NOTLOCK_COUNTER : out unsigned(7 downto 0); ADC1_NOTLOCK_COUNTER : out unsigned(7 downto 0); + ERROR_ADC0_OUT : out std_logic; + ERROR_ADC1_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); end adc_ad9228; @@ -110,6 +112,10 @@ architecture Behavioral of adc_ad9228 is signal adc1_read_enable_tt : std_logic; signal adc1_fifo_reset : std_logic; + -- Error + signal error_adc0_o : std_logic; + signal error_adc1_o : std_logic; + -- Output signal adc0_data_valid_o : std_logic; signal adc0_data_f : adc_data_t; @@ -118,30 +124,34 @@ architecture Behavioral of adc_ad9228 is signal adc1_data_valid_o : std_logic; signal adc1_data_f : adc_data_t; signal adc1_data_o : adc_data_t; - + begin -- DEBUG DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= DDR_DATA_CLK; - DEBUG_OUT(2) <= adc0_bit_shift_change; - DEBUG_OUT(3) <= adc0_write_enable; - DEBUG_OUT(4) <= adc0_fifo_full; - DEBUG_OUT(5) <= adc0_fifo_empty; - DEBUG_OUT(6) <= adc0_frame_locked; - DEBUG_OUT(7) <= adc0_new_data_t; - DEBUG_OUT(8) <= adc0_read_enable; - DEBUG_OUT(9) <= adc0_read_enable_t; + --DEBUG_OUT(2) <= adc0_bit_shift_change; + --DEBUG_OUT(3) <= adc0_write_enable; + --DEBUG_OUT(4) <= adc0_fifo_full; + --DEBUG_OUT(5) <= adc0_fifo_empty; + --DEBUG_OUT(6) <= adc0_frame_locked; + --DEBUG_OUT(7) <= adc0_new_data_t; + --DEBUG_OUT(8) <= adc0_read_enable; + --DEBUG_OUT(9) <= adc0_read_enable_t; + --DEBUG_OUT(10) <= adc0_read_enable_tt; + --DEBUG_OUT(11) <= adc0_data_valid_o; + --DEBUG_OUT(15 downto 12) <= adc0_data_f(0)(3 downto 0); + + DEBUG_OUT(5 downto 2) <= adc0_data_t(0)(3 downto 0); + DEBUG_OUT(6) <= adc0_fifo_full; + DEBUG_OUT(7) <= adc0_write_enable; + DEBUG_OUT(8) <= adc0_fifo_empty; + DEBUG_OUT(9) <= adc0_read_enable; DEBUG_OUT(10) <= adc0_read_enable_tt; DEBUG_OUT(11) <= adc0_data_valid_o; DEBUG_OUT(15 downto 12) <= adc0_data_f(0)(3 downto 0); - reset_0 <= RESET_IN or RESTART_IN; - reset_1 <= RESET_IN or RESTART_IN; - clkdiv_reset <= RESET_IN; - ----------------------------------------------------------------------------- - adc_ddr_generic_1: adc_ddr_generic port map ( clk_0 => ADC0_DCLK_IN, @@ -168,6 +178,10 @@ begin q_1 => q_1 ); + reset_0 <= RESET_IN or RESTART_IN; + reset_1 <= RESET_IN or RESTART_IN; + clkdiv_reset <= RESET_IN; + ----------------------------------------------------------------------------- PROC_MERGE_DATA0: process(DDR_DATA_CLK) @@ -348,7 +362,7 @@ begin Data(47 downto 36) => adc0_data_t(3), WrClock => DDR_DATA_CLK, RdClock => CLK_IN, - WrEn => adc0_new_data_t, + WrEn => adc0_write_enable, RdEn => adc0_read_enable, Reset => RESET_IN, RPReset => adc0_fifo_reset, @@ -359,9 +373,10 @@ begin Empty => adc0_fifo_empty, Full => adc0_fifo_full ); - adc0_fifo_reset <= RESTART_IN; - adc0_write_enable <= adc0_new_data_t and not adc0_fifo_full; - adc0_read_enable <= not adc0_fifo_empty; + + adc0_fifo_reset <= RESET_IN or RESTART_IN; + adc0_write_enable <= adc0_new_data_t and not adc0_fifo_full; + adc0_read_enable <= not adc0_fifo_empty; PROC_ADC0_FIFO_READ: process(CLK_IN) begin @@ -411,10 +426,10 @@ begin Empty => adc1_fifo_empty, Full => adc1_fifo_full ); - adc1_fifo_reset <= RESTART_IN; - adc1_write_enable <= adc1_new_data_t and not adc1_fifo_full; - adc1_read_enable <= not adc1_fifo_empty; - + adc1_fifo_reset <= RESET_IN or RESTART_IN; + adc1_write_enable <= adc1_new_data_t and not adc1_fifo_full; + adc1_read_enable <= not adc1_fifo_empty; + PROC_ADC1_FIFO_READ: process(CLK_IN) begin if (rising_edge(CLK_IN)) then @@ -505,7 +520,30 @@ begin end if; end if; end process PROC_NOTLOCK_COUNTER; - + + PROC_ERROR: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + error_adc0_o <= '0'; + error_adc1_o <= '0'; + else + error_adc0_o <= '0'; + error_adc1_o <= '0'; + + if (adc0_frame_notlocked = '1' or + adc0_bit_shift_change = '1') then + error_adc0_o <= '1'; + end if; + + if (adc1_frame_notlocked = '1' or + adc1_bit_shift_change = '1') then + error_adc0_o <= '1'; + end if; + end if; + end if; + end process PROC_ERROR; + -- Output ADC0_SCLK_OUT <= ADC0_SCLK_IN; @@ -526,4 +564,7 @@ begin ADC0_NOTLOCK_COUNTER <= adc0_notlock_ctr; ADC1_NOTLOCK_COUNTER <= adc1_notlock_ctr; + ERROR_ADC0_OUT <= error_adc0_o; + ERROR_ADC1_OUT <= error_adc1_o; + end architecture; diff --git a/nxyter/source/nx_control.vhd b/nxyter/source/nx_control.vhd index 068bcb0..658c931 100644 --- a/nxyter/source/nx_control.vhd +++ b/nxyter/source/nx_control.vhd @@ -21,7 +21,10 @@ entity nx_control is NX_TS_RESET_OUT : out std_logic; I2C_ONLINE_IN : in std_logic; OFFLINE_OUT : out std_logic; - + + -- Error + ERROR_ALL_IN : in std_logic_vector(7 downto 0); + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -422,6 +425,11 @@ begin slv_data_out_o(15 downto 0) <= pll_adc_sclk_notlock_ctr; slv_data_out_o(31 downto 6) <= (others => '0'); slv_ack_o <= '1'; + + when x"000c" => + slv_data_out_o(7 downto 0) <= ERROR_ALL_IN; + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 569151d..a3a79f4 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -46,6 +46,7 @@ entity nx_data_receiver is SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); end entity; @@ -62,12 +63,13 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- FIFO DC Input Handler + signal nx_fifo_write_enable : std_logic; signal nx_timestamp_fff : std_logic_vector(7 downto 0); signal nx_timestamp_ff : std_logic_vector(7 downto 0); signal nx_fifo_full : std_logic; signal nx_fifo_delay : unsigned(3 downto 0); signal nx_fifo_reset : std_logic; - + -- NX_TIMESTAMP_IN Process signal frame_byte_ctr : unsigned(1 downto 0); signal nx_frame_word : std_logic_vector(31 downto 0); @@ -84,10 +86,6 @@ architecture Behavioral of nx_data_receiver is -- Parity Check signal parity_error : std_logic; - -- Write to FIFO Handler - signal nx_fifo_data_input : std_logic_vector(31 downto 0); - signal nx_fifo_write_enable : std_logic; - -- NX Clock Active signal nx_clk_active_ff_0 : std_logic; signal nx_clk_active_ff_1 : std_logic; @@ -107,6 +105,7 @@ architecture Behavioral of nx_data_receiver is -- PLL ADC Monitor signal pll_adc_not_lock : std_logic; + signal pll_adc_not_lock_f : std_logic_vector(1 downto 0); signal pll_adc_not_lock_ctr : unsigned(11 downto 0); signal pll_adc_not_lock_ctr_clear : std_logic; @@ -184,11 +183,6 @@ architecture Behavioral of nx_data_receiver is signal adc_notlock_ctr : unsigned(7 downto 0); signal ADC_DEBUG : std_logic_vector(15 downto 0); - -- ADC TEST INPUT DATA - signal adc_input_error_enable : std_logic; - signal adc_input_error_ctr : unsigned(15 downto 0); - - -- Data Output Handler type STATES is (IDLE, WAIT_ADC, @@ -217,6 +211,11 @@ architecture Behavioral of nx_data_receiver is signal adc_frame_rate_ctr : unsigned(27 downto 0); signal adc_frame_rate : unsigned(27 downto 0); signal rate_timer_ctr : unsigned(27 downto 0); + + -- Error + signal error_adc0 : std_logic; + signal error_adc1 : std_logic; + signal error_o : std_logic; -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -227,7 +226,7 @@ architecture Behavioral of nx_data_receiver is signal reset_resync_ctr : std_logic; signal reset_parity_error_ctr : std_logic; signal fifo_reset_r : std_logic; - signal debug_adc : std_logic_vector(1 downto 0); + signal debug_adc : std_logic_vector(2 downto 0); signal reset_adc_handler_r : std_logic; signal reset_handler_counter_clear : std_logic; signal adc_bit_shift : unsigned(3 downto 0); @@ -261,17 +260,24 @@ begin ) begin case debug_adc is - when "01" => - DEBUG_OUT <= ADC_DEBUG; + when "001" => + DEBUG_OUT <= ADC_DEBUG; - when "10" => + when "010" => DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= nx_new_frame; DEBUG_OUT(2) <= TRIGGER_IN; DEBUG_OUT(3) <= adc_data_valid; DEBUG_OUT(15 downto 4) <= adc_data; - when "11" => + when "100" => + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= nx_new_frame; + DEBUG_OUT(2) <= TRIGGER_IN; + DEBUG_OUT(3) <= adc_data_valid; + DEBUG_OUT(15 downto 4) <= test_adc_data; + + when "011" => DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= reset_adc_handler; DEBUG_OUT(2) <= TRIGGER_IN; @@ -368,21 +374,25 @@ begin LOCK => pll_adc_sampling_clk_lock ); - signal_async_to_pulse_1: signal_async_to_pulse + signal_async_trans_2: signal_async_trans port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - PULSE_A_IN => not pll_adc_sampling_clk_lock, - PULSE_OUT => pll_adc_not_lock + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + SIGNAL_A_IN => not pll_adc_sampling_clk_lock, + SIGNAL_OUT => pll_adc_not_lock ); PROC_PLL_LOCK_COUNTER: process(CLK_IN) begin if (rising_edge(CLK_IN) ) then if( RESET_IN = '1' or pll_adc_not_lock_ctr_clear = '1') then + pll_adc_not_lock_f <= (others => '0'); pll_adc_not_lock_ctr <= (others => '0'); else - if (pll_adc_not_lock = '1') then + pll_adc_not_lock_f(0) <= pll_adc_not_lock; + pll_adc_not_lock_f(1) <= pll_adc_not_lock_f(0); + + if (pll_adc_not_lock_f = "01") then pll_adc_not_lock_ctr <= pll_adc_not_lock_ctr + 1; end if; end if; @@ -430,7 +440,9 @@ begin ADC0_NOTLOCK_COUNTER => adc_notlock_ctr, ADC1_NOTLOCK_COUNTER => open, - + + ERROR_ADC0_OUT => error_adc0, + ERROR_ADC1_OUT => error_adc1, DEBUG_OUT => ADC_DEBUG ); @@ -683,29 +695,9 @@ begin end if; end process PROC_PARITY_CHECK; - -- Write to FIFO - PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) - begin - if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then - if (RESET_IN = '1') then - nx_fifo_data_input <= (others => '0'); - nx_fifo_write_enable <= '0'; - else - nx_fifo_data_input <= x"deadbeef"; - nx_fifo_write_enable <= '0'; - if (nx_new_frame = '1' and - nx_frame_synced = '1' and - nx_fifo_full = '0') then - nx_fifo_data_input <= nx_frame_word; - nx_fifo_write_enable <= '1'; - end if; - end if; - end if; - end process PROC_WRITE_TO_FIFO; - fifo_ts_32to32_dc_1: fifo_ts_32to32_dc port map ( - Data => nx_fifo_data_input, + Data => nx_frame_word, WrClock => NX_TIMESTAMP_CLK_IN, RdClock => CLK_IN, WrEn => nx_fifo_write_enable, @@ -716,9 +708,10 @@ begin Empty => nx_fifo_empty, Full => nx_fifo_full ); - - nx_fifo_reset <= RESET_IN or data_handler_reset or fifo_reset_r; - + + nx_fifo_reset <= RESET_IN or data_handler_reset or fifo_reset_r; + nx_fifo_write_enable <= nx_new_frame and not nx_fifo_full; + PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then @@ -870,7 +863,6 @@ begin end if; end process PROC_NX_FIFO_DELAY; - ----------------------------------------------------------------------------- -- Status Counters ----------------------------------------------------------------------------- @@ -969,25 +961,6 @@ begin end if; end process PROC_ADC_DATA_READ; - PROC_ADC_TEST_INPUT_DATA: process(CLK_IN) - begin - if (rising_edge(CLK_IN) ) then - if (RESET_IN = '1') then - adc_input_error_ctr <= (others => '0'); - else - if (adc_input_error_enable = '1') then - if (adc_new_data = '1' and - adc_data_t /= x"fff" and - adc_data_t /= x"000") then - adc_input_error_ctr <= adc_input_error_ctr + 1; - end if; - else - adc_input_error_ctr <= (others => '0'); - end if; - end if; - end if; - end process PROC_ADC_TEST_INPUT_DATA; - ----------------------------------------------------------------------------- -- Output handler ----------------------------------------------------------------------------- @@ -1114,12 +1087,11 @@ begin reset_parity_error_ctr <= '0'; fifo_reset_r <= '0'; debug_adc <= (others => '0'); - adc_input_error_enable <= '0'; johnson_counter_sync_r <= "00"; pll_adc_sample_clk_dphase_r <= x"0"; pll_adc_sample_clk_finedelb <= (others => '0'); pll_adc_not_lock_ctr_clear <= '0'; - nx_fifo_delay <= x"8"; + nx_fifo_delay <= x"7"; reset_adc_handler_r <= '0'; reset_handler_counter_clear <= '0'; adc_bit_shift <= x"0"; @@ -1193,15 +1165,13 @@ begin slv_ack_o <= '1'; when x"0009" => - slv_data_out_o(0) <= adc_input_error_enable; - slv_data_out_o(31 downto 1) <= (others => '0'); + slv_data_out_o(31 downto 0) <= (others => '0'); slv_ack_o <= '1'; - + when x"000a" => - slv_data_out_o(15 downto 0) <= adc_input_error_ctr; - slv_data_out_o(31 downto 16) <= (others => '0'); + slv_data_out_o(31 downto 0) <= (others => '0'); slv_ack_o <= '1'; - + when x"000b" => slv_data_out_o(0) <= adc_clk_ok; slv_data_out_o(31 downto 1) <= (others => '0'); @@ -1237,12 +1207,17 @@ begin slv_data_out_o(27 downto 0) <= std_logic_vector(adc_frame_rate); slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; - + when x"0012" => - slv_data_out_o(1 downto 0) <= debug_adc; - slv_data_out_o(31 downto 2) <= (others => '0'); + slv_data_out_o(11 downto 0) <= test_adc_data; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0013" => + slv_data_out_o(2 downto 0) <= debug_adc; + slv_data_out_o(31 downto 3) <= (others => '0'); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; end case; @@ -1277,10 +1252,6 @@ begin reset_adc_handler_r <= '1'; slv_ack_o <= '1'; - when x"0009" => - adc_input_error_enable <= SLV_DATA_IN(0); - slv_ack_o <= '1'; - when x"000b" => reset_adc_handler_r <= '1'; slv_ack_o <= '1'; @@ -1299,8 +1270,8 @@ begin unsigned(SLV_DATA_IN(3 downto 0)); slv_ack_o <= '1'; - when x"0012" => - debug_adc <= SLV_DATA_IN(1 downto 0); + when x"0013" => + debug_adc <= SLV_DATA_IN(2 downto 0); slv_ack_o <= '1'; when others => @@ -1312,13 +1283,38 @@ begin end if; end process PROC_FIFO_REGISTERS; + -- ErrorPROC_ERROR: process(CLK_IN) + PROC_ERROR: process(CLK_IN) + begin + if (rising_edge(CLK_IN)) then + if (RESET_IN = '1') then + error_o <= '0'; + else + if (error_adc0 = '1' or + pll_adc_not_lock = '1' or + (nx_frame_rate < x"1dc_d642" or + nx_frame_rate > x"1dc_d652") or + (adc_frame_rate < x"1dc_d64e" or + adc_frame_rate > x"1dc_d652") or + adc_clk_ok = '0' or + parity_error_ctr_inc = '1' or + reg_nx_frame_synced = '0') then + error_o <= '1'; + else + error_o <= '0'; + end if; + end if; + end if; + end process PROC_ERROR; + -- Output Signals NX_TIMESTAMP_OUT <= nx_timestamp_o; ADC_DATA_OUT <= adc_data_o; NEW_DATA_OUT <= new_data_o; ADC_SCLK_LOCK_OUT <= pll_adc_sampling_clk_lock; - + ERROR_OUT <= error_o; + SLV_DATA_OUT <= slv_data_out_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index 9f33f97..41c46a5 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -78,6 +78,14 @@ architecture Behavioral of nx_data_validate is signal nx_frame_ctr_t : unsigned(27 downto 0); signal nx_rate_timer : unsigned(27 downto 0); + -- ADC Averages + signal adc_average_divisor : unsigned(3 downto 0); + signal adc_average_ctr : unsigned(8 downto 0); + signal adc_average_sum : unsigned(24 downto 0); + signal adc_average : unsigned(11 downto 0); + signal adc_data_last : std_logic_vector(11 downto 0); + signal adc_av : std_logic; + -- Config signal readout_type : std_logic_vector(1 downto 0); @@ -315,6 +323,35 @@ begin end if; end process PROC_CAL_RATES; + PROC_ADC_AVERAGE: process(CLK_IN) + begin + if (rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + adc_average_ctr <= (others => '0'); + adc_average_sum <= (others => '0'); + adc_average <= (others => '0'); + adc_data_last <= (others => '0'); + adc_av <= '0'; + else + adc_av <= '0'; + if ((adc_average_ctr srl to_integer(adc_average_divisor)) > 0) then + adc_average <= (adc_average_sum srl + to_integer(adc_average_divisor))(11 downto 0); + adc_average_sum <= (others => '0'); + adc_average_ctr <= (others => '0'); + adc_av <= '1'; + elsif (data_valid_o = '1') then + adc_average_sum <= adc_average_sum + unsigned(adc_data_o); + adc_average_ctr <= adc_average_ctr + 1; + end if; + + if (data_valid_o = '1') then + adc_data_last <= adc_data_o; + end if; + end if; + end if; + end process PROC_ADC_AVERAGE; + ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- @@ -329,6 +366,7 @@ begin slv_unknown_addr_o <= '0'; slv_no_more_data_o <= '0'; clear_counters <= '0'; + adc_average_divisor <= x"3"; else slv_data_out_o <= (others => '0'); slv_unknown_addr_o <= '0'; @@ -373,6 +411,22 @@ begin std_logic_vector(nx_frame_rate); slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; + + when x"0006" => + slv_data_out_o(11 downto 0) <= adc_data_last; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0007" => + slv_data_out_o(11 downto 0) <= std_logic_vector(adc_average); + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0008" => + slv_data_out_o(3 downto 0) <= + std_logic_vector(adc_average_divisor); + slv_data_out_o(31 downto 4) <= (others => '0'); + slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; @@ -384,6 +438,10 @@ begin when x"0000" => clear_counters <= '1'; slv_ack_o <= '1'; + + when x"0008" => + adc_average_divisor <= SLV_DATA_IN(3 downto 0); + slv_ack_o <= '1'; when others => slv_unknown_addr_o <= '1'; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 3984f2f..f7b3edc 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -250,6 +250,9 @@ component adc_ad9228 ADC0_NOTLOCK_COUNTER : out unsigned(7 downto 0); ADC1_NOTLOCK_COUNTER : out unsigned(7 downto 0); + + ERROR_ADC0_OUT : out std_logic; + ERROR_ADC1_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -321,13 +324,13 @@ component nx_control RESET_IN : in std_logic; PLL_NX_CLK_LOCK_IN : in std_logic; PLL_ADC_DCLK_LOCK_IN : in std_logic; - PLL_ADC_SCLK_LOCK_IN : in std_logic; + PLL_ADC_SCLK_LOCK_IN : in std_logic; I2C_SM_RESET_OUT : out std_logic; I2C_REG_RESET_OUT : out std_logic; NX_TS_RESET_OUT : out std_logic; I2C_ONLINE_IN : in std_logic; OFFLINE_OUT : out std_logic; - + ERROR_ALL_IN : in std_logic_vector(7 downto 0); SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -422,6 +425,7 @@ component nx_data_receiver SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index fc96bfb..0bbe92e 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -195,10 +195,14 @@ architecture Behavioral of nXyter_FEE_board is signal nx_timestamp_sync : std_logic; signal nx_timestamp_trigger_o : std_logic; - -- Trigger Generatorg + -- Trigger Generator signal trigger_intern : std_logic; signal nx_testpulse_o : std_logic; + -- Error + signal error_all : std_logic_vector(7 downto 0); + signal error_data_receiver : std_logic; + -- Debug Handler constant DEBUG_NUM_PORTS : integer := 13; signal debug_line : debug_array_t(0 to DEBUG_NUM_PORTS-1); @@ -211,6 +215,12 @@ begin -- DEBUG_LINE_OUT(0) <= CLK_IN; -- DEBUG_LINE_OUT(15 downto 0) <= (others => '0'); -- See Multiplexer + +------------------------------------------------------------------------------- +-- Errors +------------------------------------------------------------------------------- + error_all(0) <= error_data_receiver; + error_all(7 downto 1) <= (others => '0'); ------------------------------------------------------------------------------- -- Port Maps @@ -304,6 +314,8 @@ begin I2C_ONLINE_IN => nxyter_online_i2c, OFFLINE_OUT => nxyter_offline, + ERROR_ALL_IN => error_all, + SLV_READ_IN => slv_read(0), SLV_WRITE_IN => slv_write(0), SLV_DATA_OUT => slv_data_rd(0*32+31 downto 0*32), @@ -540,7 +552,7 @@ begin SLV_ACK_OUT => slv_ack(2), SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), - + ERROR_OUT => error_data_receiver, DEBUG_OUT => debug_line(7) );