From: Cahit <c.ugur@gsi.de>
Date: Tue, 22 Apr 2014 13:28:38 +0000 (+0200)
Subject: correct clock names for the multicycle constraint
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6c836f98d7c01bd057839b8e6ba578c86fcee7d9;p=trb3.git

correct clock names for the multicycle constraint
---

diff --git a/base/trb3_periph_32PinAddOn.lpf b/base/trb3_periph_32PinAddOn.lpf
index 0432b4e..c208a01 100644
--- a/base/trb3_periph_32PinAddOn.lpf
+++ b/base/trb3_periph_32PinAddOn.lpf
@@ -14,8 +14,8 @@ FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
 FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
 FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
 
-MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ;
-MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ;
+MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ;
+MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_i_c" 2 X ;
 
 LOCATE COMP   "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ;