From: hadaq Date: Sat, 20 Oct 2012 10:07:26 +0000 (+0000) Subject: Hit Counter Registers are added - cu X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6cc383c18caa525ef83424c2e574aca5e2c7c1a3;p=trb3.git Hit Counter Registers are added - cu --- diff --git a/tdc_releases/tdc_v0.5/BusHandler.vhd b/tdc_releases/tdc_v0.5/BusHandler.vhd new file mode 100644 index 0000000..abf6df5 --- /dev/null +++ b/tdc_releases/tdc_v0.5/BusHandler.vhd @@ -0,0 +1,92 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + +entity BusHandler is + generic ( + CHANNEL_NUMBER : integer range 0 to 64 := 2); + port ( + RESET : in std_logic; + CLK : in std_logic; +-- + DATA_IN : in std_logic_vector_array_32(0 to CHANNEL_NUMBER); + READ_EN_IN : in std_logic; + WRITE_EN_IN : in std_logic; + ADDR_IN : in std_logic_vector(6 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATAREADY_OUT : out std_logic; + UNKNOWN_ADDR_OUT : out std_logic); +end BusHandler; + +architecture Behavioral of BusHandler is + + --Output signals + signal data_out_reg : std_logic_vector(31 downto 0); + signal data_ready_reg : std_logic; + signal unknown_addr_reg : std_logic; + + --FSM signals + type FSM is (IDLE, READ_A, WRITE_A); + signal FSM_CURRENT, FSM_NEXT : FSM; + signal fsm_data_out : std_logic_vector(31 downto 0); + signal fsm_data_ready : std_logic; + signal fsm_unknown_addr : std_logic; + +begin + + READ_WRITE_RESPONSE : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '0'; + elsif READ_EN_IN = '1' then + if to_integer(unsigned(ADDR_IN)) > CHANNEL_NUMBER then -- if bigger than 64 + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '1'; + else + data_out_reg <= DATA_IN(to_integer(unsigned(ADDR_IN))); + data_ready_reg <= '1'; + unknown_addr_reg <= '0'; + end if; + elsif WRITE_EN_IN = '1' then + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '1'; + else + data_out_reg <= (others => '0'); + data_ready_reg <= '0'; + unknown_addr_reg <= '0'; + end if; + end if; + end process READ_WRITE_RESPONSE; + + + --FifoWriteSignal : process (CLK) + --begin + -- if rising_edge(CLK) then + -- if RESET = '1' then + -- unknown_addr_reg <= '0'; + -- else + -- unknown_addr_reg <= '1'; + -- end if; + -- end if; + --end process FifoWriteSignal; + + + + + DATA_OUT <= data_out_reg; + DATAREADY_OUT <= data_ready_reg; + UNKNOWN_ADDR_OUT <= unknown_addr_reg; + +end Behavioral; + diff --git a/tdc_releases/tdc_v0.5/Reference_channel.vhd b/tdc_releases/tdc_v0.5/Reference_channel.vhd index 7a5cb3e..b5c2074 100644 --- a/tdc_releases/tdc_v0.5/Reference_channel.vhd +++ b/tdc_releases/tdc_v0.5/Reference_channel.vhd @@ -15,23 +15,23 @@ entity Reference_Channel is generic ( CHANNEL_ID : integer range 0 to 0); port ( - RESET_200 : in std_logic; - RESET_100 : in std_logic; - CLK_200 : in std_logic; - CLK_100 : in std_logic; + RESET_200 : in std_logic; + RESET_100 : in std_logic; + CLK_200 : in std_logic; + CLK_100 : in std_logic; -- - HIT_IN : in std_logic; - READ_EN_IN : in std_logic; - VALID_TMG_TRG_IN : in std_logic; - SPIKE_DETECTED_IN : in std_logic; - MULTI_TMG_TRG_IN : in std_logic; - FIFO_DATA_OUT : out std_logic_vector(31 downto 0); - FIFO_EMPTY_OUT : out std_logic; - FIFO_FULL_OUT : out std_logic; - FIFO_ALMOST_FULL_OUT : out std_logic; - COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); - TRIGGER_TIME_OUT : out std_logic_vector(10 downto 0); -- coarse time of the timing trigger - REF_DEBUG_OUT : out std_logic_vector(31 downto 0) + HIT_IN : in std_logic; + READ_EN_IN : in std_logic; + VALID_TMG_TRG_IN : in std_logic; + SPIKE_DETECTED_IN : in std_logic; + MULTI_TMG_TRG_IN : in std_logic; + FIFO_DATA_OUT : out std_logic_vector(31 downto 0); + FIFO_EMPTY_OUT : out std_logic; + FIFO_FULL_OUT : out std_logic; + FIFO_ALMOST_FULL_OUT : out std_logic; + COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); + TRIGGER_TIME_STAMP_OUT : out std_logic_vector(10 downto 0); -- coarse time of the timing trigger + REF_DEBUG_OUT : out std_logic_vector(31 downto 0) ); end Reference_Channel; @@ -133,9 +133,9 @@ begin end if; end if; end process Start_Encoder; - encoder_start_i <= hit_detect_reg; - hit_time_stamp_reg <= hit_time_stamp_i when rising_edge(CLK_200); - TRIGGER_TIME_OUT <= hit_time_stamp_reg; -- coarse time of the timing trigger + encoder_start_i <= hit_detect_reg; + hit_time_stamp_reg <= hit_time_stamp_i when rising_edge(CLK_200); + TRIGGER_TIME_STAMP_OUT <= hit_time_stamp_reg; -- coarse time of the timing trigger --purpose: Encoder Encoder : Encoder_304_Bit diff --git a/tdc_releases/tdc_v0.5/TDC.vhd b/tdc_releases/tdc_v0.5/TDC.vhd index 9461dea..e98de1f 100644 --- a/tdc_releases/tdc_v0.5/TDC.vhd +++ b/tdc_releases/tdc_v0.5/TDC.vhd @@ -12,11 +12,6 @@ use work.trb_net_components.all; use work.trb3_components.all; use work.version.all; --- synopsys translate_off --- library ecp2m; --- use ecp2m.components.all; --- synopsys translate_on - entity TDC is generic ( CHANNEL_NUMBER : integer range 2 to 65; @@ -52,6 +47,14 @@ entity TDC is DATA_OUT : out std_logic_vector(31 downto 0); DATA_WRITE_OUT : out std_logic; DATA_FINISHED_OUT : out std_logic; +-- + --ToBusHandler + HCB_READ_EN_IN : in std_logic; + HCB_WRITE_EN_IN : in std_logic; + HCB_ADDR_IN : in std_logic_vector(6 downto 0); + HCB_DATA_OUT : out std_logic_vector(31 downto 0); + HCB_DATAREADY_OUT : out std_logic; + HCB_UNKNOWN_ADDR_OUT : out std_logic; -- TDC_DEBUG : out std_logic_vector(32*2**STATUS_REG_NR-1 downto 0); LOGIC_ANALYSER_OUT : out std_logic_vector(15 downto 0); @@ -175,6 +178,8 @@ architecture TDC of TDC is signal wrong_readout_number : std_logic_vector(23 downto 0); signal spike_number : std_logic_vector(23 downto 0); signal spike_detected_pulse : std_logic; + signal timeout_number : std_logic_vector(23 downto 0); + signal timeout_detected_pulse : std_logic; signal idle_i : std_logic; signal idle_fsm : std_logic; signal idle_time : std_logic_vector(23 downto 0); @@ -186,10 +191,12 @@ architecture TDC of TDC is signal wait_time : std_logic_vector(23 downto 0); signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal total_empty_channel : std_logic_vector(23 downto 0); - signal channel_lost_hit_number : statistics_array_24; - signal channel_hit_detect_number : statistics_array_24; - signal channel_encoder_start_number : statistics_array_24; - signal channel_fifo_wr_number : statistics_array_24; + signal channel_lost_hit_number : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal channel_hit_detect_number : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal channel_encoder_start_number : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal channel_fifo_wr_number : std_logic_vector_array_24(0 to CHANNEL_NUMBER-1); + signal channel_level_hit_number_i : std_logic_vector_array_32(0 to CHANNEL_NUMBER-1); + signal stop_status_i : std_logic; -- Test signals @@ -237,22 +244,22 @@ begin generic map ( CHANNEL_ID => 0) port map ( - RESET_200 => reset_tdc(0), - RESET_100 => RESET, - CLK_200 => CLK_TDC, - CLK_100 => CLK_READOUT, - HIT_IN => REFERENCE_TIME, - READ_EN_IN => rd_en_i(0), - VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, - SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, - MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, - FIFO_DATA_OUT => channel_data_i(0), - FIFO_EMPTY_OUT => channel_empty_i(0), - FIFO_FULL_OUT => channel_full_i(0), - FIFO_ALMOST_FULL_OUT => channel_almost_full_i(0), - COARSE_COUNTER_IN => coarse_cnt_reg, - TRIGGER_TIME_OUT => trigger_time_i, - REF_DEBUG_OUT => ref_debug_i); + RESET_200 => reset_tdc(0), + RESET_100 => RESET, + CLK_200 => CLK_TDC, + CLK_100 => CLK_READOUT, + HIT_IN => REFERENCE_TIME, + READ_EN_IN => rd_en_i(0), + VALID_TMG_TRG_IN => VALID_TIMING_TRG_IN, + SPIKE_DETECTED_IN => SPIKE_DETECTED_IN, + MULTI_TMG_TRG_IN => MULTI_TMG_TRG_IN, + FIFO_DATA_OUT => channel_data_i(0), + FIFO_EMPTY_OUT => channel_empty_i(0), + FIFO_FULL_OUT => channel_full_i(0), + FIFO_ALMOST_FULL_OUT => channel_almost_full_i(0), + COARSE_COUNTER_IN => coarse_cnt_reg, + TRIGGER_TIME_STAMP_OUT => trigger_time_i, + REF_DEBUG_OUT => ref_debug_i); -- Channel enable signals GEN_Channel_Enable : for i in 1 to CHANNEL_NUMBER-1 generate @@ -293,7 +300,26 @@ begin RESET => reset_coarse_cnt, COUNT_OUT => coarse_cnt, UP_IN => '1'); - coarse_cnt_reg <= coarse_cnt when rising_edge(CLK_TDC); + coarse_cnt_reg <= coarse_cnt when rising_edge(CLK_TDC); + + -- Bus handler for the hit counter signals + TheHitCounterBus : BusHandler + generic map ( + CHANNEL_NUMBER => CHANNEL_NUMBER-1) + port map ( + RESET => RESET, + CLK => CLK_READOUT, + DATA_IN => channel_level_hit_number_i, + READ_EN_IN => HCB_READ_EN_IN, + WRITE_EN_IN => HCB_WRITE_EN_IN, + ADDR_IN => HCB_ADDR_IN, + DATA_OUT => HCB_DATA_OUT, + DATAREADY_OUT => HCB_DATAREADY_OUT, + UNKNOWN_ADDR_OUT => HCB_UNKNOWN_ADDR_OUT); + + GenHitCounterLevelSignals: for i in 1 to CHANNEL_NUMBER-1 generate + channel_level_hit_number_i(i) <= hit_in_i(i) & "0000000" & channel_hit_detect_number(i); + end generate GenHitCounterLevelSignals; -- Trigger mode control register synchronised to the coarse counter clk Readout_trigger_mode_sync : bit_sync @@ -572,8 +598,10 @@ begin when 8 => data_out_reg <= "010" & "01000" & spike_number; when 9 => data_out_reg <= "010" & "01001" & idle_time; when 10 => data_out_reg <= "010" & "01010" & wait_time; - stop_status_i <= '1'; when 11 => data_out_reg <= "010" & "01011" & total_empty_channel; + when 12 => data_out_reg <= "010" & "01100" & readout_time; + stop_status_i <= '1'; + when 13 => data_out_reg <= "010" & "01101" & timeout_number; i := -1; when others => null; end case; @@ -776,7 +804,7 @@ begin if TRG_DATA_VALID_IN = '1' then FSM_NEXT <= WAIT_FOR_LVL1_TRG_B; elsif TMGTRG_TIMEOUT_IN = '1' then - FSM_NEXT <= IDLE; + FSM_NEXT <= SEND_TRG_RELEASE_A; --IDLE; else FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; end if; @@ -888,6 +916,13 @@ begin signal_in => SPIKE_DETECTED_IN, pulse => spike_detected_pulse); + edge_to_pulse_7 : edge_to_pulse + port map ( + clock => CLK_READOUT, + en_clk => '1', + signal_in => TMGTRG_TIMEOUT_IN, + pulse => timeout_detected_pulse); + -- purpose: Internal trigger number counter (only valid triggers) Statistics_Trigger_Number : process (CLK_READOUT, RESET) begin @@ -996,6 +1031,18 @@ begin end if; end process Statistics_Spike_Number; + -- purpose: Internal timeout number counter + Statistics_Timeout_Number : process (CLK_READOUT, RESET) + begin + if rising_edge(CLK_READOUT) then + if RESET = '1' then + timeout_number <= (others => '0'); + elsif timeout_detected_pulse = '1' then + timeout_number <= timeout_number + 1; + end if; + end if; + end process Statistics_Timeout_Number; + -- purpose: IDLE time of the TDC readout Statistics_Idle_Time : process (CLK_READOUT, RESET) begin @@ -1136,8 +1183,8 @@ begin -- Register 0x8f TDC_DEBUG(15*32+23 downto 15*32+0) <= release_number; - --Register 0x90 - -- TDC_DEBUG(16*32+23 downto 16*32+0) <= channel_lost_hit_number(1); +-- Register 0x90 + TDC_DEBUG(16*32+23 downto 16*32+0) <= timeout_number; --Register 0x91 -- TDC_DEBUG(17*32+23 downto 17*32+0) <= channel_hit_detect_number(1); diff --git a/tdc_releases/tdc_v0.5/trb3_periph.vhd b/tdc_releases/tdc_v0.5/trb3_periph.vhd index bca6314..98fc1c9 100644 --- a/tdc_releases/tdc_v0.5/trb3_periph.vhd +++ b/tdc_releases/tdc_v0.5/trb3_periph.vhd @@ -33,10 +33,10 @@ entity trb3_periph is --Connection to ADA AddOn SPARE_LINE : inout std_logic_vector(3 downto 0); --inputs only INP : in std_logic_vector(63 downto 0); - --DAC_SDO : in std_logic; - --DAC_SDI : out std_logic; - --DAC_SCK : out std_logic; - --DAC_CS : out std_logic_vector(3 downto 0); + DAC_SDO : in std_logic; + DAC_SDI : out std_logic; + DAC_SCK : out std_logic; + DAC_CS : out std_logic_vector(3 downto 0); --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; @@ -74,10 +74,10 @@ entity trb3_periph is attribute syn_useioff of TEST_LINE : signal is true; attribute syn_useioff of INP : signal is false; attribute syn_useioff of SPARE_LINE : signal is true; - --attribute syn_useioff of DAC_SDO : signal is true; - --attribute syn_useioff of DAC_SDI : signal is true; - --attribute syn_useioff of DAC_SCK : signal is true; - --attribute syn_useioff of DAC_CS : signal is true; + attribute syn_useioff of DAC_SDO : signal is true; + attribute syn_useioff of DAC_SDI : signal is true; + attribute syn_useioff of DAC_SCK : signal is true; + attribute syn_useioff of DAC_CS : signal is true; end entity; @@ -191,9 +191,13 @@ architecture trb3_periph_arch of trb3_periph is signal spidac_ack : std_logic; signal spidac_busy : std_logic; - signal dac_cs_i : std_logic_vector(3 downto 0); - signal dac_sck_i : std_logic; - signal dac_sdi_i : std_logic; + signal hitreg_read_en : std_logic; + signal hitreg_write_en : std_logic; + signal hitreg_data_in : std_logic_vector(31 downto 0); + signal hitreg_addr : std_logic_vector(6 downto 0); + signal hitreg_data_out : std_logic_vector(31 downto 0); + signal hitreg_data_ready : std_logic; + signal hitreg_invalid : std_logic; signal spi_bram_addr : std_logic_vector(7 downto 0); signal spi_bram_wr_d : std_logic_vector(7 downto 0); @@ -415,9 +419,9 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, others => 0) + PORT_NUMBER => 4, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"d400", 3 => x"c000", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 5, 3 => 7, others => 0) ) port map( CLK => clk_100_i, @@ -470,7 +474,19 @@ begin BUS_WRITE_ACK_IN(2) => spidac_ack, BUS_NO_MORE_DATA_IN(2) => spidac_busy, BUS_UNKNOWN_ADDR_IN(2) => '0', - + --HitRegisters + BUS_READ_ENABLE_OUT(3) => hitreg_read_en, + BUS_WRITE_ENABLE_OUT(3) => hitreg_write_en, + BUS_DATA_OUT(3*32+31 downto 3*32) => open, + BUS_ADDR_OUT(3*16+6 downto 3*16) => hitreg_addr, + BUS_ADDR_OUT(3*16+15 downto 3*16+7) => open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => hitreg_data_out, + BUS_DATAREADY_IN(3) => hitreg_data_ready, + BUS_WRITE_ACK_IN(3) => '0', + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => hitreg_invalid, + STAT_DEBUG => open ); @@ -540,14 +556,10 @@ begin BUS_DATA_OUT => spidac_data_out, -- SPI connections SPI_CS_OUT(15 downto 4) => open, - SPI_CS_OUT(3 downto 0) => dac_cs_i, + SPI_CS_OUT(3 downto 0) => DAC_CS, SPI_SDI_IN => open, - SPI_SDO_OUT => dac_sdi_i, - SPI_SCK_OUT => dac_sck_i); - - --DAC_CS <= open; --dac_cs_i; - --DAC_SDI <= open; --dac_sdi_i; - --DAC_SCK <= open; --dac_sck_i; + SPI_SDO_OUT => DAC_SDI, + SPI_SCK_OUT => DAC_SCK); --------------------------------------------------------------------------- -- Reboot FPGA @@ -580,7 +592,7 @@ begin THE_TDC : TDC generic map ( - CHANNEL_NUMBER => 17, -- Number of TDC channels + CHANNEL_NUMBER => 65, -- Number of TDC channels STATUS_REG_NR => REGIO_NUM_STAT_REGS, CONTROL_REG_NR => REGIO_NUM_CTRL_REGS) port map ( @@ -588,7 +600,7 @@ begin CLK_TDC => CLK_PCLK_LEFT, -- Clock used for the time measurement CLK_READOUT => clk_100_i, -- Clock for the readout REFERENCE_TIME => timing_trg_received_i, -- Reference time input - HIT_IN => hit_in_i(16 downto 1), -- Channel start signals + HIT_IN => hit_in_i(64 downto 1), -- Channel start signals TRG_WIN_PRE => ctrl_reg(42 downto 32), -- Pre-Trigger window width TRG_WIN_POST => ctrl_reg(58 downto 48), -- Post-Trigger window width -- @@ -614,6 +626,14 @@ begin DATA_WRITE_OUT => fee_data_write_i, -- data valid signal DATA_FINISHED_OUT => fee_data_finished_i, -- readout finished signal -- + --Hit Counter Bus + HCB_READ_EN_IN => hitreg_read_en, -- bus read en strobe + HCB_WRITE_EN_IN => hitreg_write_en, -- bus write en strobe + HCB_ADDR_IN => hitreg_addr, -- bus address + HCB_DATA_OUT => hitreg_data_out, -- bus data + HCB_DATAREADY_OUT => hitreg_data_ready, -- bus data ready strobe + HCB_UNKNOWN_ADDR_OUT => hitreg_invalid, -- bus invalid addr + -- TDC_DEBUG => stat_reg, LOGIC_ANALYSER_OUT => logic_analyser_i, CONTROL_REG_IN => ctrl_reg);