From: Andreas Neiser <neiser@kph.uni-mainz.de>
Date: Wed, 14 Jan 2015 10:26:34 +0000 (+0100)
Subject: ADC: convert explicitly to std_logic_vector
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6cd1461d5322989daa114720550c485c81d5b0e3;p=trb3.git

ADC: convert explicitly to std_logic_vector
---

diff --git a/ADC/source/adc_ad9219.vhd b/ADC/source/adc_ad9219.vhd
index 9fb3678..3a1d16b 100644
--- a/ADC/source/adc_ad9219.vhd
+++ b/ADC/source/adc_ad9219.vhd
@@ -248,7 +248,7 @@ gen_chips : for i in 0 to NUM_DEVICES-1 generate
 
   proc_debug : process begin
     wait until rising_edge(CLK);
-    DEBUG(i*32+31 downto i*32+4) <= counter(i);
+    DEBUG(i*32+31 downto i*32+4) <= std_logic_vector(counter(i));
     case state_q(i) is
       when S1 =>     DEBUG(i*32+3 downto  i*32+0) <= x"1";
       when S2 =>     DEBUG(i*32+3 downto  i*32+0) <= x"2";