From: Jan Michel Date: Tue, 18 Jul 2017 16:37:42 +0000 (+0200) Subject: Move some MachXO3 files to new repository 'vhdlbasics' X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6cd1bec02e6613cc89c784fb309caad11b8ab5cb;p=dirich.git Move some MachXO3 files to new repository 'vhdlbasics' --- diff --git a/.gitignore b/.gitignore index 4e16d7d..7c6b138 100644 --- a/.gitignore +++ b/.gitignore @@ -32,4 +32,5 @@ licbug.txt old config_compile.pl ._Real_._Math_.vhd -diamond \ No newline at end of file +diamond +diamondwin diff --git a/code/pwm_machxo.vhd b/code/pwm_machxo.vhd deleted file mode 100644 index 0298b89..0000000 --- a/code/pwm_machxo.vhd +++ /dev/null @@ -1,82 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - - - -entity pwm_generator is - generic( - CHANNELS : integer := 32 - ); - port( - CLK : in std_logic; - - DATA_IN : in std_logic_vector(15 downto 0) := (others => '0'); - DATA_OUT : out std_logic_vector(15 downto 0); - WRITE_IN : in std_logic := '0'; - COMP_IN : in signed(15 downto 0); - ADDR_IN : in std_logic_vector(4 downto 0) := (others => '0'); - - - PWM : out std_logic_vector(CHANNELS-1 downto 0) - - ); -end entity; - - - -architecture pwm_arch of pwm_generator is - -type ram_t is array(0 to CHANNELS-1) of unsigned(15 downto 0); -signal set : ram_t := (others => x"87C1"); -signal set_tmp : ram_t; - -type cnt_t is array(0 to CHANNELS-1) of unsigned(16 downto 0); -signal cnt : cnt_t := (others => (others => '0')); - -signal last_flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); -signal flag : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); -signal pwm_i : std_logic_vector(CHANNELS-1 downto 0) := (others => '0'); - -signal i : integer range 0 to CHANNELS-1 := 0; -signal clock_enable : std_logic_vector(15 downto 0) := x"0001"; -begin - -PROC_MEM : process begin - wait until rising_edge(CLK); - if WRITE_IN = '1' then - set(to_integer(unsigned(ADDR_IN))) <= unsigned(DATA_IN); - end if; - DATA_OUT <= std_logic_vector(set(to_integer(unsigned(ADDR_IN)))); -end process; - - -GEN_REAL_VALUES : process begin - wait until rising_edge(CLK); - set_tmp(i) <= unsigned(signed(set(i)) + COMP_IN); - i <= i + 1; -end process; - -process begin - wait until rising_edge(CLK); - clock_enable <= clock_enable(14 downto 0) & clock_enable(15); -end process; - -gen_channels : for i in 0 to CHANNELS-1 generate - flag(i) <= cnt(i)(16); - - process begin - wait until rising_edge(CLK); - if clock_enable(i) = '1' then - last_flag(i) <= flag(i); - pwm_i(i) <= (last_flag(i) xor flag(i)); - cnt(i) <= cnt(i) + resize(set_tmp(i),17); - end if; - end process; -end generate; - - - -PWM(CHANNELS-1 downto 0 ) <= pwm_i(CHANNELS-1 downto 0); - -end architecture; diff --git a/code/spi_slave.vhd b/code/spi_slave.vhd deleted file mode 100644 index 1223524..0000000 --- a/code/spi_slave.vhd +++ /dev/null @@ -1,154 +0,0 @@ -library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; - -library work; -use work.trb_net_std.all; - - -entity spi_slave is - port( - CLK : in std_logic; - - SPI_CLK : in std_logic; - SPI_CS : in std_logic; - SPI_IN : in std_logic; - SPI_OUT : out std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - DATA_IN : in std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector(7 downto 0); - WRITE_OUT : out std_logic; - READ_OUT : out std_logic; - READY_IN : in std_logic; - - DEBUG : out std_logic_vector(15 downto 0) - ); -end entity; - -architecture SPI_Slave_arch of spi_slave is -signal spi_clk_last : std_logic; -signal spi_clk_reg : std_logic; -signal spi_cs_reg : std_logic; -signal spi_in_reg : std_logic; - -signal operation_i : std_logic; -signal data_write : std_logic_vector(15 downto 0); -signal data_in_i : std_logic_vector(15 downto 0); -signal addr_i : std_logic_vector(7 downto 0); -signal last_input : std_logic; -signal input : std_logic_vector(31 downto 0); - -signal next_output : std_logic; -signal output_data : std_logic_vector (31 downto 0); - -signal bitcnt : integer range 0 to 31 := 31; - -type state_t is (IDLE, WAIT_FOR_CMD, GET_DATA, PREPARE_OUTPUT, WRITE_DATA, WAIT_FINISH); -signal state : state_t; - -signal buf_SPI_OUT : std_logic; - -begin - -spi_clk_last <= spi_clk_reg when rising_edge(CLK); -spi_clk_reg <= SPI_CLK when rising_edge(CLK); -spi_cs_reg <= SPI_CS when rising_edge(CLK); -spi_in_reg <= SPI_IN when rising_edge(CLK); - -DATA_OUT <= data_write; - -PROC_OUTPUT : process begin - wait until rising_edge(CLK); - next_output <= output_data(bitcnt); - if spi_clk_reg = '0' and spi_clk_last = '1' then - SPI_OUT <= last_input; - if operation_i = '0' and bitcnt <= 15 then - SPI_OUT <= next_output; - end if; - end if; -end process; - -PROC_INPUT_SHIFT : process begin - wait until rising_edge(CLK); - if spi_cs_reg = '1' then - bitcnt <= 31; - else - if spi_clk_reg = '1' and spi_clk_last = '0' then - if bitcnt /= 0 then - bitcnt <= bitcnt - 1; - else - bitcnt <= 31; - end if; - last_input <= spi_in_reg; - input(bitcnt) <= spi_in_reg; - end if; - end if; -end process; - -PROC_GEN_SIGNALS : process begin - wait until rising_edge(CLK); - --write_i <= (others => '0'); - READ_OUT <= '0'; - WRITE_OUT <= '0'; - case state is - when IDLE => - --operation_i <= x"0"; - if spi_cs_reg = '0' then - state <= WAIT_FOR_CMD; - end if; - - when WAIT_FOR_CMD => - if bitcnt = 22 then - operation_i <= input(23); - if (input(23) = '0') then - READ_OUT <= '1'; - --else - -- WRITE_OUT <= '1'; - end if; - ADDR_OUT <= input(31 downto 24); - state <= GET_DATA; - end if; - - when GET_DATA => - state <= PREPARE_OUTPUT; - - when PREPARE_OUTPUT => - if READY_IN = '1' then - output_data(15 downto 0) <= DATA_IN; - end if; - state <= WRITE_DATA; - - when WRITE_DATA => - if bitcnt = 31 then - if operation_i = '1' then - WRITE_OUT <= '1'; - data_write <= input(15 downto 0); - --write_i(to_integer(unsigned(input(31 downto 28)))) <= '1'; - end if; - state <= WAIT_FINISH; - end if; - - when WAIT_FINISH => - WRITE_OUT <= '0'; - --if spi_cs_reg = '1' then - state <= IDLE; - --end if; - - end case; - - if spi_cs_reg = '1' then - state <= IDLE; - operation_i <= '0'; - end if; -end process; - -DEBUG(0) <= spi_clk_reg; -DEBUG(1) <= spi_cs_reg; -DEBUG(2) <= spi_in_reg; -DEBUG(3) <= buf_SPI_OUT; -DEBUG(7 downto 4) <= std_logic_vector(to_unsigned(bitcnt,4)); -DEBUG(14 downto 8) <= input(30 downto 24); ---DEBUG_OUT(15) <= write_i(4); - -end; \ No newline at end of file diff --git a/thresholds/thresholds.prj b/thresholds/thresholds.prj index dfd8284..55e559c 100644 --- a/thresholds/thresholds.prj +++ b/thresholds/thresholds.prj @@ -9,9 +9,9 @@ #add_file -vhdl -lib work "../../trbnet/lattice/machxo3/fifo_9x2k_oreg.vhd" #add file -vhdl -lib work "./test/machxo3lf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" -add_file -vhdl -lib work "../../dirich/code/spi_slave.vhd" -add_file -vhdl -lib work "../../logicbox/code/sedcheck.vhd" -add_file -vhdl -lib work "../code/pwm_machxo.vhd" +add_file -vhdl -lib work "../../vhdlbasics/interface/spi_slave.vhd" +add_file -vhdl -lib work "../../vhdlbasics/machxo3/sedcheck.vhd" +add_file -vhdl -lib work "../../vhdlbasics/io/pwm.vhd" add_file -vhdl -lib work "../../logicbox/UFM_control/UFM_control.vhd" add_file -vhdl -lib work "../../logicbox/cores/flashram.vhd" add_file -vhdl -lib work "../../logicbox/cores/flash.vhd" diff --git a/thresholds/thresholds.vhd b/thresholds/thresholds.vhd index 3c4d374..1f4d8e0 100644 --- a/thresholds/thresholds.vhd +++ b/thresholds/thresholds.vhd @@ -327,6 +327,9 @@ end process; THE_SED : entity work.sedcheck + generic map( + DEV_DENSITY =>"4300L" + ) port map( CLK => clk_i, ERROR_OUT => sed_error,