From: Jan Michel <j.michel@gsi.de>
Date: Tue, 4 Mar 2014 11:56:25 +0000 (+0100)
Subject: added input scaler description
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6da513b85a204ca3d9492050d7ac41d32e0aecc3;p=daqdocu.git

added input scaler description
---

diff --git a/trb3/TriggerModule.tex b/trb3/TriggerModule.tex
index fd00264..63d53ae 100644
--- a/trb3/TriggerModule.tex
+++ b/trb3/TriggerModule.tex
@@ -20,8 +20,31 @@ to one of the RJ-45 sockets on the CTS-AddOn.
 \paragraph*{SlowControl}
 Configuration of the module can be done in registers 0xcf00 to 0xcf3f. Each output has four 
 configuration registers. The first one contains a bit mask to enable individual inputs. The second 
-one contains a bitmask to invert individual input signals. The other two registers are reserved for 
-future extensions. 
+one contains a bitmask to invert individual input signals.
 
-In case of four outputs configured, registers 0xcf00, 0xcf04, 0xcf08 and 0xcf0c contain the enable 
-bit mask and registers 0xcf01, 0xcf05, 0xcf09 and 0xcf0d contain the inverter bits.
\ No newline at end of file
+In case of four outputs configured, registers 0xcf00, 0xcf02, 0xcf04 and 0xcf06 contain the enable 
+bit mask and registers 0xcf01, 0xcf03, 0xcf05 and 0xcf07 contain the inverter bits.
+
+\paragraph*{Input Scalers}
+An additional module is used to have counters for each of up to 32 input channels. These values can
+be stored in a Fifo at an adjustable rate. The Fifos for all channels are controlled by a common
+logic and store their data synchronously. Filling of the Fifos has to be triggered and stops after
+1024 samples have been acquired.
+
+\begin{description*}
+ \item[cf00, cf02 .. cf1e] Input enable mask. Up to 16 times, according to number of outputs.
+ \item[cf01, cf03 .. cf1f] Input invert mask. Up to 16 times, according to number of outputs.
+ \item[cf20] Status of all input signals
+ \item[cf21] Status of all trigger output signals
+ \item[cf80] Input enable for monitoring
+ \item[cf81] Input invert for monitoring
+ \item[cf82] Set the monitoring rate in units of 10 ns (FPGA clock frequency)
+ \item[cf83] Debug: Current value of the timer register
+ \item[cf84] Debug: Status register
+ \item[cf8e] Status of all input signals
+ \item[cf8f] Bit 0: Trigger recording of data. Fifo are cleared, then 1024 samples are acquired\\
+             Bit 1: Reset counters
+ \item[cfa0 .. cfbf] One fifo for each input. Up to 1024 values of 18 Bit are stored. The uppermost
+bit is the Fifo empty signal (data invalid)
+ \item[cfc0 .. cfdf] One counter for each input. The width is 24 Bit.
+\end{description*}
\ No newline at end of file