From: Jan Michel Date: Mon, 8 Aug 2022 12:10:54 +0000 (+0200) Subject: finish CTS / backplane master design X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6dde3bba61813612d239d7e1f0c690647223157b;p=trb3sc.git finish CTS / backplane master design --- diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 6fe8d52..319220c 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -26,7 +26,7 @@ entity trb3sc_cts is BACK_GPIO : inout std_logic_vector( 3 downto 0); SPARE_IN : in std_logic_vector( 1 downto 0); - INP : in std_logic_vector(31-12*USE_RJADAPT downto 0); + INP : in std_logic_vector(31-12*USE_RJADAPT+64*USE_BACKPLANE downto 64*USE_BACKPLANE); RJ_IO : out std_logic_vector( 3 downto 0); --0, inner RJ trigger output RJ_IO_IN : in std_logic_vector( 1 downto 0); REFOUT : out std_logic_vector( 8*USE_RJADAPT-1 downto 0); @@ -49,20 +49,20 @@ entity trb3sc_cts is SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); - LED_HUB_LINKOK : out std_logic_vector(8 downto 1); - LED_HUB_RX : out std_logic_vector(8 downto 1); - LED_HUB_TX : out std_logic_vector(8 downto 1); - HUB_MOD0 : in std_logic_vector(8 downto 1); - HUB_MOD1 : inout std_logic_vector(8 downto 1); - HUB_MOD2 : inout std_logic_vector(8 downto 1); - HUB_TXDIS : out std_logic_vector(8 downto 1); - HUB_LOS : in std_logic_vector(8 downto 1); + LED_HUB_LINKOK : out std_logic_vector(8*USE_ADDON-1 downto 1); + LED_HUB_RX : out std_logic_vector(8*USE_ADDON-1 downto 1); + LED_HUB_TX : out std_logic_vector(8*USE_ADDON-1 downto 1); + HUB_MOD0 : in std_logic_vector(8*USE_ADDON-1 downto 1); + HUB_MOD1 : inout std_logic_vector(8*USE_ADDON-1 downto 1); + HUB_MOD2 : inout std_logic_vector(8*USE_ADDON-1 downto 1); + HUB_TXDIS : out std_logic_vector(8*USE_ADDON-1 downto 1); + HUB_LOS : in std_logic_vector(8*USE_ADDON-1 downto 1); --Lines to slaves - BACK_MASTER_READY : out std_logic_vector(8 downto 0); - BACK_SLAVE_READY : in std_logic_vector(8 downto 0); - BACK_TRIG1 : in std_logic_vector(8 downto 0); - BACK_TRIG2 : in std_logic_vector(8 downto 0); + BACK_MASTER_READY : out std_logic_vector(9*USE_BACKPLANE-1 downto 0); + BACK_SLAVE_READY : in std_logic_vector(9*USE_BACKPLANE-1 downto 0); + BACK_TRIG1 : in std_logic_vector(9*USE_BACKPLANE-1 downto 0); + BACK_TRIG2 : in std_logic_vector(9*USE_BACKPLANE-1 downto 0); --Serdes switch PCSSW_ENSMB : out std_logic; @@ -77,10 +77,10 @@ entity trb3sc_cts is ADC_DOUT : in std_logic; --SPI - DAC_OUT_SDO : out std_logic_vector(6 downto 5+2*USE_RJADAPT); -- - DAC_OUT_SCK : out std_logic_vector(6 downto 5+2*USE_RJADAPT); -- - DAC_OUT_CS : out std_logic_vector(6 downto 5+2*USE_RJADAPT); -- - DAC_IN_SDI : in std_logic_vector(6 downto 5+2*USE_RJADAPT); -- + DAC_OUT_SDO : out std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); -- + DAC_OUT_SCK : out std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); -- + DAC_OUT_CS : out std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); -- + DAC_IN_SDI : in std_logic_vector(6 downto 5+2*USE_RJADAPT+2*USE_BACKPLANE); -- --Flash, 1-wire, Reload @@ -939,7 +939,7 @@ gen_inputs_rj : if USE_BACKPLANE = 0 and USE_RJADAPT = 1 generate end generate; gen_inputs_bkpl : if USE_BACKPLANE = 1 generate cts_addon_triggers_in(1 downto 0) <= SPARE_IN(1 downto 0); - cts_addon_triggers_in(33 downto 2) <= INP(31 downto 0); + cts_addon_triggers_in(33 downto 2) <= INP(95 downto 64); cts_addon_triggers_in(35 downto 34) <= trigger_gen_outputs_i when rising_edge(clk_sys); gen_trg_inputs : for i in 0 to 8 generate cts_addon_triggers_in(i*2+37 downto i*2+36) <= BACK_TRIG2(i) & BACK_TRIG1(i); @@ -1185,7 +1185,7 @@ end generate; --------------------------------------------------------------------------- -- I/O --------------------------------------------------------------------------- -gen_SPI : if USE_RJADAPT = 0 generate +gen_SPI : if USE_RJADAPT = 0 and USE_BACKPLANE = 0 generate spi_miso(5 downto 4) <= DAC_IN_SDI(6 downto 5); DAC_OUT_SCK(6 downto 5) <= spi_clk(5 downto 4); DAC_OUT_CS(6 downto 5) <= spi_cs(5 downto 4); diff --git a/pinout/trb3sc_hub_ctsrj.lpf b/pinout/trb3sc_hub_ctsrj.lpf index 282b4a4..bb73146 100644 --- a/pinout/trb3sc_hub_ctsrj.lpf +++ b/pinout/trb3sc_hub_ctsrj.lpf @@ -295,6 +295,11 @@ IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; +LOCATE COMP "RJ_IO_IN_0" SITE "R28"; +LOCATE COMP "RJ_IO_IN_1" SITE "R31"; +IOBUF PORT "RJ_IO_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "RJ_IO_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100; + LOCATE COMP "SPARE_IN_0" SITE "K31"; LOCATE COMP "SPARE_IN_1" SITE "R4"; diff --git a/pinout/trb3sc_master.lpf b/pinout/trb3sc_master.lpf index 6276efe..cfc72c4 100644 --- a/pinout/trb3sc_master.lpf +++ b/pinout/trb3sc_master.lpf @@ -261,6 +261,11 @@ IOBUF PORT "RJ_IO_1" IO_TYPE=LVDS25 ; IOBUF PORT "RJ_IO_2" IO_TYPE=LVDS25E ; IOBUF PORT "RJ_IO_3" IO_TYPE=LVDS25E ; +LOCATE COMP "RJ_IO_IN_0" SITE "R28"; +LOCATE COMP "RJ_IO_IN_1" SITE "R31"; +IOBUF PORT "RJ_IO_IN_0" IO_TYPE=LVDS25 DIFFRESISTOR=100 ; +IOBUF PORT "RJ_IO_IN_1" IO_TYPE=LVDS25 DIFFRESISTOR=100; + LOCATE COMP "SPARE_IN_0" SITE "K31"; LOCATE COMP "SPARE_IN_1" SITE "R4";