From: Jan Michel Date: Tue, 28 Jun 2022 15:02:05 +0000 (+0200) Subject: add R3B timestamp receiver to CTS X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=6e1ea639b8994741c1c55a6a1fc6523fa43227b7;p=trb3.git add R3B timestamp receiver to CTS --- diff --git a/cts/source/r3b_timestamp_recv.vhd b/cts/source/r3b_timestamp_recv.vhd index e873928..ee2322c 100644 --- a/cts/source/r3b_timestamp_recv.vhd +++ b/cts/source/r3b_timestamp_recv.vhd @@ -13,6 +13,7 @@ use IEEE.numeric_std.All; library work; use work.rataser_records.all; use work.rataser_sym24word8_util; +use work.trb_net_std.all; entity r3b_timestamp_recv is port( @@ -24,6 +25,9 @@ entity r3b_timestamp_recv is SERIAL_OUT : out std_logic; TRG_SYNC_OUT : out std_logic; + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + --data output for read-out TRIGGER_IN : in std_logic; DATA_OUT : out std_logic_vector(31 downto 0); @@ -53,6 +57,7 @@ architecture arch of r3b_timestamp_recv is signal CONF_time_offset : std_logic_vector(15 downto 0); signal CONF_clear_status_i : std_logic; signal CONF_loopback : std_logic; + signal CONF_use_pulse_period_ns : std_logic; signal serial_in_i : std_logic; signal serial_out_i : std_logic; signal aux_sigs_i : std_logic_vector(4 downto 0); @@ -61,6 +66,11 @@ architecture arch of r3b_timestamp_recv is signal bad_signals_i : std_logic_vector(4 downto 0); signal sender_timestamp : unsigned(63 downto 0); signal sender_timestamp_upper_enable : std_logic; + signal sender_period_ns_i : std_logic_vector(9 downto 0); + signal track_incr_per_clock_i : std_logic_vector(15 downto 0); + signal pulse_length_min_i : std_logic_vector(9 downto 0); + signal pulse_length_max_i : std_logic_vector(9 downto 0); + component rataser_clock_recv is generic( @@ -96,6 +106,10 @@ architecture arch of r3b_timestamp_recv is clear_status: in std_logic; pulse_period_clks: in std_logic_vector(period_bits-1 downto 0); clk_period_ns: in std_logic_vector(9 downto 0); + sender_period_ns: out std_logic_vector(9 downto 0); + track_incr_per_clock: out std_logic_vector(15 downto 0); + pulse_length_min: out std_logic_vector(9 downto 0); + pulse_length_max: out std_logic_vector(9 downto 0); sym8_debug: out rataser_sym8word1_debug ); end component; @@ -122,6 +136,7 @@ architecture arch of r3b_timestamp_recv is eight_slot: in std_logic; -- Pulse period (in ns, encoded in message). pulse_period_ns: in std_logic_vector(9 downto 0); + use_pulse_period_ns: in std_logic; -- Message delay (in ns, added to time in message). message_delay_ns: in std_logic_vector(21 downto 0); -- Output message. @@ -178,6 +193,12 @@ THE_RATASER_CLOCK : rataser_clock_recv pulse_period_clks=> (others => '0'), -- When operated behind a PLL, the pulse length (in clock cycles) clk_period_ns => (others => '0'), -- When operated behind a PLL, the frequency must be given. + sender_period_ns => sender_period_ns_i, + track_incr_per_clock => track_incr_per_clock_i, + pulse_length_min => pulse_length_min_i, + pulse_length_max => pulse_length_max_i, + + sym8_debug => open ); @@ -231,6 +252,7 @@ THE_RATASER_CLOCK : rataser_clock_recv CONF_time_offset <= CONTROL_REG_IN(15 downto 0) when rising_edge(CLK); CONF_clear_status_i <= CONTROL_REG_IN(16) when rising_edge(CLK); + CONF_use_pulse_period_ns <= CONTROL_REG_IN(27) when rising_edge(CLK); CONF_loopback <= CONTROL_REG_IN(31) when rising_edge(CLK); DEBUG <= x"00000000"; @@ -238,6 +260,37 @@ THE_RATASER_CLOCK : rataser_clock_recv HEADER_REG_OUT <= b"10"; -- send four words on DATA_OUT +--------------------------------------------------------------------------- +-- Slow Control Bus +--------------------------------------------------------------------------- +THE_RDO_STAT : process begin + wait until rising_edge(CLK); + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + BUS_TX.unknown <= '0'; + + if BUS_RX.write = '1' then + BUS_TX.unknown <= '1'; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + if BUS_RX.addr = x"0000" then + BUS_TX.data(31 downto 0) <= status_i; + elsif BUS_RX.addr = x"0001" then + BUS_TX.data(31 downto 0) <= track_incr_per_clock_i & "000000" & sender_period_ns_i; + elsif BUS_RX.addr = x"0002" then + BUS_TX.data(31 downto 0) <= "000000" & pulse_length_max_i & "000000" & pulse_length_min_i; + elsif BUS_RX.addr = x"0003" then + BUS_TX.data(31 downto 0) <= timestamp_i(31 downto 0); + elsif BUS_RX.addr = x"0004" then + BUS_TX.data(31 downto 0) <= timestamp_i(63 downto 32); + else + BUS_TX.ack <= '0'; + BUS_TX.unknown <= '1'; + end if; + end if; +end process; + + --------------------------------------------------------------------------- -- Dummy timestamp sender --------------------------------------------------------------------------- @@ -246,7 +299,7 @@ THE_SENDER: rataser_clock_send period_bits => 6 ) port map( - clk => CLK, + clk => CLK_SENDER, tick_ns => std_logic_vector(sender_timestamp), aux_sigs => "00000", info_bit => '0', @@ -256,7 +309,8 @@ THE_SENDER: rataser_clock_send duty_low_max_clks => "010000", eight_slot => '0', - pulse_period_ns => 320, + pulse_period_ns => 256, + use_pulse_period_ns => CONF_use_pulse_period_ns, message_delay_ns => (others => '0'), transmit => serial_out_i, @@ -265,16 +319,16 @@ THE_SENDER: rataser_clock_send PROC_TIMESTAMP : process begin - wait until rising_edge(CLK); + wait until rising_edge(CLK_SENDER); - sender_timestamp(31 downto 0) <= sender_timestamp(31 downto 0) + 10; + sender_timestamp(31 downto 0) <= sender_timestamp(31 downto 0) + 8; if sender_timestamp_upper_enable = '1' then sender_timestamp(63 downto 32) <= sender_timestamp(63 downto 32) + 1; end if; sender_timestamp_upper_enable <= '0'; - if sender_timestamp(31 downto 0) < 10 then + if sender_timestamp(31 downto 0) < 8 then sender_timestamp_upper_enable <= '1'; end if;