From: Tobias Weber <toweber86@gmail.com>
Date: Fri, 16 Nov 2018 14:17:28 +0000 (+0100)
Subject: modify trigger state machine reset
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7046cc3dcf51997c11050b5188093a0dde7a27b0;p=trb3.git

modify trigger state machine reset
---

diff --git a/mupix/Mupix8/sources/Datapath/TriggerHandler.vhd b/mupix/Mupix8/sources/Datapath/TriggerHandler.vhd
index 2319ef7..43c6922 100644
--- a/mupix/Mupix8/sources/Datapath/TriggerHandler.vhd
+++ b/mupix/Mupix8/sources/Datapath/TriggerHandler.vhd
@@ -15,8 +15,8 @@ entity TriggerHandler is
     CLK_IN   : in std_logic;
     RESET_IN : in std_logic;
 
-    --Input Triggers          
-    TIMING_TRIGGER_IN          : in std_logic;  -- The raw timing Trigger Signal 
+    --Input Triggers
+    TIMING_TRIGGER_IN          : in std_logic;  -- The raw timing Trigger Signal
     LVL1_TRG_DATA_VALID_IN     : in std_logic;  -- Data Trigger is valid
     LVL1_VALID_TIMING_TRG_IN   : in std_logic;  -- Timin Trigger is valid
     LVL1_VALID_NOTIMING_TRG_IN : in std_logic;  -- calib trigger w/o ref time
@@ -42,7 +42,7 @@ entity TriggerHandler is
     -- OUT
     VALID_TRIGGER_OUT : out std_logic;
 
-    -- Slave bus               
+    -- Slave bus
     SLV_READ_IN          : in  std_logic;
     SLV_WRITE_IN         : in  std_logic;
     SLV_DATA_OUT         : out std_logic_vector(31 downto 0);
@@ -60,7 +60,6 @@ architecture behavioral of TriggerHandler is
 --trigger
   signal bypass_trigger           : std_logic                     := '1';
   signal reset_trigger_state      : std_logic                     := '0';
-  signal reset_trigger_state_edge : std_logic_vector(1 downto 0)  := "00";
   signal valid_trigger_int        : std_logic                     := '0';
   signal timing_trigger_edge      : std_logic_vector(1 downto 0)  := "00";
   signal trigger_busy_int         : std_logic                     := '0';
@@ -130,11 +129,9 @@ begin
       if reset_in = '1' then
         buffer_readout_end_int   <= (others => '0');
         timing_trigger_edge      <= (others => '0');
-        reset_trigger_state_edge <= (others => '0');
       else
         buffer_readout_end_int   <= buffer_readout_end_int(0) & TRIGGER_BUSY_BUFFER_READ_IN;
         timing_trigger_edge      <= timing_trigger_edge(0) & TIMING_TRIGGER_IN;
-        reset_trigger_state_edge <= reset_trigger_state_edge(0) & reset_trigger_state;
       end if;
     end if;
   end process Signal_Edge_Detect;
@@ -154,7 +151,8 @@ begin
       valid_trigger_int     <= '0';
       fee_data_finished_int <= '0';
       fee_trg_release_int   <= '0';
-      if reset_in = '1' or LVL1_INVALID_TRG_IN = '1' or reset_trigger_state_edge = "01" then
+      trigger_handler_fsm   <= idle;
+      if reset_in = '1' or LVL1_INVALID_TRG_IN = '1' or reset_trigger_state = '1' then
         valid_trigger_int     <= '0';
         fee_data_finished_int <= '0';
         fee_trg_release_int   <= '0';
@@ -165,6 +163,7 @@ begin
         wr_data_int           <= '0';
         wr_status_int         <= '0';
         wr_dummy_int          <= '0';
+        trigger_handler_fsm   <= idle;
       else
         case trigger_handler_fsm is
           when idle =>
@@ -367,6 +366,8 @@ begin
       SLV_READ_IN_i  <= SLV_READ_IN;
       SLV_WRITE_IN_i <= SLV_WRITE_IN;
 
+      reset_trigger_state <= '0';
+
       if SLV_WRITE_IN_i = '1' then
         case SLV_ADDR_IN_i is
           when x"0125" =>