From: Manuel Penschuck Date: Mon, 22 Sep 2014 16:20:25 +0000 (+0200) Subject: CTS: Included sync module, introduced new constraints; issues with CTS-endpoint after... X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=70ae1f3cfa41954582146638bb6f19e655a6b733;p=trb3.git CTS: Included sync module, introduced new constraints; issues with CTS-endpoint after TrbNet reset --- diff --git a/cts/cbmnet_bridge b/cts/cbmnet_bridge new file mode 120000 index 0000000..125ef8c --- /dev/null +++ b/cts/cbmnet_bridge @@ -0,0 +1 @@ +../cbmnet/code/ \ No newline at end of file diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index d615fa6..ac56f69 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -90,7 +90,7 @@ foreach (@a) $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; -$c=qq| $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; +$c=qq' $lattice_path/ispfpga/bin/lin/edif2ngd -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" | grep -v -e "WARNING - edif2ngd: Unsupported property" | grep -v -e "Property MEM_INIT_FILE has no value" ' ; execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; @@ -101,7 +101,7 @@ execute($c); my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/map -hier -retime EFFORT=6 -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -o "$tpmap.ncd" -xref_sig -mp "$TOPNAME.mrp" -td_pack|; execute($c); system("rm $TOPNAME.ncd"); @@ -113,6 +113,12 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); +$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; +execute($c); + +$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; +execute($c); + # TWR Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); @@ -120,11 +126,7 @@ execute($c); $c=qq|$lattice_path/ispfpga/bin/lin/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/ltxt2ptxt $TOPNAME.ncd|; -execute($c); -$c=qq|$lattice_path/ispfpga/bin/lin/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); chdir ".."; diff --git a/cts/config_default.vhd b/cts/config_default.vhd index 7542503..15a4e50 100644 --- a/cts/config_default.vhd +++ b/cts/config_default.vhd @@ -61,12 +61,10 @@ package config is ------------------------------------------------------------------------------ --Hub configuration ------------------------------------------------------------------------------ - - - type hub_mii_t is array(0 to 2) of integer; + type hub_mii_t is array(0 to 1) of integer; type hub_ct is array(0 to 16) of integer; - type hub_cfg_t is array(0 to 2) of hub_ct; - type hw_info_t is array(0 to 2) of std_logic_vector(31 downto 0); + type hub_cfg_t is array(0 to 1) of hub_ct; + type hw_info_t is array(0 to 1) of std_logic_vector(31 downto 0); --this is used to select the proper configuration in the main code constant CFG_MODE : integer; @@ -74,18 +72,16 @@ package config is --first entry is normal CTS with one optical output, second one is with four optical outputs --slow-control is accepted on SFP1 only, triggers are sent to all used SFP - constant INTERNAL_NUM_ARR : hub_mii_t := (5,5,5); - constant INTERFACE_NUM_ARR : hub_mii_t := (5,8,5); + constant INTERNAL_NUM_ARR : hub_mii_t := (5,5); + constant INTERFACE_NUM_ARR : hub_mii_t := (5,8); +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), - (0,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0), - (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0)); + (0,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0)); constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), - (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0), - (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0)); + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0)); constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), - (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), - (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0)); - constant HARDWARE_INFO_ARR : hw_info_t := (x"9000CEE0", x"9000CEE2", x"9000CEE0"); -- TODO: Adopt for CBMNet + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)); + constant HARDWARE_INFO_ARR : hw_info_t := (x"9000CEE0",x"9000CEE2"); constant INTERNAL_NUM : integer; constant INTERFACE_NUM : integer; @@ -124,15 +120,15 @@ end; package body config is --compute correct configuration mode - constant CFG_MODE : integer := 2*INCLUDE_CBMNET+USE_4_SFP; - constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC; + constant CFG_MODE : integer := USE_4_SFP; + constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC + INCLUDE_CBMNET; constant HARDWARE_INFO : std_logic_vector (31 downto 0) := HARDWARE_INFO_ARR(INCLUDE_TDC); - constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE); -- TODO: what's that ? + constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE); constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); -end package body; \ No newline at end of file +end package body; diff --git a/cts/source/cbmnet_dlm_etm.vhd b/cts/source/cbmnet_dlm_etm.vhd index c703c4d..b89de22 100644 --- a/cts/source/cbmnet_dlm_etm.vhd +++ b/cts/source/cbmnet_dlm_etm.vhd @@ -57,77 +57,79 @@ architecture cbmnet_dlm_etm_arch of cbmnet_dlm_etm is signal rdo_disable_i : std_logic; begin --- TrbNet sync - trb_fine_grain_counter_i <= cbm_fine_grain_counter_i when rising_edge(CLK); - trb_filtered_dlm_counter_i <= cbm_filtered_dlm_counter_i when rising_edge(CLK); - trb_dlm_counter_i <= cbm_dlm_counter_i when rising_edge(CLK); - - trb_ignore_resets_threshold_i <= UNSIGNED(x"00" & CONTROL_REG_IN(23 downto 0)) when rising_edge(CLK); - STATUS_REG_OUT <= x"00" & STD_LOGIC_VECTOR(trb_fine_grain_counter_i(31 downto 24)) & STD_LOGIC_VECTOR(trb_filtered_dlm_counter_i(15 downto 0)) when rising_edge(CLK); - - TRG_SYNC_OUT <= '1' when trb_fine_grain_counter_i < 4 else '0'; - --- TrbNet readout - rdo_disable_i <= CONTROL_REG_IN(0); - HEADER_REG_OUT <= "10"; -- send four data words (3 not supported w/o header) --- DATA_OUT <= rdo_buffer_i(rdo_index_i); - - PROC_RDO: process is - begin - wait until rising_edge(CLK); - - FINISHED_OUT <= '0'; - WRITE_OUT <= '0'; - STATUSBIT_OUT <= (others => '0'); - - if RESET_IN = '1' or rdo_disable_i = '1' then - rdo_fsm_i <= RDO_IDLE; - FINISHED_OUT <= '1'; - - else - case(rdo_fsm_i) is - when RDO_IDLE => - rdo_buffer_i(0) <= trb_fine_grain_counter_i; - rdo_buffer_i(1) <= trb_dlm_counter_i; - rdo_buffer_i(2) <= trb_filtered_dlm_counter_i; - rdo_buffer_i(3) <= x"deadbeaf"; - rdo_index_i <= 0; - - if TRIGGER_IN = '1' then - rdo_fsm_i <= RDO_WRITE; - WRITE_OUT <= '1'; - end if; - - when RDO_WRITE => - rdo_index_i <= rdo_index_i + 1; - if rdo_index_i = 3 then - rdo_fsm_i <= RDO_FINISH; - end if; - WRITE_OUT <= '1'; - - when RDO_FINISH => - FINISHED_OUT <= '1'; - rdo_fsm_i <= RDO_IDLE; - - end case; - end if; - end process; - --- CBMNet synchronous - cbm_ignore_resets_threshold_i <= trb_ignore_resets_threshold_i; - PROC_RECV: process is - begin - wait until rising_edge(CBMNET_CLK_IN); - - if CBMNET_DLM_REC_IN = cbm_listing_dlm_num_i and CBMNET_DLM_REC_VALID_IN = '1' then - if cbm_fine_grain_counter_i >= cbm_ignore_resets_threshold_i then - cbm_fine_grain_counter_i <= (others => '0'); - cbm_filtered_dlm_counter_i <= cbm_filtered_dlm_counter_i + 1; - end if; - - cbm_dlm_counter_i <= cbm_dlm_counter_i + 1; - end if; - end process; - - cbm_listing_dlm_num_i <= CONTROL_REG_IN(7 downto 4) when rising_edge(CBMNET_CLK_IN); +FINISHED_OUT <= '1'; +-- +-- -- TrbNet sync +-- trb_fine_grain_counter_i <= cbm_fine_grain_counter_i when rising_edge(CLK); +-- trb_filtered_dlm_counter_i <= cbm_filtered_dlm_counter_i when rising_edge(CLK); +-- trb_dlm_counter_i <= cbm_dlm_counter_i when rising_edge(CLK); +-- +-- trb_ignore_resets_threshold_i <= UNSIGNED(x"00" & CONTROL_REG_IN(23 downto 0)) when rising_edge(CLK); +-- STATUS_REG_OUT <= x"00" & STD_LOGIC_VECTOR(trb_fine_grain_counter_i(31 downto 24)) & STD_LOGIC_VECTOR(trb_filtered_dlm_counter_i(15 downto 0)) when rising_edge(CLK); +-- +-- TRG_SYNC_OUT <= '1' when trb_fine_grain_counter_i < 4 else '0'; +-- +-- -- TrbNet readout +-- rdo_disable_i <= CONTROL_REG_IN(0); +-- HEADER_REG_OUT <= "10"; -- send four data words (3 not supported w/o header) +-- -- DATA_OUT <= rdo_buffer_i(rdo_index_i); +-- +-- PROC_RDO: process is +-- begin +-- wait until rising_edge(CLK); +-- +-- FINISHED_OUT <= '0'; +-- WRITE_OUT <= '0'; +-- STATUSBIT_OUT <= (others => '0'); +-- +-- if RESET_IN = '1' or rdo_disable_i = '1' then +-- rdo_fsm_i <= RDO_IDLE; +-- FINISHED_OUT <= '1'; +-- +-- else +-- case(rdo_fsm_i) is +-- when RDO_IDLE => +-- rdo_buffer_i(0) <= trb_fine_grain_counter_i; +-- rdo_buffer_i(1) <= trb_dlm_counter_i; +-- rdo_buffer_i(2) <= trb_filtered_dlm_counter_i; +-- rdo_buffer_i(3) <= x"deadbeaf"; +-- rdo_index_i <= 0; +-- +-- if TRIGGER_IN = '1' then +-- rdo_fsm_i <= RDO_WRITE; +-- WRITE_OUT <= '1'; +-- end if; +-- +-- when RDO_WRITE => +-- rdo_index_i <= rdo_index_i + 1; +-- if rdo_index_i = 3 then +-- rdo_fsm_i <= RDO_FINISH; +-- end if; +-- WRITE_OUT <= '1'; +-- +-- when RDO_FINISH => +-- FINISHED_OUT <= '1'; +-- rdo_fsm_i <= RDO_IDLE; +-- +-- end case; +-- end if; +-- end process; +-- +-- -- CBMNet synchronous +-- cbm_ignore_resets_threshold_i <= trb_ignore_resets_threshold_i; +-- PROC_RECV: process is +-- begin +-- wait until rising_edge(CBMNET_CLK_IN); +-- +-- if CBMNET_DLM_REC_IN = cbm_listing_dlm_num_i and CBMNET_DLM_REC_VALID_IN = '1' then +-- if cbm_fine_grain_counter_i >= cbm_ignore_resets_threshold_i then +-- cbm_fine_grain_counter_i <= (others => '0'); +-- cbm_filtered_dlm_counter_i <= cbm_filtered_dlm_counter_i + 1; +-- end if; +-- +-- cbm_dlm_counter_i <= cbm_dlm_counter_i + 1; +-- end if; +-- end process; +-- +-- cbm_listing_dlm_num_i <= CONTROL_REG_IN(7 downto 4) when rising_edge(CBMNET_CLK_IN); end architecture; diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 77d1deb..0213ef5 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -301,8 +301,8 @@ if {$INCLUDE_TDC == 1} { add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd" } -add_file -vhdl -lib work "../cbmnet/code/cbmnet_interface_pkg.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_pkg.vhd" +add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_interface_pkg.vhd" +add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_pkg.vhd" if {$INCLUDE_CBMNET == 1} { set_option -include_path {../cbmnet/cbmnet/cores/CBMnet/includes/} @@ -369,21 +369,27 @@ if {$INCLUDE_CBMNET == 1} { add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_slave_top.v" add_file -verilog "../cbmnet/cbmnet/cores/CBMnet/building_blocks/LP/lp_tx_top.v" -add_file -vhdl -lib work "../base/cores/cbmnet_sfp1.vhd" -add_file -vhdl -lib work "../cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_rx_reset_fsm.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3_tx_reset_fsm.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_rx_gear.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_tx_gear.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_phy_ecp3.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_trbnet_decoder.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_event_packer.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_fifo.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout_tx_fsm.vhd" -add_file -vhdl -lib work "../cbmnet/code/cbmnet_readout.vhd" - - + add_file -vhdl -lib work "../base/cores/cbmnet_sfp1.vhd" + add_file -vhdl -lib work "../cbmnet/cores/lattice_ecp3_fifo_16x16_dualport.vhd" + add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" + + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3_rx_reset_fsm.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3_tx_reset_fsm.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_rx_gear.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_tx_gear.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3.vhd" + + add_file -vhdl -lib work "../cbmnet/cores/cbmnet_fifo_18x2k_dp.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_trbnet_decoder.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_event_packer.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_fifo_ecp3.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_frame_packer.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_tx_fifo.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_obuf.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout.vhd" + + add_file -vhdl -lib work "./cbmnet_bridge/pos_edge_strech_sync.vhd" + add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_sync_module.vhd" } add_file -vhdl -lib work "./trb3_central.vhd" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index c3662eb..a5a7dc9 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -27,8 +27,9 @@ library work; -- C0 - CF Hub control registers -- 4000 - 40FF Hub status registers -- 7000 - 72FF Readout endpoint registers --- 8100 - 83FF bGE configuration & status --- A000 - A1FF CTS configuration & status +-- 8100 - 83FF GbE configuration & status +-- A000 - A7FF CTS configuration & status +-- A800 - A8ff CBMNet -- C000 - CFFF TDC configuration & status -- D000 - D13F Flash Programming @@ -179,7 +180,103 @@ entity trb3_central is attribute syn_useioff of CLOCK_SELECT : signal is false; attribute syn_useioff of CLK_EXT : signal is false; + + -- no FF for CTS addon ... relax timing + attribute syn_useioff of ECL_IN : signal is false; + attribute syn_useioff of NIM_IN : signal is false; + attribute syn_useioff of JIN1 : signal is false; + attribute syn_useioff of JIN2 : signal is false; + attribute syn_useioff of JINLVDS : signal is false; + attribute syn_useioff of DISCRIMINATOR_IN : signal is false; + attribute syn_useioff of PWM_OUT : signal is false; + attribute syn_useioff of JOUT1 : signal is false; + attribute syn_useioff of JOUT2 : signal is false; + attribute syn_useioff of JOUTLVDS : signal is false; + attribute syn_useioff of JTTL : signal is false; + attribute syn_useioff of TRG_FANOUT_ADDON : signal is false; + attribute syn_useioff of LED_BANK : signal is false; + attribute syn_useioff of LED_RJ_GREEN : signal is false; + attribute syn_useioff of LED_RJ_RED : signal is false; + attribute syn_useioff of LED_FAN_GREEN : signal is false; + attribute syn_useioff of LED_FAN_ORANGE : signal is false; + attribute syn_useioff of LED_FAN_RED : signal is false; + attribute syn_useioff of LED_FAN_YELLOW : signal is false; + attribute syn_keep : boolean; + attribute syn_keep of CLK_EXT : signal is true; + attribute syn_keep of CLK_GPLL_LEFT : signal is true; + attribute syn_keep of CLK_GPLL_RIGHT : signal is true; + attribute syn_keep of CLK_PCLK_LEFT : signal is true; + attribute syn_keep of CLK_PCLK_RIGHT : signal is true; + attribute syn_keep of TRIGGER_LEFT : signal is true; + attribute syn_keep of TRIGGER_RIGHT : signal is true; + attribute syn_keep of TRIGGER_EXT : signal is true; + attribute syn_keep of TRIGGER_OUT : signal is true; + attribute syn_keep of TRIGGER_OUT2 : signal is true; + attribute syn_keep of CLK_SERDES_INT_LEFT : signal is true; + attribute syn_keep of CLK_SERDES_INT_RIGHT : signal is true; + attribute syn_keep of SFP_RX_P : signal is true; + attribute syn_keep of SFP_RX_N : signal is true; + attribute syn_keep of SFP_TX_P : signal is true; + attribute syn_keep of SFP_TX_N : signal is true; + attribute syn_keep of SFP_TX_FAULT : signal is true; + attribute syn_keep of SFP_RATE_SEL : signal is true; + attribute syn_keep of SFP_LOS : signal is true; + attribute syn_keep of SFP_MOD0 : signal is true; + attribute syn_keep of SFP_MOD1 : signal is true; + attribute syn_keep of SFP_MOD2 : signal is true; + attribute syn_keep of SFP_TXDIS : signal is true; + attribute syn_keep of TRIGGER_SELECT : signal is true; + attribute syn_keep of CLOCK_SELECT : signal is true; + attribute syn_keep of CLK_MNGR1_USER : signal is true; + attribute syn_keep of CLK_MNGR2_USER : signal is true; + attribute syn_keep of FPGA1_COMM : signal is true; + attribute syn_keep of FPGA2_COMM : signal is true; + attribute syn_keep of FPGA3_COMM : signal is true; + attribute syn_keep of FPGA4_COMM : signal is true; + attribute syn_keep of FPGA1_TTL : signal is true; + attribute syn_keep of FPGA2_TTL : signal is true; + attribute syn_keep of FPGA3_TTL : signal is true; + attribute syn_keep of FPGA4_TTL : signal is true; + attribute syn_keep of FPGA1_CONNECTOR : signal is true; + attribute syn_keep of FPGA2_CONNECTOR : signal is true; + attribute syn_keep of FPGA3_CONNECTOR : signal is true; + attribute syn_keep of FPGA4_CONNECTOR : signal is true; + attribute syn_keep of ECL_IN : signal is true; + attribute syn_keep of NIM_IN : signal is true; + attribute syn_keep of JIN1 : signal is true; + attribute syn_keep of JIN2 : signal is true; + attribute syn_keep of JINLVDS : signal is true; + attribute syn_keep of DISCRIMINATOR_IN : signal is true; + attribute syn_keep of PWM_OUT : signal is true; + attribute syn_keep of JOUT1 : signal is true; + attribute syn_keep of JOUT2 : signal is true; + attribute syn_keep of JOUTLVDS : signal is true; + attribute syn_keep of JTTL : signal is true; + attribute syn_keep of TRG_FANOUT_ADDON : signal is true; + attribute syn_keep of LED_BANK : signal is true; + attribute syn_keep of LED_RJ_GREEN : signal is true; + attribute syn_keep of LED_RJ_RED : signal is true; + attribute syn_keep of LED_FAN_GREEN : signal is true; + attribute syn_keep of LED_FAN_ORANGE : signal is true; + attribute syn_keep of LED_FAN_RED : signal is true; + attribute syn_keep of LED_FAN_YELLOW : signal is true; + attribute syn_keep of FLASH_CLK : signal is true; + attribute syn_keep of FLASH_CS : signal is true; + attribute syn_keep of FLASH_DIN : signal is true; + attribute syn_keep of FLASH_DOUT : signal is true; + attribute syn_keep of PROGRAMN : signal is true; + attribute syn_keep of ENPIRION_CLOCK : signal is true; + attribute syn_keep of TEMPSENS : signal is true; + attribute syn_keep of LED_CLOCK_GREEN : signal is true; + attribute syn_keep of LED_CLOCK_RED : signal is true; + attribute syn_keep of LED_GREEN : signal is true; + attribute syn_keep of LED_ORANGE : signal is true; + attribute syn_keep of LED_RED : signal is true; + attribute syn_keep of LED_TRIGGER_GREEN : signal is true; + attribute syn_keep of LED_TRIGGER_RED : signal is true; + attribute syn_keep of LED_YELLOW : signal is true; + attribute syn_keep of TEST_LINE : signal is true; end entity; architecture trb3_central_arch of trb3_central is @@ -197,8 +294,6 @@ architecture trb3_central_arch of trb3_central is attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; - - --FPGA Test signal time_counter, time_counter2 : unsigned(31 downto 0); @@ -337,10 +432,10 @@ architecture trb3_central_arch of trb3_central is signal cts_ext_debug : std_logic_vector(31 downto 0); signal cts_ext_header : std_logic_vector(1 downto 0); - signal cts_rdo_additional_data : std_logic_vector(31+INCLUDE_TDC*32 downto 0); - signal cts_rdo_additional_write : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0'); - signal cts_rdo_additional_finished : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0'); - signal cts_rdo_trg_status_bits_additional : std_logic_vector(31+INCLUDE_TDC*32 downto 0) := (others => '0'); + signal cts_rdo_additional_data : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0); + signal cts_rdo_additional_write : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(cts_rdo_additional_ports-1 downto 0) := (others => '1'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(32*cts_rdo_additional_ports-1 downto 0) := (others => '0'); signal cts_rdo_trg_type : std_logic_vector(3 downto 0); signal cts_rdo_trg_code : std_logic_vector(7 downto 0); signal cts_rdo_trg_information : std_logic_vector(23 downto 0); @@ -526,10 +621,27 @@ architecture trb3_central_arch of trb3_central is signal cbm_phy_regio_write_ack_i : std_logic; signal cbm_phy_regio_unknown_addr_i : std_logic; - signal reset_fifo_i : std_logic_vector(3 downto 0) := (others => '0'); + signal cbm_sync_regio_read_en_i : std_logic; + signal cbm_sync_regio_write_en_i : std_logic; + signal cbm_sync_regio_status_data_i : std_logic_vector(31 downto 0); + signal cbm_sync_regio_addr_i : std_logic_vector(3 downto 0); + signal cbm_sync_regio_config_data_i : std_logic_vector(31 downto 0); + signal cbm_sync_regio_read_ack_i : std_logic; + signal cbm_sync_regio_write_ack_i : std_logic; + signal cbm_sync_regio_unknown_i : std_logic; + + signal cbm_sync_dlm_sensed_i : std_logic; + signal cbm_sync_pulser_i : std_logic; + + signal cbm_dlm_trigger_i : std_logic; + + --signal reset_fifo_i : std_logic_vector(3 downto 0) := (others => '0'); signal cbm_phy_debug : std_logic_vector(511 downto 0); + signal do_reboot_i : std_logic; + signal cbm_do_reboot_i : std_logic; + signal trb_crs_cbm_do_reboot_i : std_logic := '0'; begin assert not(USE_4_SFP = c_YES and INCLUDE_CBMNET = c_YES) report "CBMNET uses SFPs 1-4 and hence does not support USE_4_SFP" severity failure; assert not(INCLUDE_CBMNET = c_YES and INCLUDE_CTS = c_NO) report "CBMNET is supported only with CTS included" severity failure; @@ -589,34 +701,7 @@ begin -- CBMNet ETM gen_cbmnet_etm: if (ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) generate - --assert(INCLUDE_CBMNET = c_YES or not( ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES)) report "CBMNET DLM ETM requires the CBMNET stack (INCLUDE_CBMNET = c_YES)" severity failure; - THE_CBMNET_ETM: entity work.cbmnet_dlm_etm --- generic map (DLM_NUM => 10) - port map ( - CLK => clk_100_i, - RESET_IN => reset_i, - - TRG_SYNC_OUT => cts_ext_trigger, - - -- CBMNET DLM Port - CBMNET_CLK_IN => cbm_clk_i, - CBMNET_DLM_REC_IN => cbm_dlm_rec_type_i, - CBMNET_DLM_REC_VALID_IN => cbm_dlm_rec_va_i, - - --data output for read-out - TRIGGER_IN => cts_rdo_trg_data_valid, - DATA_OUT => cts_rdo_additional_data(31 downto 0), - WRITE_OUT => cts_rdo_additional_write(0), - STATUSBIT_OUT => cts_rdo_trg_status_bits_additional(31 downto 0), - FINISHED_OUT => cts_rdo_additional_finished(0), - - --Registers / Debug - CONTROL_REG_IN => cts_ext_control, - STATUS_REG_OUT => cts_ext_status, - HEADER_REG_OUT => cts_ext_header - --- DEBUG => cts_ext_debug - ); + cts_ext_trigger <= cbm_sync_dlm_sensed_i; end generate; GEN_CTS: if INCLUDE_CTS = c_YES generate @@ -757,7 +842,7 @@ begin port map ( CLK => clk_125_i, RESET => reset_i, - CLEAR => '0', + CLEAR => clear_i, --Internal Connection TX PHY_TXDATA_IN => cbm_data2link_i(15 downto 0), @@ -793,6 +878,7 @@ begin CTRL_OP => open, DEBUG_OUT => cbm_phy_debug ); + SFP_RATE_SEL(1) <= '1'; -- not supported by SFP, but in general, this should be the correct setting proc_debug_regio: process is variable addr : integer range 0 to 15; @@ -896,6 +982,7 @@ begin ); cbm_reset_n_i <= not cbm_reset_i when rising_edge(cbm_clk_i); + cbm_crc_error_cntr_clr_i <= cbm_reset_i; cbm_retrans_cntr_clr_i <= cbm_reset_i; cbm_retrans_error_cntr_clr_i <= cbm_reset_i; @@ -919,7 +1006,7 @@ begin ); -- TODO: just borrowed from CTS ... ! - JOUT2 <= "0" & clk_100_i & cbm_dlm2send_va_i & cbm_clk_i; + JOUT2 <= "000" & cbm_dlm_ref_rec_va_i; THE_CBMNET_READOUT: cbmnet_readout port map( @@ -976,7 +1063,7 @@ begin CBMNET_DATA2SEND_DATA_OUT => cbm_data2send_i -- out std_logic_vector(15 downto 0) ); - trb_reset_in <= reset_via_gbe; -- or MED_STAT_OP(4*16+13); --_delayed(2) +-- trb_reset_in <= reset_via_gbe; -- or MED_STAT_OP(4*16+13); --_delayed(2) LED_TRIGGER_GREEN <= not cbm_link_active_i; LED_TRIGGER_RED <= not cbm_dlm_rec_va_i; @@ -988,7 +1075,52 @@ begin med_stat_op(79 downto 64) <= (others => '0'); med_stat_debug(4*64+63 downto 4*64) <= (others => '0'); - SFP_TXDIS(7 downto 2) <= (others => '1'); + SFP_TXDIS(7 downto 2) <= (others => '1'); + + THE_SYNC_MODULE: cbmnet_sync_module port map ( + -- TRB + TRB_CLK_IN => clk_100_i, -- in std_logic; + TRB_RESET_IN => reset_i, -- in std_logic; + TRB_TRIGGER_OUT => cbm_dlm_trigger_i, -- out std_logic; + + --data output for read-out + TRB_TRIGGER_IN => cts_trigger_out, -- in std_logic; -- TODO: we may want to feed the reference time via an external input + TRB_RDO_VALID_IN => cts_rdo_trg_data_valid, + TRB_RDO_DATA_OUT => cts_rdo_additional_data(32*cts_rdo_additional_ports-1 downto 32*cts_rdo_additional_ports-32), -- out std_logic_vector(31 downto 0); + TRB_RDO_WRITE_OUT => cts_rdo_additional_write(cts_rdo_additional_ports-1), -- out std_logic; +-- TRB_RDO_STATUSBIT_OUT => cts_rdo_add(32*cts_rdo_additional_ports-1 downto 32*cts_rdo_additional_ports-32), -- out std_logic_vector(31 downto 0); + TRB_RDO_FINISHED_OUT => cts_rdo_additional_finished(cts_rdo_additional_ports-1), -- out std_logic; + + -- reg io + TRB_REGIO_ADDR_IN(15 downto 4) => x"000", + TRB_REGIO_ADDR_IN(3 downto 0) => cbm_sync_regio_addr_i, -- in std_logic_vector(15 downto 0); + TRB_REGIO_DATA_IN => cbm_sync_regio_config_data_i, -- in std_logic_vector(31 downto 0); + TRB_REGIO_READ_ENABLE_IN => cbm_sync_regio_read_en_i, -- in std_logic; + TRB_REGIO_WRITE_ENABLE_IN => cbm_sync_regio_write_en_i, -- in std_logic; + TRB_REGIO_DATA_OUT => cbm_sync_regio_status_data_i, -- out std_logic_vector(31 downto 0); + TRB_REGIO_DATAREADY_OUT => cbm_sync_regio_read_ack_i, -- out std_logic; + TRB_REGIO_WRITE_ACK_OUT => cbm_sync_regio_write_ack_i, -- out std_logic; + TRB_REGIO_UNKNOWN_ADDR_OUT => cbm_sync_regio_unknown_i, -- out std_logic; + + -- CBMNET + CBM_CLK_IN => cbm_clk_i, -- in std_logic; + CBM_RESET_IN => cbm_reset_i, -- in std_logic; + CBM_PHY_BARREL_SHIFTER_POS_IN => x"0", -- in std_logic_vector(3 downto 0); + + -- DLM port + CBM_DLM_REC_IN => cbm_dlm_rec_type_i, -- in std_logic_vector(3 downto 0); + CBM_DLM_REC_VALID_IN => cbm_dlm_rec_va_i, -- in std_logic; + CBM_DLM_SENSE_OUT => cbm_sync_dlm_sensed_i, -- out std_logic; + CBM_PULSER_OUT => cbm_sync_pulser_i, -- out std_logic; -- connect to TDC + + -- Ctrl port + CBM_CTRL_DATA_IN => cbm_ctrl_rec_i, -- in std_logic_vector(15 downto 0); + CBM_CTRL_DATA_START_IN => cbm_ctrl_rec_start_i, -- in std_logic; + CBM_CTRL_DATA_END_IN => cbm_ctrl_rec_end_i, -- in std_logic; + CBM_CTRL_DATA_STOP_OUT => cbm_ctrl_rec_stop_i, -- out std_logic; + + DEBUG_OUT => open -- out std_logic_vector(31 downto 0) + ); end generate; GEN_NO_CBMNET: if INCLUDE_CBMNET = c_NO generate @@ -1009,6 +1141,16 @@ begin trb_reset_in <= reset_via_gbe or MED_STAT_OP(4*16+13); --_delayed(2) LED_TRIGGER_GREEN <= not med_stat_op(4*16+9); LED_TRIGGER_RED <= not (med_stat_op(4*16+11) or med_stat_op(4*16+10)); + + cbm_dlm_trigger_i <= '0'; + + cbm_sync_regio_unknown_i <= '1'; + cbm_sync_regio_read_ack_i <= cbm_sync_regio_read_en_i; + cbm_sync_regio_write_ack_i <= cbm_sync_regio_write_en_i; + + cbm_phy_regio_unknown_addr_i <= '1'; + cbm_phy_regio_dataready_i <= cbm_phy_regio_read_enable_i; + cbm_phy_regio_write_ack_i <= cbm_phy_regio_write_enable_i; end generate; @@ -1035,19 +1177,18 @@ THE_RESET_HANDLER : trb_net_reset_handler DEBUG_OUT => open ); +trb_reset_in <= reset_via_gbe or MED_STAT_OP(4*16+13); --_delayed(2) +reset_i <= reset_i_temp; -- or trb_reset_in; -reset_fifo_i <= reset_i_temp & reset_fifo_i(reset_fifo_i'high downto 1) when rising_edge(clk_100_i); -reset_i <= reset_fifo_i(0) when rising_edge(clk_100_i); --- reset_i <= reset_i_temp; -- or trb_reset_in; - -process begin - wait until rising_edge(clk_100_i); - if reset_i = '1' then - reset_via_gbe_delayed <= "000"; - elsif timer_ticks(0) = '1' then - reset_via_gbe_delayed <= reset_via_gbe_delayed(1 downto 0) & reset_via_gbe; - end if; - end process; +-- +-- process begin +-- wait until rising_edge(clk_100_i); +-- if reset_i = '1' then +-- reset_via_gbe_delayed <= "000"; +-- elsif timer_ticks(0) = '1' then +-- reset_via_gbe_delayed <= reset_via_gbe_delayed(1 downto 0) & reset_via_gbe; +-- end if; +-- end process; --------------------------------------------------------------------------- @@ -1469,9 +1610,9 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 13, - PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", 6 => x"c000", 7 => x"c100", 8 => x"c200", 9 => x"c300", 10 => x"c800", 11 => x"a800", 12 => x"a880", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 11, 5 => 0, 6 => 7, 7 => 5, 8 => 7, 9 => 7, 10 => 3, 11 => 7, 12 => 7, others => 0) + PORT_NUMBER => 14, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8100", 3 => x"8300", 4 => x"a000", 5 => x"d300", 6 => x"c000", 7 => x"c100", 8 => x"c200", 9 => x"c300", 10 => x"c800", 11 => x"a800", 12 => x"a880", 13 => x"a900", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 8, 3 => 8, 4 => 11, 5 => 0, 6 => 7, 7 => 5, 8 => 7, 9 => 7, 10 => 3, 11 => 7, 12 => 7, 13 => 4, others => 0) ) port map( CLK => clk_100_i, @@ -1647,6 +1788,20 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_WRITE_ACK_IN(12) => cbm_phy_regio_write_ack_i, BUS_NO_MORE_DATA_IN(12) => '0', BUS_UNKNOWN_ADDR_IN(12) => cbm_phy_regio_unknown_addr_i, + + --CBMNet (sync) + BUS_READ_ENABLE_OUT(13) => cbm_sync_regio_read_en_i, + BUS_WRITE_ENABLE_OUT(13) => cbm_sync_regio_write_en_i, + BUS_DATA_OUT(13*32+31 downto 13*32) => cbm_sync_regio_config_data_i, + BUS_ADDR_OUT(13*16+3 downto 13*16) => cbm_sync_regio_addr_i, + BUS_ADDR_OUT(13*16+15 downto 13*16+4)=> open, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(13*32+31 downto 13*32) => cbm_sync_regio_status_data_i, + BUS_DATAREADY_IN(13) => cbm_sync_regio_read_ack_i, + BUS_WRITE_ACK_IN(13) => cbm_sync_regio_write_ack_i, + BUS_NO_MORE_DATA_IN(13) => '0', + BUS_UNKNOWN_ADDR_IN(13) => cbm_sync_regio_unknown_i, + STAT_DEBUG => open ); @@ -1712,10 +1867,33 @@ THE_FPGA_REBOOT : fpga_reboot port map( CLK => clk_100_i, RESET => reset_i, - DO_REBOOT => common_ctrl_regs(15), + DO_REBOOT => do_reboot_i, PROGRAMN => PROGRAMN ); +do_reboot_i <= trb_crs_cbm_do_reboot_i or common_ctrl_regs(15); + +GEN_CBM_REBOOT: if INCLUDE_CBMNET = c_YES generate + CBM_REBOOT_PROC: process is + begin + wait until rising_edge(cbm_clk_i); + cbm_do_reboot_i <= '0'; + if cbm_dlm_rec_type_i = x"f" and cbm_dlm_rec_va_i = '1' then + cbm_do_reboot_i <= '1'; + end if; + end process; + + THE_REBOOT_SENSE_SYNC: pos_edge_strech_sync port map ( + IN_CLK_IN => cbm_clk_i, OUT_CLK_IN => clk_100_i, + DATA_IN => cbm_do_reboot_i, + DATA_OUT => trb_crs_cbm_do_reboot_i + ); +end generate; + + + + + ------------------------------------------------------------------------------- -- TDC @@ -1800,6 +1978,8 @@ gen_TDC : if INCLUDE_TDC = c_YES generate CONTROL_REG_IN => tdc_ctrl_reg ); + tdc_inputs(1 downto 0) <= cbm_sync_dlm_sensed_i & cbm_sync_pulser_i ; + PROC_TDC_CTRL_REG : process variable pos : integer; begin @@ -1861,8 +2041,8 @@ process begin -- output time reference synchronously to the 200MHz clock -- in order to reduce jitter wait until rising_edge(clk_200_i); - TRIGGER_OUT <= cts_trigger_out; - TRIGGER_OUT2 <= cts_trigger_out; + TRIGGER_OUT <= cts_trigger_out; + TRIGGER_OUT2 <= cts_trigger_out; TRG_FANOUT_ADDON <= cts_trigger_out; end process; @@ -1925,26 +2105,22 @@ end process; -- LED_RED <= '1'; -LED_GREEN <= debug(0); +LED_GREEN <= debug(0); LED_ORANGE <= debug(1); -LED_RED <= debug(2); -LED_YELLOW <= link_ok; --debug(3); +LED_RED <= debug(2) when INCLUDE_CBMNET=c_NO else cbm_link_active_i; +LED_YELLOW <= link_ok when INCLUDE_CBMNET=c_NO else cbm_dlm_ref_rec_va_i; + + + --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- --- TEST_LINE(7 downto 0) <= med_data_in(7 downto 0); --- TEST_LINE(8) <= med_dataready_in(0); --- TEST_LINE(9) <= med_dataready_out(0); - TEST_LINE(15 downto 0) <= tdc_debug; - TEST_LINE(16) <= CLK_EXT(3); --this prevents adding an input register in the CBM MBS input module - TEST_LINE(31 downto 17) <= (others => '0'); --- TEST_LINE(31 downto 0) <= cts_ext_debug; end architecture; \ No newline at end of file diff --git a/cts/trb3_central_constraints_2.lpf b/cts/trb3_central_constraints_2.lpf index a1b7f47..8bcdabb 100644 --- a/cts/trb3_central_constraints_2.lpf +++ b/cts/trb3_central_constraints_2.lpf @@ -5,283 +5,271 @@ BLOCK RD_DURING_WR_PATHS ; ################################################################# # Basic Settings ################################################################# - - SYSCONFIG MCCLK_FREQ = 20; - - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; - FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; - FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; +SYSCONFIG MCCLK_FREQ=20 ; +FREQUENCY PORT "CLK_PCLK_RIGHT" 200.000000 MHz ; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +FREQUENCY PORT "CLK_GPLL_RIGHT" 125.000000 MHz ; +FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; # FREQUENCY PORT CLK_EXT_3 10 MHz; # FREQUENCY PORT CLK_EXT_4 10 MHz; - +FREQUENCY NET "clk_200_i" 200.000000 MHz ; +FREQUENCY NET "clk_100_i_c" 100.000000 MHz ; +FREQUENCY NET "cts_trigger_out" 100.000000 MHz ; +FREQUENCY NET "GBE/serdes_rx_clk_c" 125.000000 MHz ; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch1" 100.000000 MHz ; +FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch0" 100.000000 MHz ; +FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/clk_tx_full_i" 250.000000 MHz ; +FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/un1_THE_CBM_PHY" 250.000000 MHz ; +FREQUENCY NET "cbm_clk_i_c" 125.000000 MHz ; ################################################################# # Reset Nets ################################################################# -GSR_NET NET "GSR_N"; - - +GSR_NET NET "GSR_N"; ################################################################# # Locate Serdes and media interfaces ################################################################# -LOCATE COMP "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSD_INST" SITE "PCSB"; -LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; - -LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ; -LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; - -MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset_*" 30 ns; -MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30 ns; - - -REGION "MEDIA_UPLINK" "R92C90" 22 76; +LOCATE COMP "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; +MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset[*]" 30.000000 ns ; +MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; +REGION "MEDIA_UPLINK" "R92C90" 22 76 DEVSIZE; LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; - #REGION "MEDIA_ONBOARD" "R90C122" 20 40; - -MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; - +#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; +MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50.000000 ns ; #SPI Interface -REGION "REGION_SPI" "R9C108D" 20 20 DEVSIZE; -LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; -LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - +REGION "REGION_SPI" "R9C95D" 20 20 DEVSIZE; +LOCATE UGROUP "THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; +#LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; #REGION "REGION_CTS" "R42C2D" 37 57 DEVSIZE; # UGROUP "cts_group" # BLKNAME THE_CTS; # LOCATE UGROUP "cts_group" REGION "REGION_CTS"; -MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20 ns; -MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20 ns; - -# CBMNet -FREQUENCY NET "gen_cbmnet_THE_CBM_PHY/clk_tx_full_i" 250 MHz ; -FREQUENCY NET "gen_cbmnet_THE_CBM_PHY/THE_RX_GEAR/clk_125_i_i" 125 MHz ; -FREQUENCY NET "cbm_clk_i" 125 MHz ; - -DEFINE BUS "cbm_rx_data" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[0]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[1]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[2]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[3]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[4]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[5]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[6]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[7]" NET "gen_cbmnet_THE_CBM_PHY/rx_data_from_serdes_i[8]"; -DEFINE BUS "cbm_tx_data" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[0]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[1]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[2]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[3]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[4]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[5]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[6]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[7]" NET "gen_cbmnet_THE_CBM_PHY/tx_data_to_serdes_i[8]"; - -PRIORITIZE BUS "cbm_rx_data" 91; -PRIORITIZE BUS "cbm_tx_data" 90; - +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20.000000 ns ; +MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20.000000 ns ; #TrbNet Hub -REGION "REGION_IOBUF" "R40C40D" 55 75 DEVSIZE; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_3_MPLEX/MUX_group" REGION "REGION_IOBUF" ; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_4_MPLEX/MUX_group" REGION "REGION_IOBUF" ; - -LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic_1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic_0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_hub_logic_3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/GEN_IBUF_THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_0_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_1_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_2_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_0_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_1_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_3_gen_iobufs_3_gen_iobuf_IOBUF/genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; -LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; - -#GbE Part - +REGION "REGION_IOBUF" "R35C35D" 65 85 DEVSIZE; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF1.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/genREPLYOBUF2.gen_REPLYOBUF3.REPLYOBUF/OBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.3.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.4.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; +LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; #GbE Part - -FREQUENCY NET "GBE/serdes_clk_125" 125.000000 MHz ; -FREQUENCY NET "GBE/CLK_125_OUT_inferred_clock" 125.00 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_txfullclk" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/ff_rxfullclk" 125.000000 MHz ; - -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_tx_clock" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/sd_rx_clock" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/refclkcore" 125.000000 MHz ; - -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/CLK_RX_OUT" 125.000000 MHz ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/CLK_TX_OUT_inferred_clock" 125.000000 MHz ; - -FREQUENCY PORT "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_TX_F_CLK" 125.000000 MHz; -FREQUENCY PORT "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSC_INST.FF_RX_F_CLK" 125.000000 MHz; - - -UGROUP "tsmac" - BLKNAME GBE/imp_gen_MAC - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SGMII_GBE_PCS - BLKNAME GBE/FRAME_RECEIVER - BLKNAME GBE/FRAME_TRANSMITTER; +UGROUP "tsmac" + BLKNAME GBE/imp_gen.MAC + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS + BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER + BLKNAME GBE/FRAME_TRANSMITTER; UGROUP "controllers" - BLKNAME GBE/MAIN_CONTROL - BLKNAME GBE/RECEIVE_CONTROLLER - BLKNAME GBE/TRANSMIT_CONTROLLER; + BLKNAME GBE/main_gen.MAIN_CONTROL + BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER + BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER; UGROUP "gbe_rx_tx" - BLKNAME GBE/FRAME_CONSTRUCTOR - BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG - BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR -# BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/PACKET_CONSTRUCTOR -# BLKNAME GBE/MAIN_CONTROL/protocol_selector/TrbNetData/THE_IPU_INTERFACE - BLKNAME GBE/setup_imp_gen_SETUP; + BLKNAME GBE/FRAME_CONSTRUCTOR + BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG + BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR + BLKNAME GBE/setup_imp_gen.SETUP; - -#REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; + #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; #REGION "MED0" "R81C30D" 34 40 DEVSIZE; #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; -FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ; #REGION "GBE_MAIN_REGION" "R50C64C" 65 64 DEVSIZE; - #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ; #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ; - - -REGION "MED0" "R69C4D" 35 40 DEVSIZE; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; -FREQUENCY NET "GBE/serdes_clk_125_c" 125.000000 MHz ; -#LOCATE UGROUP "tsmac" REGION "MED0" ; -BLOCK JTAGPATHS ; UGROUP "sd_tx_to_pcs" - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_0 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_1 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_2 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_3 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_4 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_5 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_6 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q_7 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; UGROUP "sd_rx_to_pcs" - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_0 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_1 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_2 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_3 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_4 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_5 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_6 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q_7 - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q - BLKNAME GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7] + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; UGROUP "pcs_tx_to_mac" BLKNAME GBE/pcs_tx_en_q BLKNAME GBE/pcs_tx_en_qq BLKNAME GBE/pcs_tx_er_q BLKNAME GBE/pcs_tx_er_qq - BLKNAME GBE/pcs_txd_q_0 - BLKNAME GBE/pcs_txd_q_1 - BLKNAME GBE/pcs_txd_q_2 - BLKNAME GBE/pcs_txd_q_3 - BLKNAME GBE/pcs_txd_q_4 - BLKNAME GBE/pcs_txd_q_5 - BLKNAME GBE/pcs_txd_q_6 - BLKNAME GBE/pcs_txd_q_7 - BLKNAME GBE/pcs_txd_qq_0 - BLKNAME GBE/pcs_txd_qq_1 - BLKNAME GBE/pcs_txd_qq_2 - BLKNAME GBE/pcs_txd_qq_3 - BLKNAME GBE/pcs_txd_qq_4 - BLKNAME GBE/pcs_txd_qq_5 - BLKNAME GBE/pcs_txd_qq_6 - BLKNAME GBE/pcs_txd_qq_7; + BLKNAME GBE/pcs_txd_q[0] + BLKNAME GBE/pcs_txd_q[1] + BLKNAME GBE/pcs_txd_q[2] + BLKNAME GBE/pcs_txd_q[3] + BLKNAME GBE/pcs_txd_q[4] + BLKNAME GBE/pcs_txd_q[5] + BLKNAME GBE/pcs_txd_q[6] + BLKNAME GBE/pcs_txd_q[7] + BLKNAME GBE/pcs_txd_qq[0] + BLKNAME GBE/pcs_txd_qq[1] + BLKNAME GBE/pcs_txd_qq[2] + BLKNAME GBE/pcs_txd_qq[3] + BLKNAME GBE/pcs_txd_qq[4] + BLKNAME GBE/pcs_txd_qq[5] + BLKNAME GBE/pcs_txd_qq[6] + BLKNAME GBE/pcs_txd_qq[7]; UGROUP "pcs_rx_to_mac" BLKNAME GBE/pcs_rx_en_q BLKNAME GBE/pcs_rx_en_qq BLKNAME GBE/pcs_rx_er_q BLKNAME GBE/pcs_rx_er_qq - BLKNAME GBE/pcs_rxd_q_0 - BLKNAME GBE/pcs_rxd_q_1 - BLKNAME GBE/pcs_rxd_q_2 - BLKNAME GBE/pcs_rxd_q_3 - BLKNAME GBE/pcs_rxd_q_4 - BLKNAME GBE/pcs_rxd_q_5 - BLKNAME GBE/pcs_rxd_q_6 - BLKNAME GBE/pcs_rxd_q_7 - BLKNAME GBE/pcs_rxd_qq_0 - BLKNAME GBE/pcs_rxd_qq_1 - BLKNAME GBE/pcs_rxd_qq_2 - BLKNAME GBE/pcs_rxd_qq_3 - BLKNAME GBE/pcs_rxd_qq_4 - BLKNAME GBE/pcs_rxd_qq_5 - BLKNAME GBE/pcs_rxd_qq_6 - BLKNAME GBE/pcs_rxd_qq_7; -USE PRIMARY NET "CLK_GPLL_RIGHT_c" ; -FREQUENCY NET "GBE/serdes_rx_clk_c" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_0" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_1" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_2" 125.000000 MHz PAR_ADJ 25.000000 ; -FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/FF_TX_F_CLK_3" 125.000000 MHz PAR_ADJ 25.000000 ; - -MAXDELAY NET "GBE/pcs_rx_en_q" 1.5 ns; -MAXDELAY NET "GBE/pcs_rx_er_q" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_0" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_1" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_2" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_3" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_4" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_5" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_6" 1.5 ns; -MAXDELAY NET "GBE/pcs_rxd_q_7" 1.5 ns; + BLKNAME GBE/pcs_rxd_q[0] + BLKNAME GBE/pcs_rxd_q[1] + BLKNAME GBE/pcs_rxd_q[2] + BLKNAME GBE/pcs_rxd_q[3] + BLKNAME GBE/pcs_rxd_q[4] + BLKNAME GBE/pcs_rxd_q[5] + BLKNAME GBE/pcs_rxd_q[6] + BLKNAME GBE/pcs_rxd_q[7] + BLKNAME GBE/pcs_rxd_qq[0] + BLKNAME GBE/pcs_rxd_qq[1] + BLKNAME GBE/pcs_rxd_qq[2] + BLKNAME GBE/pcs_rxd_qq[3] + BLKNAME GBE/pcs_rxd_qq[4] + BLKNAME GBE/pcs_rxd_qq[5] + BLKNAME GBE/pcs_rxd_qq[6] + BLKNAME GBE/pcs_rxd_qq[7]; + +UGROUP "GBE_SERDES_group" BBOX 10 67 + BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES; +LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ; + +MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ; +MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ; DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q" "GBE/pcs_rx_er_q" - "GBE/pcs_rxd_q_*"; + "GBE/pcs_rxd_q*"; INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ; -PRIORITIZE NET "GBE/pcs_rx_en_q" 100; -PRIORITIZE NET "GBE/pcs_rx_er_q" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_0" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_1" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_2" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_3" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_4" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_5" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_6" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_7" 100; -PRIORITIZE NET "GBE/pcs_rxd_q_0" 100; -PRIORITIZE NET "GBE/serdes_rx_clk_c" 80; +PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ; +PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ; +PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; +PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; + +BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; +BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; + +# CBMNET +LOCATE COMP "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; +DEFINE BUS cbm_rx_data + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[0]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[1]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[2]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[3]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[4]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[5]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[6]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[7]" + NET "GEN_CBMNET.THE_CBM_PHY/rx_data_from_serdes_i[8]"; +DEFINE BUS cbm_tx_data + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[0]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[1]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[2]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[3]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[4]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[5]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[6]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[7]" + NET "GEN_CBMNET.THE_CBM_PHY/tx_data_to_serdes_i[8]"; + +PRIORITIZE BUS "cbm_rx_data" 100 ; +PRIORITIZE BUS "cbm_tx_data" 100 ; + +MULTICYCLE TO CELL "GEN_CBMNET.THE_CBM_PHY/THE_TX_GEAR/data_in_buf250_0_i*" 2 X; +MULTICYCLE TO CELL "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/delay_clock_buf_i" 2 X; +MULTICYCLE TO CELL "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/data_out_buf125_i*" 2 X; + +BLOCK NET "cbm_phy_debug*" ; +REGION "REGIONTDCPLACEHOLDER" "R2C115D" 31 67 DEVSIZE; +PROHIBIT REGION "REGIONTDCPLACEHOLDER" ; + +#PROHIBIT PRIMARY NET "GEN_CBMNET.THE_CBM_PHY/un1_THE_CBM_PHY" ; +#PROHIBIT SECONDARY NET "GEN_CBMNET.THE_CBM_PHY/un1_THE_CBM_PHY" ; +#PROHIBIT PRIMARY NET "GEN_CBMNET.THE_CBM_PHY/clk_tx_full_i" ; +#PROHIBIT SECONDARY NET "GEN_CBMNET.THE_CBM_PHY/clk_tx_full_i" ; + +UGROUP "CBM_PHY_UGROUP" BBOX 13 26 + BLKNAME GEN_CBMNET.THE_CBM_PHY + BLKNAME GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR + BLKNAME GEN_CBMNET.THE_CBM_PHY/THE_TX_GEAR; +LOCATE UGROUP "CBM_PHY_UGROUP" SITE "R105C110D" ; + +UGROUP "CBMNET_group" BBOX 36 50 +# BLKNAME GEN_CBMNET.THE_CBMNET_READOUT + BLKNAME GEN_CBMNET.THE_CBM_ENDPOINT + BLKNAME GEN_CBMNET.THE_DLM_REFLECT + BLKNAME GEN_CBMNET.THE_SYNC_MODULE; +LOCATE UGROUP "CBMNET_group" SITE "R80C85D" ; -BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ; -BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ; diff --git a/cts/trb3_central_syn.fdc b/cts/trb3_central_syn.fdc index 95e488c..3fac7d4 100644 --- a/cts/trb3_central_syn.fdc +++ b/cts/trb3_central_syn.fdc @@ -2,8 +2,8 @@ # Synopsys, Inc. constraint file # /d/jspc29/mpenschuck/trb3/cts/trb3_central_syn.fdc -# Written on Sun Jul 27 13:52:03 2014 -# by Synplify Premier, I-2013.09-SP1 FDC Constraint Editor +# Written on Wed Sep 17 21:53:44 2014 +# by Synplify Pro, I-2013.09-SP1 FDC Constraint Editor # Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. # These sections are generated from SCOPE spreadsheet tabs. @@ -14,8 +14,8 @@ ###==== END Collections ###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock {n:GEN_CBMNET\.THE_CBM_PHY.THE_RX_GEAR.CLK_125_OUT} -period {8} -create_clock {n:THE_MAIN_PLL.CLKOP} -period {10} +create_clock -name {rclk125} {n:GEN_CBMNET\.THE_CBM_PHY.THE_RX_GEAR.CLK_125_OUT} -period {8} +create_clock -name {clk100} {n:THE_MAIN_PLL.CLKOP} -period {10} create_clock {n:THE_MAIN_PLL.CLKOK} -period {5} create_clock {n:GEN_CBMNET\.THE_CBM_PHY.THE_SERDES.rx_full_clk_ch0} -period {4} create_clock {n:GEN_CBMNET\.THE_CBM_PHY.THE_SERDES.tx_full_clk_ch0} -period {4} @@ -24,8 +24,8 @@ create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch1} create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch2} -period {10} create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch3} -period {10} create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_tx_ch} -period {10} -create_clock {n:GEN_CTS\.THE_CTS.TIME_REFERENCE_OUT} -period {10} -create_clock {n:GBE.imp_gen\.serdes_intclk_gen\.PCS_SERDES.clk_int\.SERDES_GBE.rx_full_clk_ch3} -period {4} +create_clock -name {refTime} {n:GEN_CTS\.THE_CTS.TIME_REFERENCE_OUT} -period {10} +create_clock {n:GBE.imp_gen\.serdes_intclk_gen\.PCS_SERDES.clk_int\.SERDES_GBE.rx_full_clk_ch3} -period {8} create_clock {p:CLK_GPLL_RIGHT} -period {8} ###==== END Clocks @@ -36,10 +36,9 @@ create_clock {p:CLK_GPLL_RIGHT} -period {8} ###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) ###==== END Inputs/Outputs -###==== BEGIN Registers - (Populated from tab in SCOPE, do not edit) -###==== END Registers ###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +set_false_path -disable ###==== END "Delay Paths" ###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) @@ -53,3 +52,7 @@ create_clock {p:CLK_GPLL_RIGHT} -period {8} + + + +