From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Sat, 12 Nov 2022 21:47:29 +0000 (+0100)
Subject: registered debug out
X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=71e9bbf3defabf3fd39d6d6f51b4d5319be34d9c;p=trb3sc.git

registered debug out
---

diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj
index f56f38b..c0b3f2d 100644
--- a/gbe_hub/trb3sc_gbe_hub.prj
+++ b/gbe_hub/trb3sc_gbe_hub.prj
@@ -215,5 +215,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72_s.vhd"
 
 add_file -vhdl -lib work "./trb3sc_gbe_hub.vhd"
 
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/odr_dbg.vhd"
+add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ddr_out.vhd"
 
 
diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd
index fb0b753..78a50b6 100644
--- a/gbe_hub/trb3sc_gbe_hub.vhd
+++ b/gbe_hub/trb3sc_gbe_hub.vhd
@@ -68,18 +68,12 @@ entity trb3sc_gbe_hub is
     TEST_LINE            : out std_logic_vector(15 downto 0)
   );
 
-
-  attribute syn_useioff                  : boolean;
-  attribute syn_useioff of FLASH_CLK  : signal is true;
-  attribute syn_useioff of FLASH_CS   : signal is true;
-  attribute syn_useioff of FLASH_IN   : signal is true;
-  attribute syn_useioff of FLASH_OUT  : signal is true;
-
 end entity;
 
 architecture trb3sc_gbe_hub_arch of trb3sc_gbe_hub is
   attribute syn_keep                : boolean;
   attribute syn_preserve            : boolean;
+  attribute syn_useioff             : boolean;
   
   signal clk_sys                    : std_logic;
   signal clear_i                    : std_logic;
@@ -100,6 +94,11 @@ architecture trb3sc_gbe_hub_arch of trb3sc_gbe_hub is
   signal flash_miso_i               : std_logic;
   signal flash_mosi_i               : std_logic;
 
+  attribute syn_useioff of FLASH_CLK  : signal is true;
+  attribute syn_useioff of FLASH_CS   : signal is true;
+  attribute syn_useioff of FLASH_IN   : signal is true;
+  attribute syn_useioff of FLASH_OUT  : signal is true;
+
   signal common_stat_reg            : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0');
   signal common_ctrl_reg            : std_logic_vector(std_COMCTRLREG*32-1 downto 0);
 
@@ -420,7 +419,25 @@ begin
   -- 8 : fifo_eof
   -- 7..0: data
 
-  DBG(31 downto 0)  <= debug_wrapper(31 downto 0);
+  THE_LA_SIGNALS: entity odr_dbg
+  port map(
+    CLK     => master_clk, 
+    CLKOUT  => open, 
+    RESET   => '0', 
+    D       => debug_wrapper(31 downto 0),
+    DOUT    => DBG(31 downto 0)
+  );
+  
+--  THE_LA_CLK: entity ddr_out
+--  port map(
+--    CLK    => master_clk,
+--    CLKOUT => open,
+--    DA     => (others => '1'),
+--    DB     => (others => '0'),
+--    Q      => DBG(33 downto 33)
+--  );
+
+--  DBG(31 downto 0)  <= debug_wrapper(31 downto 0);
   DBG(32)           <= '0';
   DBG(33)           <= master_clk;
   
@@ -1063,7 +1080,7 @@ begin
   LED_SFP_GREEN(1)   <= not status_raw(13 * 8 + 7); --'0'; -- D1
   LED_SFP_RED(1)     <= not status_raw(13 * 8 + 2); --'0';
   
-  LED_WHITE(1)       <= not debug_wrapper(31); --oob_3_reg(0); --'0';
+  LED_WHITE(1)       <= not oob_3_reg(0); --'0';
   LED_WHITE(0)       <= not status(0); --'0';
 
   LED_RJ_GREEN(0)    <= not status_raw(0 * 8 + 7); -- A0