From: Andreas Neiser Date: Tue, 10 Feb 2015 09:15:44 +0000 (+0100) Subject: ADC: Add 65MHz PLL to project X-Git-Url: https://jspc29.x-matter.uni-frankfurt.de/git/?a=commitdiff_plain;h=7303c8a1b7841821eb25d86522ae1ad6a4ea7c43;p=trb3.git ADC: Add 65MHz PLL to project --- diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj index cac1d07..62fcb01 100644 --- a/ADC/trb3_periph_adc.prj +++ b/ADC/trb3_periph_adc.prj @@ -142,6 +142,7 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.v add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "../base/cores/pll_in200_out40.vhd" +add_file -vhdl -lib "work" "../base/cores/pll_in200_out65.vhd" add_file -vhdl -lib "work" "../base/cores/pll_adc10bit.vhd" add_file -vhdl -lib "work" "../base/cores/dqsinput_7x5.vhd" add_file -vhdl -lib "work" "../base/cores/dqsinput_5x5.vhd"